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5
6#include <linux/bitfield.h>
7#include <linux/clk.h>
8#include <sound/pcm_params.h>
9#include <sound/soc.h>
10#include <sound/soc-dai.h>
11
12#include "aiu.h"
13#include "aiu-fifo.h"
14
15#define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
16#define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
17#define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
18#define AIU_I2S_SOURCE_DESC_MODE_SPLIT BIT(11)
19#define AIU_MEM_I2S_MASKS_IRQ_BLOCK GENMASK(31, 16)
20#define AIU_MEM_I2S_CONTROL_MODE_16BIT BIT(6)
21#define AIU_MEM_I2S_BUF_CNTL_INIT BIT(0)
22#define AIU_RST_SOFT_I2S_FAST BIT(0)
23
24#define AIU_FIFO_I2S_BLOCK 256
25
26static struct snd_pcm_hardware fifo_i2s_pcm = {
27 .info = (SNDRV_PCM_INFO_INTERLEAVED |
28 SNDRV_PCM_INFO_MMAP |
29 SNDRV_PCM_INFO_MMAP_VALID |
30 SNDRV_PCM_INFO_PAUSE),
31 .formats = AIU_FORMATS,
32 .rate_min = 5512,
33 .rate_max = 192000,
34 .channels_min = 2,
35 .channels_max = 8,
36 .period_bytes_min = AIU_FIFO_I2S_BLOCK,
37 .period_bytes_max = AIU_FIFO_I2S_BLOCK * USHRT_MAX,
38 .periods_min = 2,
39 .periods_max = UINT_MAX,
40
41
42 .buffer_bytes_max = 1 * 1024 * 1024,
43};
44
45static int aiu_fifo_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
46 struct snd_soc_dai *dai)
47{
48 struct snd_soc_component *component = dai->component;
49
50 switch (cmd) {
51 case SNDRV_PCM_TRIGGER_START:
52 case SNDRV_PCM_TRIGGER_RESUME:
53 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
54 snd_soc_component_write(component, AIU_RST_SOFT,
55 AIU_RST_SOFT_I2S_FAST);
56 snd_soc_component_read(component, AIU_I2S_SYNC);
57 break;
58 }
59
60 return aiu_fifo_trigger(substream, cmd, dai);
61}
62
63static int aiu_fifo_i2s_prepare(struct snd_pcm_substream *substream,
64 struct snd_soc_dai *dai)
65{
66 struct snd_soc_component *component = dai->component;
67 int ret;
68
69 ret = aiu_fifo_prepare(substream, dai);
70 if (ret)
71 return ret;
72
73 snd_soc_component_update_bits(component,
74 AIU_MEM_I2S_BUF_CNTL,
75 AIU_MEM_I2S_BUF_CNTL_INIT,
76 AIU_MEM_I2S_BUF_CNTL_INIT);
77 snd_soc_component_update_bits(component,
78 AIU_MEM_I2S_BUF_CNTL,
79 AIU_MEM_I2S_BUF_CNTL_INIT, 0);
80
81 return 0;
82}
83
84static int aiu_fifo_i2s_hw_params(struct snd_pcm_substream *substream,
85 struct snd_pcm_hw_params *params,
86 struct snd_soc_dai *dai)
87{
88 struct snd_soc_component *component = dai->component;
89 struct aiu_fifo *fifo = dai->playback_dma_data;
90 unsigned int val;
91 int ret;
92
93 ret = aiu_fifo_hw_params(substream, params, dai);
94 if (ret)
95 return ret;
96
97 switch (params_physical_width(params)) {
98 case 16:
99 val = AIU_MEM_I2S_CONTROL_MODE_16BIT;
100 break;
101 case 32:
102 val = 0;
103 break;
104 default:
105 dev_err(dai->dev, "Unsupported physical width %u\n",
106 params_physical_width(params));
107 return -EINVAL;
108 }
109
110 snd_soc_component_update_bits(component, AIU_MEM_I2S_CONTROL,
111 AIU_MEM_I2S_CONTROL_MODE_16BIT,
112 val);
113
114
115 val = params_period_bytes(params) / fifo->fifo_block;
116 val = FIELD_PREP(AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
117 snd_soc_component_update_bits(component, AIU_MEM_I2S_MASKS,
118 AIU_MEM_I2S_MASKS_IRQ_BLOCK, val);
119
120 return 0;
121}
122
123const struct snd_soc_dai_ops aiu_fifo_i2s_dai_ops = {
124 .trigger = aiu_fifo_i2s_trigger,
125 .prepare = aiu_fifo_i2s_prepare,
126 .hw_params = aiu_fifo_i2s_hw_params,
127 .startup = aiu_fifo_startup,
128 .shutdown = aiu_fifo_shutdown,
129};
130
131int aiu_fifo_i2s_dai_probe(struct snd_soc_dai *dai)
132{
133 struct snd_soc_component *component = dai->component;
134 struct aiu *aiu = snd_soc_component_get_drvdata(component);
135 struct aiu_fifo *fifo;
136 int ret;
137
138 ret = aiu_fifo_dai_probe(dai);
139 if (ret)
140 return ret;
141
142 fifo = dai->playback_dma_data;
143
144 fifo->pcm = &fifo_i2s_pcm;
145 fifo->mem_offset = AIU_MEM_I2S_START;
146 fifo->fifo_block = AIU_FIFO_I2S_BLOCK;
147 fifo->pclk = aiu->i2s.clks[PCLK].clk;
148 fifo->irq = aiu->i2s.irq;
149
150 return 0;
151}
152
