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18#include <linux/pm_runtime.h>
19#include <sound/hdaudio_ext.h>
20#include <sound/hda_register.h>
21#include <sound/sof.h>
22#include "../ops.h"
23#include "../sof-audio.h"
24#include "hda.h"
25
26#define HDA_LTRP_GB_VALUE_US 95
27
28
29
30
31static int hda_setup_bdle(struct snd_sof_dev *sdev,
32 struct snd_dma_buffer *dmab,
33 struct hdac_stream *stream,
34 struct sof_intel_dsp_bdl **bdlp,
35 int offset, int size, int ioc)
36{
37 struct hdac_bus *bus = sof_to_bus(sdev);
38 struct sof_intel_dsp_bdl *bdl = *bdlp;
39
40 while (size > 0) {
41 dma_addr_t addr;
42 int chunk;
43
44 if (stream->frags >= HDA_DSP_MAX_BDL_ENTRIES) {
45 dev_err(sdev->dev, "error: stream frags exceeded\n");
46 return -EINVAL;
47 }
48
49 addr = snd_sgbuf_get_addr(dmab, offset);
50
51 bdl->addr_l = cpu_to_le32(lower_32_bits(addr));
52 bdl->addr_h = cpu_to_le32(upper_32_bits(addr));
53
54 chunk = snd_sgbuf_get_chunk_size(dmab, offset, size);
55
56 if (bus->align_bdle_4k) {
57 u32 remain = 0x1000 - (offset & 0xfff);
58
59 if (chunk > remain)
60 chunk = remain;
61 }
62 bdl->size = cpu_to_le32(chunk);
63
64 size -= chunk;
65 bdl->ioc = (size || !ioc) ? 0 : cpu_to_le32(0x01);
66 bdl++;
67 stream->frags++;
68 offset += chunk;
69
70 dev_vdbg(sdev->dev, "bdl, frags:%d, chunk size:0x%x;\n",
71 stream->frags, chunk);
72 }
73
74 *bdlp = bdl;
75 return offset;
76}
77
78
79
80
81
82int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
83 struct snd_dma_buffer *dmab,
84 struct hdac_stream *stream)
85{
86 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
87 struct sof_intel_dsp_bdl *bdl;
88 int i, offset, period_bytes, periods;
89 int remain, ioc;
90
91 period_bytes = stream->period_bytes;
92 dev_dbg(sdev->dev, "period_bytes:0x%x\n", period_bytes);
93 if (!period_bytes)
94 period_bytes = stream->bufsize;
95
96 periods = stream->bufsize / period_bytes;
97
98 dev_dbg(sdev->dev, "periods:%d\n", periods);
99
100 remain = stream->bufsize % period_bytes;
101 if (remain)
102 periods++;
103
104
105 bdl = (struct sof_intel_dsp_bdl *)stream->bdl.area;
106 offset = 0;
107 stream->frags = 0;
108
109
110
111
112
113 ioc = hda->no_ipc_position ?
114 !stream->no_period_wakeup : 0;
115
116 for (i = 0; i < periods; i++) {
117 if (i == (periods - 1) && remain)
118
119 offset = hda_setup_bdle(sdev, dmab,
120 stream, &bdl, offset,
121 remain, 0);
122 else
123 offset = hda_setup_bdle(sdev, dmab,
124 stream, &bdl, offset,
125 period_bytes, ioc);
126 }
127
128 return offset;
129}
130
131int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
132 struct hdac_ext_stream *stream,
133 int enable, u32 size)
134{
135 struct hdac_stream *hstream = &stream->hstream;
136 u32 mask;
137
138 if (!sdev->bar[HDA_DSP_SPIB_BAR]) {
139 dev_err(sdev->dev, "error: address of spib capability is NULL\n");
140 return -EINVAL;
141 }
142
143 mask = (1 << hstream->index);
144
145
146 snd_sof_dsp_update_bits(sdev, HDA_DSP_SPIB_BAR,
147 SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL, mask,
148 enable << hstream->index);
149
150
151 sof_io_write(sdev, stream->spib_addr, size);
152
153 return 0;
154}
155
156
157struct hdac_ext_stream *
158hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags)
159{
160 struct hdac_bus *bus = sof_to_bus(sdev);
161 struct sof_intel_hda_stream *hda_stream;
162 struct hdac_ext_stream *stream = NULL;
163 struct hdac_stream *s;
164
165 spin_lock_irq(&bus->reg_lock);
166
167
168 list_for_each_entry(s, &bus->stream_list, list) {
169 if (s->direction == direction && !s->opened) {
170 stream = stream_to_hdac_ext_stream(s);
171 hda_stream = container_of(stream,
172 struct sof_intel_hda_stream,
173 hda_stream);
174
175 if (hda_stream->host_reserved)
176 continue;
177
178 s->opened = true;
179 break;
180 }
181 }
182
183 spin_unlock_irq(&bus->reg_lock);
184
185
186 if (!stream) {
187 dev_err(sdev->dev, "error: no free %s streams\n",
188 direction == SNDRV_PCM_STREAM_PLAYBACK ?
189 "playback" : "capture");
190 return stream;
191 }
192
193 hda_stream->flags = flags;
194
195
196
197
198
199
200 if (!IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_ALWAYS_ENABLE_DMI_L1))
201 if (stream && !(flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE))
202 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
203 HDA_VS_INTEL_EM2,
204 HDA_VS_INTEL_EM2_L1SEN, 0);
205
206 return stream;
207}
208
209
210int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag)
211{
212 struct hdac_bus *bus = sof_to_bus(sdev);
213 struct sof_intel_hda_stream *hda_stream;
214 struct hdac_ext_stream *stream;
215 struct hdac_stream *s;
216 bool dmi_l1_enable = true;
217 bool found = false;
218
219 spin_lock_irq(&bus->reg_lock);
220
221
222
223
224
225 list_for_each_entry(s, &bus->stream_list, list) {
226 stream = stream_to_hdac_ext_stream(s);
227 hda_stream = container_of(stream, struct sof_intel_hda_stream, hda_stream);
228
229 if (!s->opened)
230 continue;
231
232 if (s->direction == direction && s->stream_tag == stream_tag) {
233 s->opened = false;
234 found = true;
235 } else if (!(hda_stream->flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) {
236 dmi_l1_enable = false;
237 }
238 }
239
240 spin_unlock_irq(&bus->reg_lock);
241
242
243 if (!IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_ALWAYS_ENABLE_DMI_L1) && dmi_l1_enable)
244 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
245 HDA_VS_INTEL_EM2_L1SEN, HDA_VS_INTEL_EM2_L1SEN);
246
247 if (!found) {
248 dev_dbg(sdev->dev, "stream_tag %d not opened!\n", stream_tag);
249 return -ENODEV;
250 }
251
252 return 0;
253}
254
255int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
256 struct hdac_ext_stream *stream, int cmd)
257{
258 struct hdac_stream *hstream = &stream->hstream;
259 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
260 u32 dma_start = SOF_HDA_SD_CTL_DMA_START;
261 int ret;
262 u32 run;
263
264
265 switch (cmd) {
266 case SNDRV_PCM_TRIGGER_RESUME:
267 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
268 case SNDRV_PCM_TRIGGER_START:
269 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
270 1 << hstream->index,
271 1 << hstream->index);
272
273 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
274 sd_offset,
275 SOF_HDA_SD_CTL_DMA_START |
276 SOF_HDA_CL_DMA_SD_INT_MASK,
277 SOF_HDA_SD_CTL_DMA_START |
278 SOF_HDA_CL_DMA_SD_INT_MASK);
279
280 ret = snd_sof_dsp_read_poll_timeout(sdev,
281 HDA_DSP_HDA_BAR,
282 sd_offset, run,
283 ((run & dma_start) == dma_start),
284 HDA_DSP_REG_POLL_INTERVAL_US,
285 HDA_DSP_STREAM_RUN_TIMEOUT);
286
287 if (ret < 0) {
288 dev_err(sdev->dev,
289 "error: %s: cmd %d: timeout on STREAM_SD_OFFSET read\n",
290 __func__, cmd);
291 return ret;
292 }
293
294 hstream->running = true;
295 break;
296 case SNDRV_PCM_TRIGGER_SUSPEND:
297 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
298 case SNDRV_PCM_TRIGGER_STOP:
299 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
300 sd_offset,
301 SOF_HDA_SD_CTL_DMA_START |
302 SOF_HDA_CL_DMA_SD_INT_MASK, 0x0);
303
304 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
305 sd_offset, run,
306 !(run & dma_start),
307 HDA_DSP_REG_POLL_INTERVAL_US,
308 HDA_DSP_STREAM_RUN_TIMEOUT);
309
310 if (ret < 0) {
311 dev_err(sdev->dev,
312 "error: %s: cmd %d: timeout on STREAM_SD_OFFSET read\n",
313 __func__, cmd);
314 return ret;
315 }
316
317 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, sd_offset +
318 SOF_HDA_ADSP_REG_CL_SD_STS,
319 SOF_HDA_CL_DMA_SD_INT_MASK);
320
321 hstream->running = false;
322 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
323 1 << hstream->index, 0x0);
324 break;
325 default:
326 dev_err(sdev->dev, "error: unknown command: %d\n", cmd);
327 return -EINVAL;
328 }
329
330 return 0;
331}
332
333
334int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *stream,
335 struct snd_dma_buffer *dmab,
336 struct snd_pcm_hw_params *params)
337{
338 struct hdac_bus *bus = sof_to_bus(sdev);
339 struct hdac_stream *hstream = &stream->hstream;
340 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
341 int ret;
342 u32 mask = 0x1 << hstream->index;
343
344 if (!stream) {
345 dev_err(sdev->dev, "error: no stream available\n");
346 return -ENODEV;
347 }
348
349 if (hstream->posbuf)
350 *hstream->posbuf = 0;
351
352
353 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
354 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
355 0x0);
356 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
357 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
358 0x0);
359
360 hstream->frags = 0;
361
362 ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
363 if (ret < 0) {
364 dev_err(sdev->dev, "error: set up of BDL failed\n");
365 return ret;
366 }
367
368
369 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
370 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
371 (u32)hstream->bdl.addr);
372 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
373 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
374 upper_32_bits(hstream->bdl.addr));
375
376
377 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
378 sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL,
379 hstream->bufsize);
380
381
382 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
383 sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI,
384 0xffff, (hstream->frags - 1));
385
386
387 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
388 mask, mask);
389
390
391 snd_hdac_chip_updateb(bus, VS_LTRP, HDA_VS_INTEL_LTRP_GB_MASK, HDA_LTRP_GB_VALUE_US);
392
393
394 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
395 SOF_HDA_SD_CTL_DMA_START, SOF_HDA_SD_CTL_DMA_START);
396
397 return 0;
398}
399
400
401
402
403
404int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
405 struct hdac_ext_stream *stream,
406 struct snd_dma_buffer *dmab,
407 struct snd_pcm_hw_params *params)
408{
409 struct hdac_bus *bus = sof_to_bus(sdev);
410 struct hdac_stream *hstream = &stream->hstream;
411 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
412 int ret, timeout = HDA_DSP_STREAM_RESET_TIMEOUT;
413 u32 dma_start = SOF_HDA_SD_CTL_DMA_START;
414 u32 val, mask;
415 u32 run;
416
417 if (!stream) {
418 dev_err(sdev->dev, "error: no stream available\n");
419 return -ENODEV;
420 }
421
422
423 mask = 0x1 << hstream->index;
424 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
425 mask, mask);
426
427 if (!dmab) {
428 dev_err(sdev->dev, "error: no dma buffer allocated!\n");
429 return -ENODEV;
430 }
431
432
433 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
434 SOF_HDA_CL_DMA_SD_INT_MASK |
435 SOF_HDA_SD_CTL_DMA_START, 0);
436
437 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
438 sd_offset, run,
439 !(run & dma_start),
440 HDA_DSP_REG_POLL_INTERVAL_US,
441 HDA_DSP_STREAM_RUN_TIMEOUT);
442
443 if (ret < 0) {
444 dev_err(sdev->dev,
445 "error: %s: timeout on STREAM_SD_OFFSET read1\n",
446 __func__);
447 return ret;
448 }
449
450 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
451 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
452 SOF_HDA_CL_DMA_SD_INT_MASK,
453 SOF_HDA_CL_DMA_SD_INT_MASK);
454
455
456 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 0x1,
457 0x1);
458 udelay(3);
459 do {
460 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
461 sd_offset);
462 if (val & 0x1)
463 break;
464 } while (--timeout);
465 if (timeout == 0) {
466 dev_err(sdev->dev, "error: stream reset failed\n");
467 return -ETIMEDOUT;
468 }
469
470 timeout = HDA_DSP_STREAM_RESET_TIMEOUT;
471 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, 0x1,
472 0x0);
473
474
475 udelay(3);
476 do {
477 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
478 sd_offset);
479 if ((val & 0x1) == 0)
480 break;
481 } while (--timeout);
482 if (timeout == 0) {
483 dev_err(sdev->dev, "error: timeout waiting for stream reset\n");
484 return -ETIMEDOUT;
485 }
486
487 if (hstream->posbuf)
488 *hstream->posbuf = 0;
489
490
491 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
492 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
493 0x0);
494 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
495 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
496 0x0);
497
498
499 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
500 SOF_HDA_CL_DMA_SD_INT_MASK |
501 SOF_HDA_SD_CTL_DMA_START, 0);
502
503 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
504 sd_offset, run,
505 !(run & dma_start),
506 HDA_DSP_REG_POLL_INTERVAL_US,
507 HDA_DSP_STREAM_RUN_TIMEOUT);
508
509 if (ret < 0) {
510 dev_err(sdev->dev,
511 "error: %s: timeout on STREAM_SD_OFFSET read2\n",
512 __func__);
513 return ret;
514 }
515
516 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
517 sd_offset + SOF_HDA_ADSP_REG_CL_SD_STS,
518 SOF_HDA_CL_DMA_SD_INT_MASK,
519 SOF_HDA_CL_DMA_SD_INT_MASK);
520
521 hstream->frags = 0;
522
523 ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
524 if (ret < 0) {
525 dev_err(sdev->dev, "error: set up of BDL failed\n");
526 return ret;
527 }
528
529
530 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
531 SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK,
532 hstream->stream_tag <<
533 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT);
534
535
536 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
537 sd_offset + SOF_HDA_ADSP_REG_CL_SD_CBL,
538 hstream->bufsize);
539
540
541
542
543
544
545
546
547
548
549
550
551
552 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
553 mask, 0);
554
555
556 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
557 sd_offset +
558 SOF_HDA_ADSP_REG_CL_SD_FORMAT,
559 0xffff, hstream->format_val);
560
561
562 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
563 mask, mask);
564
565
566 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
567 sd_offset + SOF_HDA_ADSP_REG_CL_SD_LVI,
568 0xffff, (hstream->frags - 1));
569
570
571 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
572 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPL,
573 (u32)hstream->bdl.addr);
574 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
575 sd_offset + SOF_HDA_ADSP_REG_CL_SD_BDLPU,
576 upper_32_bits(hstream->bdl.addr));
577
578
579 if (!(snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE)
580 & SOF_HDA_ADSP_DPLBASE_ENABLE)) {
581 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
582 upper_32_bits(bus->posbuf.addr));
583 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
584 (u32)bus->posbuf.addr |
585 SOF_HDA_ADSP_DPLBASE_ENABLE);
586 }
587
588
589 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
590 SOF_HDA_CL_DMA_SD_INT_MASK,
591 SOF_HDA_CL_DMA_SD_INT_MASK);
592
593
594 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) {
595 hstream->fifo_size =
596 snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
597 sd_offset +
598 SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE);
599 hstream->fifo_size &= 0xffff;
600 hstream->fifo_size += 1;
601 } else {
602 hstream->fifo_size = 0;
603 }
604
605 return ret;
606}
607
608int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
609 struct snd_pcm_substream *substream)
610{
611 struct hdac_stream *stream = substream->runtime->private_data;
612 struct hdac_ext_stream *link_dev = container_of(stream,
613 struct hdac_ext_stream,
614 hstream);
615 struct hdac_bus *bus = sof_to_bus(sdev);
616 u32 mask = 0x1 << stream->index;
617
618 spin_lock_irq(&bus->reg_lock);
619
620 if (!link_dev->link_locked)
621 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
622 SOF_HDA_REG_PP_PPCTL, mask, 0);
623 spin_unlock_irq(&bus->reg_lock);
624
625 stream->substream = NULL;
626
627 return 0;
628}
629
630bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev)
631{
632 struct hdac_bus *bus = sof_to_bus(sdev);
633 bool ret = false;
634 u32 status;
635
636
637 spin_lock_irq(&bus->reg_lock);
638
639 status = snd_hdac_chip_readl(bus, INTSTS);
640 dev_vdbg(bus->dev, "stream irq, INTSTS status: 0x%x\n", status);
641
642
643 if (status != 0xffffffff)
644 ret = true;
645
646 spin_unlock_irq(&bus->reg_lock);
647
648 return ret;
649}
650
651static void
652hda_dsp_set_bytes_transferred(struct hdac_stream *hstream, u64 buffer_size)
653{
654 u64 prev_pos, pos, num_bytes;
655
656 div64_u64_rem(hstream->curr_pos, buffer_size, &prev_pos);
657 pos = snd_hdac_stream_get_pos_posbuf(hstream);
658
659 if (pos < prev_pos)
660 num_bytes = (buffer_size - prev_pos) + pos;
661 else
662 num_bytes = pos - prev_pos;
663
664 hstream->curr_pos += num_bytes;
665}
666
667static bool hda_dsp_stream_check(struct hdac_bus *bus, u32 status)
668{
669 struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus);
670 struct hdac_stream *s;
671 bool active = false;
672 u32 sd_status;
673
674 list_for_each_entry(s, &bus->stream_list, list) {
675 if (status & BIT(s->index) && s->opened) {
676 sd_status = snd_hdac_stream_readb(s, SD_STS);
677
678 dev_vdbg(bus->dev, "stream %d status 0x%x\n",
679 s->index, sd_status);
680
681 snd_hdac_stream_writeb(s, SD_STS, sd_status);
682
683 active = true;
684 if ((!s->substream && !s->cstream) ||
685 !s->running ||
686 (sd_status & SOF_HDA_CL_DMA_SD_INT_COMPLETE) == 0)
687 continue;
688
689
690 if (s->substream && sof_hda->no_ipc_position) {
691 snd_sof_pcm_period_elapsed(s->substream);
692 } else if (s->cstream) {
693 hda_dsp_set_bytes_transferred(s,
694 s->cstream->runtime->buffer_size);
695 snd_compr_fragment_elapsed(s->cstream);
696 }
697 }
698 }
699
700 return active;
701}
702
703irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context)
704{
705 struct snd_sof_dev *sdev = context;
706 struct hdac_bus *bus = sof_to_bus(sdev);
707#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
708 u32 rirb_status;
709#endif
710 bool active;
711 u32 status;
712 int i;
713
714
715
716
717
718 for (i = 0, active = true; i < 10 && active; i++) {
719 spin_lock_irq(&bus->reg_lock);
720
721 status = snd_hdac_chip_readl(bus, INTSTS);
722
723
724 active = hda_dsp_stream_check(bus, status);
725
726
727#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
728 if (status & AZX_INT_CTRL_EN) {
729 rirb_status = snd_hdac_chip_readb(bus, RIRBSTS);
730 if (rirb_status & RIRB_INT_MASK) {
731
732
733
734
735
736 snd_hdac_chip_writeb(bus, RIRBSTS,
737 RIRB_INT_MASK);
738 active = true;
739 if (rirb_status & RIRB_INT_RESPONSE)
740 snd_hdac_bus_update_rirb(bus);
741 }
742 }
743#endif
744 spin_unlock_irq(&bus->reg_lock);
745 }
746
747 return IRQ_HANDLED;
748}
749
750int hda_dsp_stream_init(struct snd_sof_dev *sdev)
751{
752 struct hdac_bus *bus = sof_to_bus(sdev);
753 struct hdac_ext_stream *stream;
754 struct hdac_stream *hstream;
755 struct pci_dev *pci = to_pci_dev(sdev->dev);
756 struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus);
757 int sd_offset;
758 int i, num_playback, num_capture, num_total, ret;
759 u32 gcap;
760
761 gcap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCAP);
762 dev_dbg(sdev->dev, "hda global caps = 0x%x\n", gcap);
763
764
765 num_capture = (gcap >> 8) & 0x0f;
766 num_playback = (gcap >> 12) & 0x0f;
767 num_total = num_playback + num_capture;
768
769 dev_dbg(sdev->dev, "detected %d playback and %d capture streams\n",
770 num_playback, num_capture);
771
772 if (num_playback >= SOF_HDA_PLAYBACK_STREAMS) {
773 dev_err(sdev->dev, "error: too many playback streams %d\n",
774 num_playback);
775 return -EINVAL;
776 }
777
778 if (num_capture >= SOF_HDA_CAPTURE_STREAMS) {
779 dev_err(sdev->dev, "error: too many capture streams %d\n",
780 num_playback);
781 return -EINVAL;
782 }
783
784
785
786
787
788 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
789 SOF_HDA_DPIB_ENTRY_SIZE * num_total,
790 &bus->posbuf);
791 if (ret < 0) {
792 dev_err(sdev->dev, "error: posbuffer dma alloc failed\n");
793 return -ENOMEM;
794 }
795
796#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
797
798 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
799 PAGE_SIZE, &bus->rb);
800 if (ret < 0) {
801 dev_err(sdev->dev, "error: RB alloc failed\n");
802 return -ENOMEM;
803 }
804#endif
805
806
807 for (i = 0; i < num_capture; i++) {
808 struct sof_intel_hda_stream *hda_stream;
809
810 hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream),
811 GFP_KERNEL);
812 if (!hda_stream)
813 return -ENOMEM;
814
815 hda_stream->sdev = sdev;
816
817 stream = &hda_stream->hda_stream;
818
819 stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +
820 SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i;
821
822 stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
823 SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total +
824 SOF_HDA_PPLC_INTERVAL * i;
825
826
827 if (sdev->bar[HDA_DSP_SPIB_BAR]) {
828 stream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
829 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
830 SOF_HDA_SPIB_SPIB;
831
832 stream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
833 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
834 SOF_HDA_SPIB_MAXFIFO;
835 }
836
837 hstream = &stream->hstream;
838 hstream->bus = bus;
839 hstream->sd_int_sta_mask = 1 << i;
840 hstream->index = i;
841 sd_offset = SOF_STREAM_SD_OFFSET(hstream);
842 hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset;
843 hstream->stream_tag = i + 1;
844 hstream->opened = false;
845 hstream->running = false;
846 hstream->direction = SNDRV_PCM_STREAM_CAPTURE;
847
848
849 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
850 HDA_DSP_BDL_SIZE, &hstream->bdl);
851 if (ret < 0) {
852 dev_err(sdev->dev, "error: stream bdl dma alloc failed\n");
853 return -ENOMEM;
854 }
855 hstream->posbuf = (__le32 *)(bus->posbuf.area +
856 (hstream->index) * 8);
857
858 list_add_tail(&hstream->list, &bus->stream_list);
859 }
860
861
862 for (i = num_capture; i < num_total; i++) {
863 struct sof_intel_hda_stream *hda_stream;
864
865 hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream),
866 GFP_KERNEL);
867 if (!hda_stream)
868 return -ENOMEM;
869
870 hda_stream->sdev = sdev;
871
872 stream = &hda_stream->hda_stream;
873
874
875 stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +
876 SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i;
877
878 stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
879 SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total +
880 SOF_HDA_PPLC_INTERVAL * i;
881
882
883 if (sdev->bar[HDA_DSP_SPIB_BAR]) {
884 stream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
885 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
886 SOF_HDA_SPIB_SPIB;
887
888 stream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
889 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
890 SOF_HDA_SPIB_MAXFIFO;
891 }
892
893 hstream = &stream->hstream;
894 hstream->bus = bus;
895 hstream->sd_int_sta_mask = 1 << i;
896 hstream->index = i;
897 sd_offset = SOF_STREAM_SD_OFFSET(hstream);
898 hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset;
899 hstream->stream_tag = i - num_capture + 1;
900 hstream->opened = false;
901 hstream->running = false;
902 hstream->direction = SNDRV_PCM_STREAM_PLAYBACK;
903
904
905 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
906 HDA_DSP_BDL_SIZE, &hstream->bdl);
907 if (ret < 0) {
908 dev_err(sdev->dev, "error: stream bdl dma alloc failed\n");
909 return -ENOMEM;
910 }
911
912 hstream->posbuf = (__le32 *)(bus->posbuf.area +
913 (hstream->index) * 8);
914
915 list_add_tail(&hstream->list, &bus->stream_list);
916 }
917
918
919 sof_hda->stream_max = num_total;
920
921 return 0;
922}
923
924void hda_dsp_stream_free(struct snd_sof_dev *sdev)
925{
926 struct hdac_bus *bus = sof_to_bus(sdev);
927 struct hdac_stream *s, *_s;
928 struct hdac_ext_stream *stream;
929 struct sof_intel_hda_stream *hda_stream;
930
931
932 if (bus->posbuf.area)
933 snd_dma_free_pages(&bus->posbuf);
934
935#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
936
937 if (bus->rb.area)
938 snd_dma_free_pages(&bus->rb);
939#endif
940
941 list_for_each_entry_safe(s, _s, &bus->stream_list, list) {
942
943
944
945 if (s->bdl.area)
946 snd_dma_free_pages(&s->bdl);
947 list_del(&s->list);
948 stream = stream_to_hdac_ext_stream(s);
949 hda_stream = container_of(stream, struct sof_intel_hda_stream,
950 hda_stream);
951 devm_kfree(sdev->dev, hda_stream);
952 }
953}
954
