1/* SPDX-License-Identifier: GPL-2.0-only */ 2#ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H 3#define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H 4 5/* 6 * OMAP2/3 PRCM base and module definitions 7 * 8 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc. 9 * Copyright (C) 2007-2009 Nokia Corporation 10 * 11 * Written by Paul Walmsley 12 */ 13 14/* Module offsets from both CM_BASE & PRM_BASE */ 15 16/* 17 * Offsets that are the same on 24xx and 34xx 18 * 19 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is 20 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2. 21 */ 22#define OCP_MOD 0x000 23#define MPU_MOD 0x100 24#define CORE_MOD 0x200 25#define GFX_MOD 0x300 26#define WKUP_MOD 0x400 27#define PLL_MOD 0x500 28 29 30/* Chip-specific module offsets */ 31#define OMAP24XX_GR_MOD OCP_MOD 32#define OMAP24XX_DSP_MOD 0x800 33 34#define OMAP2430_MDM_MOD 0xc00 35 36/* IVA2 module is < base on 3430 */ 37#define OMAP3430_IVA2_MOD -0x800 38#define OMAP3430ES2_SGX_MOD GFX_MOD 39#define OMAP3430_CCR_MOD PLL_MOD 40#define OMAP3430_DSS_MOD 0x600 41#define OMAP3430_CAM_MOD 0x700 42#define OMAP3430_PER_MOD 0x800 43#define OMAP3430_EMU_MOD 0x900 44#define OMAP3430_GR_MOD 0xa00 45#define OMAP3430_NEON_MOD 0xb00 46#define OMAP3430ES2_USBHOST_MOD 0xc00 47 48/* 49 * TI81XX PRM module offsets 50 */ 51#define TI814X_PRM_DSP_MOD 0x0a00 52#define TI814X_PRM_HDVICP_MOD 0x0c00 53#define TI814X_PRM_ISP_MOD 0x0d00 54#define TI814X_PRM_HDVPSS_MOD 0x0e00 55#define TI814X_PRM_GFX_MOD 0x0f00 56 57#define TI81XX_PRM_DEVICE_MOD 0x0000 58#define TI816X_PRM_ACTIVE_MOD 0x0a00 59#define TI81XX_PRM_DEFAULT_MOD 0x0b00 60#define TI816X_PRM_IVAHD0_MOD 0x0c00 61#define TI816X_PRM_IVAHD1_MOD 0x0d00 62#define TI816X_PRM_IVAHD2_MOD 0x0e00 63#define TI816X_PRM_SGX_MOD 0x0f00 64#define TI81XX_PRM_ALWON_MOD 0x1800 65 66/* 24XX register bits shared between CM & PRM registers */ 67 68/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 69#define OMAP2420_EN_MMC_SHIFT 26 70#define OMAP2420_EN_MMC_MASK (1 << 26) 71#define OMAP24XX_EN_UART2_SHIFT 22 72#define OMAP24XX_EN_UART2_MASK (1 << 22) 73#define OMAP24XX_EN_UART1_SHIFT 21 74#define OMAP24XX_EN_UART1_MASK (1 << 21) 75#define OMAP24XX_EN_MCSPI2_SHIFT 18 76#define OMAP24XX_EN_MCSPI2_MASK (1 << 18) 77#define OMAP24XX_EN_MCSPI1_SHIFT 17 78#define OMAP24XX_EN_MCSPI1_MASK (1 << 17) 79#define OMAP24XX_EN_MCBSP2_SHIFT 16 80#define OMAP24XX_EN_MCBSP2_MASK (1 << 16) 81#define OMAP24XX_EN_MCBSP1_SHIFT 15 82#define OMAP24XX_EN_MCBSP1_MASK (1 << 15) 83#define OMAP24XX_EN_GPT12_SHIFT 14 84#define OMAP24XX_EN_GPT12_MASK (1 << 14) 85#define OMAP24XX_EN_GPT11_SHIFT 13 86#define OMAP24XX_EN_GPT11_MASK (1 << 13) 87#define OMAP24XX_EN_GPT10_SHIFT 12 88#define OMAP24XX_EN_GPT10_MASK (1 << 12) 89#define OMAP24XX_EN_GPT9_SHIFT 11 90#define OMAP24XX_EN_GPT9_MASK (1 << 11) 91#define OMAP24XX_EN_GPT8_SHIFT 10 92#define OMAP24XX_EN_GPT8_MASK (1 << 10) 93#define OMAP24XX_EN_GPT7_SHIFT 9 94#define OMAP24XX_EN_GPT7_MASK (1 << 9) 95#define OMAP24XX_EN_GPT6_SHIFT 8 96#define OMAP24XX_EN_GPT6_MASK (1 << 8) 97#define OMAP24XX_EN_GPT5_SHIFT 7 98#define OMAP24XX_EN_GPT5_MASK (1 << 7) 99#define OMAP24XX_EN_GPT4_SHIFT 6 100#define OMAP24XX_EN_GPT4_MASK (1 << 6) 101#define OMAP24XX_EN_GPT3_SHIFT 5 102#define OMAP24XX_EN_GPT3_MASK (1 << 5) 103#define OMAP24XX_EN_GPT2_SHIFT 4 104#define OMAP24XX_EN_GPT2_MASK (1 << 4) 105#define OMAP2420_EN_VLYNQ_SHIFT 3 106#define OMAP2420_EN_VLYNQ_MASK (1 << 3) 107 108/* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 109#define OMAP2430_EN_GPIO5_SHIFT 10 110#define OMAP2430_EN_GPIO5_MASK (1 << 10) 111#define OMAP2430_EN_MCSPI3_SHIFT 9 112#define OMAP2430_EN_MCSPI3_MASK (1 << 9) 113#define OMAP2430_EN_MMCHS2_SHIFT 8 114#define OMAP2430_EN_MMCHS2_MASK (1 << 8) 115#define OMAP2430_EN_MMCHS1_SHIFT 7 116#define OMAP2430_EN_MMCHS1_MASK (1 << 7) 117#define OMAP24XX_EN_UART3_SHIFT 2 118#define OMAP24XX_EN_UART3_MASK (1 << 2) 119#define OMAP24XX_EN_USB_SHIFT 0 120#define OMAP24XX_EN_USB_MASK (1 << 0) 121 122/* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ 123#define OMAP2430_EN_MDM_INTC_SHIFT 11 124#define OMAP2430_EN_MDM_INTC_MASK (1 << 11) 125#define OMAP2430_EN_USBHS_SHIFT 6 126#define OMAP2430_EN_USBHS_MASK (1 << 6) 127#define OMAP24XX_EN_GPMC_SHIFT 1 128#define OMAP24XX_EN_GPMC_MASK (1 << 1) 129 130/* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ 131#define OMAP2420_ST_MMC_SHIFT 26 132#define OMAP2420_ST_MMC_MASK (1 << 26) 133#define OMAP24XX_ST_UART2_SHIFT 22 134#define OMAP24XX_ST_UART2_MASK (1 << 22) 135#define OMAP24XX_ST_UART1_SHIFT 21 136#define OMAP24XX_ST_UART1_MASK (1 << 21) 137#define OMAP24XX_ST_MCSPI2_SHIFT 18 138#define OMAP24XX_ST_MCSPI2_MASK (1 << 18) 139#define OMAP24XX_ST_MCSPI1_SHIFT 17 140#define OMAP24XX_ST_MCSPI1_MASK (1 << 17) 141#define OMAP24XX_ST_MCBSP2_SHIFT 16 142#define OMAP24XX_ST_MCBSP2_MASK (1 << 16) 143#define OMAP24XX_ST_MCBSP1_SHIFT 15 144#define OMAP24XX_ST_MCBSP1_MASK (1 << 15) 145#define OMAP24XX_ST_GPT12_SHIFT 14 146#define OMAP24XX_ST_GPT12_MASK (1 << 14) 147#define OMAP24XX_ST_GPT11_SHIFT 13 148#define OMAP24XX_ST_GPT11_MASK (1 << 13) 149#define OMAP24XX_ST_GPT10_SHIFT 12 150#define OMAP24XX_ST_GPT10_MASK (1 << 12) 151#define OMAP24XX_ST_GPT9_SHIFT 11 152#define OMAP24XX_ST_GPT9_MASK (1 << 11) 153#define OMAP24XX_ST_GPT8_SHIFT 10 154#define OMAP24XX_ST_GPT8_MASK (1 << 10) 155#define OMAP24XX_ST_GPT7_SHIFT 9 156#define OMAP24XX_ST_GPT7_MASK (1 << 9) 157#define OMAP24XX_ST_GPT6_SHIFT 8 158#define OMAP24XX_ST_GPT6_MASK (1 << 8) 159#define OMAP24XX_ST_GPT5_SHIFT 7 160#define OMAP24XX_ST_GPT5_MASK (1 << 7) 161#define OMAP24XX_ST_GPT4_SHIFT 6 162#define OMAP24XX_ST_GPT4_MASK (1 << 6) 163#define OMAP24XX_ST_GPT3_SHIFT 5 164#define OMAP24XX_ST_GPT3_MASK (1 << 5) 165#define OMAP24XX_ST_GPT2_SHIFT 4 166#define OMAP24XX_ST_GPT2_MASK (1 << 4) 167#define OMAP2420_ST_VLYNQ_SHIFT 3 168#define OMAP2420_ST_VLYNQ_MASK (1 << 3) 169 170/* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ 171#define OMAP2430_ST_MDM_INTC_SHIFT 11 172#define OMAP2430_ST_MDM_INTC_MASK (1 << 11) 173#define OMAP2430_ST_GPIO5_SHIFT 10 174#define OMAP2430_ST_GPIO5_MASK (1 << 10) 175#define OMAP2430_ST_MCSPI3_SHIFT 9 176#define OMAP2430_ST_MCSPI3_MASK (1 << 9) 177#define OMAP2430_ST_MMCHS2_SHIFT 8 178#define OMAP2430_ST_MMCHS2_MASK (1 << 8) 179#define OMAP2430_ST_MMCHS1_SHIFT 7 180#define OMAP2430_ST_MMCHS1_MASK (1 << 7) 181#define OMAP2430_ST_USBHS_SHIFT 6 182#define OMAP2430_ST_USBHS_MASK (1 << 6) 183#define OMAP24XX_ST_UART3_SHIFT 2 184#define OMAP24XX_ST_UART3_MASK (1 << 2) 185#define OMAP24XX_ST_USB_SHIFT 0 186#define OMAP24XX_ST_USB_MASK (1 << 0) 187 188/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 189#define OMAP24XX_EN_GPIOS_SHIFT 2 190#define OMAP24XX_EN_GPIOS_MASK (1 << 2) 191#define OMAP24XX_EN_GPT1_SHIFT 0 192#define OMAP24XX_EN_GPT1_MASK (1 << 0) 193 194/* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ 195#define OMAP24XX_ST_GPIOS_SHIFT 2 196#define OMAP24XX_ST_GPIOS_MASK (1 << 2) 197#define OMAP24XX_ST_32KSYNC_SHIFT 1 198#define OMAP24XX_ST_32KSYNC_MASK (1 << 1) 199#define OMAP24XX_ST_GPT1_SHIFT 0 200#define OMAP24XX_ST_GPT1_MASK (1 << 0) 201 202/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ 203#define OMAP2430_ST_MDM_SHIFT 0 204#define OMAP2430_ST_MDM_MASK (1 << 0) 205 206 207/* 3430 register bits shared between CM & PRM registers */ 208 209/* CM_REVISION, PRM_REVISION shared bits */ 210#define OMAP3430_REV_SHIFT 0 211#define OMAP3430_REV_MASK (0xff << 0) 212 213/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ 214#define OMAP3430_AUTOIDLE_MASK (1 << 0) 215 216/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 217#define OMAP3430_EN_MMC3_MASK (1 << 30) 218#define OMAP3430_EN_MMC3_SHIFT 30 219#define OMAP3430_EN_MMC2_MASK (1 << 25) 220#define OMAP3430_EN_MMC2_SHIFT 25 221#define OMAP3430_EN_MMC1_MASK (1 << 24) 222#define OMAP3430_EN_MMC1_SHIFT 24 223#define AM35XX_EN_UART4_MASK (1 << 23) 224#define AM35XX_EN_UART4_SHIFT 23 225#define OMAP3430_EN_MCSPI4_MASK (1 << 21) 226#define OMAP3430_EN_MCSPI4_SHIFT 21 227#define OMAP3430_EN_MCSPI3_MASK (1 << 20) 228#define OMAP3430_EN_MCSPI3_SHIFT 20 229#define OMAP3430_EN_MCSPI2_MASK (1 << 19) 230#define OMAP3430_EN_MCSPI2_SHIFT 19 231#define OMAP3430_EN_MCSPI1_MASK (1 << 18) 232#define OMAP3430_EN_MCSPI1_SHIFT 18 233#define OMAP3430_EN_I2C3_MASK (1 << 17) 234#define OMAP3430_EN_I2C3_SHIFT 17 235#define OMAP3430_EN_I2C2_MASK (1 << 16) 236#define OMAP3430_EN_I2C2_SHIFT 16 237#define OMAP3430_EN_I2C1_MASK (1 << 15) 238#define OMAP3430_EN_I2C1_SHIFT 15 239#define OMAP3430_EN_UART2_MASK (1 << 14) 240#define OMAP3430_EN_UART2_SHIFT 14 241#define OMAP3430_EN_UART1_MASK (1 << 13) 242#define OMAP3430_EN_UART1_SHIFT 13 243#define OMAP3430_EN_GPT11_MASK (1 << 12) 244#define OMAP3430_EN_GPT11_SHIFT 12 245#define OMAP3430_EN_GPT10_MASK (1 << 11) 246#define OMAP3430_EN_GPT10_SHIFT 11 247#define OMAP3430_EN_MCBSP5_MASK (1 << 10) 248#define OMAP3430_EN_MCBSP5_SHIFT 10 249#define OMAP3430_EN_MCBSP1_MASK (1 << 9) 250#define OMAP3430_EN_MCBSP1_SHIFT 9 251#define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5) 252#define OMAP3430_EN_FSHOSTUSB_SHIFT 5 253#define OMAP3430_EN_D2D_MASK (1 << 3) 254#define OMAP3430_EN_D2D_SHIFT 3 255 256/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 257#define OMAP3430_EN_HSOTGUSB_MASK (1 << 4) 258#define OMAP3430_EN_HSOTGUSB_SHIFT 4 259 260/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ 261#define OMAP3430_ST_MMC3_SHIFT 30 262#define OMAP3430_ST_MMC3_MASK (1 << 30) 263#define OMAP3430_ST_MMC2_SHIFT 25 264#define OMAP3430_ST_MMC2_MASK (1 << 25) 265#define OMAP3430_ST_MMC1_SHIFT 24 266#define OMAP3430_ST_MMC1_MASK (1 << 24) 267#define OMAP3430_ST_MCSPI4_SHIFT 21 268#define OMAP3430_ST_MCSPI4_MASK (1 << 21) 269#define OMAP3430_ST_MCSPI3_SHIFT 20 270#define OMAP3430_ST_MCSPI3_MASK (1 << 20) 271#define OMAP3430_ST_MCSPI2_SHIFT 19 272#define OMAP3430_ST_MCSPI2_MASK (1 << 19) 273#define OMAP3430_ST_MCSPI1_SHIFT 18 274#define OMAP3430_ST_MCSPI1_MASK (1 << 18) 275#define OMAP3430_ST_I2C3_SHIFT 17 276#define OMAP3430_ST_I2C3_MASK (1 << 17) 277#define OMAP3430_ST_I2C2_SHIFT 16 278#define OMAP3430_ST_I2C2_MASK (1 << 16) 279#define OMAP3430_ST_I2C1_SHIFT 15 280#define OMAP3430_ST_I2C1_MASK (1 << 15) 281#define OMAP3430_ST_UART2_SHIFT 14 282#define OMAP3430_ST_UART2_MASK (1 << 14) 283#define OMAP3430_ST_UART1_SHIFT 13 284#define OMAP3430_ST_UART1_MASK (1 << 13) 285#define OMAP3430_ST_GPT11_SHIFT 12 286#define OMAP3430_ST_GPT11_MASK (1 << 12) 287#define OMAP3430_ST_GPT10_SHIFT 11 288#define OMAP3430_ST_GPT10_MASK (1 << 11) 289#define OMAP3430_ST_MCBSP5_SHIFT 10 290#define OMAP3430_ST_MCBSP5_MASK (1 << 10) 291#define OMAP3430_ST_MCBSP1_SHIFT 9 292#define OMAP3430_ST_MCBSP1_MASK (1 << 9) 293#define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5 294#define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5) 295#define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4 296#define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4) 297#define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 298#define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5) 299#define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4 300#define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4) 301#define OMAP3430_ST_D2D_SHIFT 3 302#define OMAP3430_ST_D2D_MASK (1 << 3) 303 304/* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 305#define OMAP3430_EN_GPIO1_MASK (1 << 3) 306#define OMAP3430_EN_GPIO1_SHIFT 3 307#define OMAP3430_EN_GPT12_MASK (1 << 1) 308#define OMAP3430_EN_GPT12_SHIFT 1 309#define OMAP3430_EN_GPT1_MASK (1 << 0) 310#define OMAP3430_EN_GPT1_SHIFT 0 311 312/* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ 313#define OMAP3430_EN_SR2_MASK (1 << 7) 314#define OMAP3430_EN_SR2_SHIFT 7 315#define OMAP3430_EN_SR1_MASK (1 << 6) 316#define OMAP3430_EN_SR1_SHIFT 6 317 318/* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ 319#define OMAP3430_EN_GPT12_MASK (1 << 1) 320#define OMAP3430_EN_GPT12_SHIFT 1 321 322/* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ 323#define OMAP3430_ST_SR2_SHIFT 7 324#define OMAP3430_ST_SR2_MASK (1 << 7) 325#define OMAP3430_ST_SR1_SHIFT 6 326#define OMAP3430_ST_SR1_MASK (1 << 6) 327#define OMAP3430_ST_GPIO1_SHIFT 3 328#define OMAP3430_ST_GPIO1_MASK (1 << 3) 329#define OMAP3430_ST_32KSYNC_SHIFT 2 330#define OMAP3430_ST_32KSYNC_MASK (1 << 2) 331#define OMAP3430_ST_GPT12_SHIFT 1 332#define OMAP3430_ST_GPT12_MASK (1 << 1) 333#define OMAP3430_ST_GPT1_SHIFT 0 334#define OMAP3430_ST_GPT1_MASK (1 << 0) 335 336/* 337 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, 338 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, 339 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits 340 */ 341#define OMAP3430_EN_MPU_MASK (1 << 1) 342#define OMAP3430_EN_MPU_SHIFT 1 343 344/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ 345 346#define OMAP3630_EN_UART4_MASK (1 << 18) 347#define OMAP3630_EN_UART4_SHIFT 18 348#define OMAP3430_EN_GPIO6_MASK (1 << 17) 349#define OMAP3430_EN_GPIO6_SHIFT 17 350#define OMAP3430_EN_GPIO5_MASK (1 << 16) 351#define OMAP3430_EN_GPIO5_SHIFT 16 352#define OMAP3430_EN_GPIO4_MASK (1 << 15) 353#define OMAP3430_EN_GPIO4_SHIFT 15 354#define OMAP3430_EN_GPIO3_MASK (1 << 14) 355#define OMAP3430_EN_GPIO3_SHIFT 14 356#define OMAP3430_EN_GPIO2_MASK (1 << 13) 357#define OMAP3430_EN_GPIO2_SHIFT 13 358#define OMAP3430_EN_UART3_MASK (1 << 11) 359#define OMAP3430_EN_UART3_SHIFT 11 360#define OMAP3430_EN_GPT9_MASK (1 << 10) 361#define OMAP3430_EN_GPT9_SHIFT 10 362#define OMAP3430_EN_GPT8_MASK (1 << 9) 363#define OMAP3430_EN_GPT8_SHIFT 9 364#define OMAP3430_EN_GPT7_MASK (1 << 8) 365#define OMAP3430_EN_GPT7_SHIFT 8 366#define OMAP3430_EN_GPT6_MASK (1 << 7) 367#define OMAP3430_EN_GPT6_SHIFT 7 368#define OMAP3430_EN_GPT5_MASK (1 << 6) 369#define OMAP3430_EN_GPT5_SHIFT 6 370#define OMAP3430_EN_GPT4_MASK (1 << 5) 371#define OMAP3430_EN_GPT4_SHIFT 5 372#define OMAP3430_EN_GPT3_MASK (1 << 4) 373#define OMAP3430_EN_GPT3_SHIFT 4 374#define OMAP3430_EN_GPT2_MASK (1 << 3) 375#define OMAP3430_EN_GPT2_SHIFT 3 376 377/* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ 378/* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits 379 * be ST_* bits instead? */ 380#define OMAP3430_EN_MCBSP4_MASK (1 << 2) 381#define OMAP3430_EN_MCBSP4_SHIFT 2 382#define OMAP3430_EN_MCBSP3_MASK (1 << 1) 383#define OMAP3430_EN_MCBSP3_SHIFT 1 384#define OMAP3430_EN_MCBSP2_MASK (1 << 0) 385#define OMAP3430_EN_MCBSP2_SHIFT 0 386 387/* CM_IDLEST_PER, PM_WKST_PER shared bits */ 388#define OMAP3630_ST_UART4_SHIFT 18 389#define OMAP3630_ST_UART4_MASK (1 << 18) 390#define OMAP3430_ST_GPIO6_SHIFT 17 391#define OMAP3430_ST_GPIO6_MASK (1 << 17) 392#define OMAP3430_ST_GPIO5_SHIFT 16 393#define OMAP3430_ST_GPIO5_MASK (1 << 16) 394#define OMAP3430_ST_GPIO4_SHIFT 15 395#define OMAP3430_ST_GPIO4_MASK (1 << 15) 396#define OMAP3430_ST_GPIO3_SHIFT 14 397#define OMAP3430_ST_GPIO3_MASK (1 << 14) 398#define OMAP3430_ST_GPIO2_SHIFT 13 399#define OMAP3430_ST_GPIO2_MASK (1 << 13) 400#define OMAP3430_ST_UART3_SHIFT 11 401#define OMAP3430_ST_UART3_MASK (1 << 11) 402#define OMAP3430_ST_GPT9_SHIFT 10 403#define OMAP3430_ST_GPT9_MASK (1 << 10) 404#define OMAP3430_ST_GPT8_SHIFT 9 405#define OMAP3430_ST_GPT8_MASK (1 << 9) 406#define OMAP3430_ST_GPT7_SHIFT 8 407#define OMAP3430_ST_GPT7_MASK (1 << 8) 408#define OMAP3430_ST_GPT6_SHIFT 7 409#define OMAP3430_ST_GPT6_MASK (1 << 7) 410#define OMAP3430_ST_GPT5_SHIFT 6 411#define OMAP3430_ST_GPT5_MASK (1 << 6) 412#define OMAP3430_ST_GPT4_SHIFT 5 413#define OMAP3430_ST_GPT4_MASK (1 << 5) 414#define OMAP3430_ST_GPT3_SHIFT 4 415#define OMAP3430_ST_GPT3_MASK (1 << 4) 416#define OMAP3430_ST_GPT2_SHIFT 3 417#define OMAP3430_ST_GPT2_MASK (1 << 3) 418 419/* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ 420#define OMAP3430_EN_CORE_SHIFT 0 421#define OMAP3430_EN_CORE_MASK (1 << 0) 422 423 424 425/* 426 * Maximum time(us) it takes to output the signal WUCLKOUT of the last 427 * pad of the I/O ring after asserting WUCLKIN high. Tero measured 428 * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4 429 * microseconds on OMAP4, so this timeout may be too high. 430 */ 431#define MAX_IOPAD_LATCH_TIME 100 432# ifndef __ASSEMBLER__ 433 434#include <linux/delay.h> 435 436/** 437 * omap_test_timeout - busy-loop, testing a condition 438 * @cond: condition to test until it evaluates to true 439 * @timeout: maximum number of microseconds in the timeout 440 * @index: loop index (integer) 441 * 442 * Loop waiting for @cond to become true or until at least @timeout 443 * microseconds have passed. To use, define some integer @index in the 444 * calling code. After running, if @index == @timeout, then the loop has 445 * timed out. 446 */ 447#define omap_test_timeout(cond, timeout, index) \ 448({ \ 449 for (index = 0; index < timeout; index++) { \ 450 if (cond) \ 451 break; \ 452 udelay(1); \ 453 } \ 454}) 455 456/** 457 * struct omap_prcm_irq - describes a PRCM interrupt bit 458 * @name: a short name describing the interrupt type, e.g. "wkup" or "io" 459 * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs 460 * @priority: should this interrupt be handled before @priority=false IRQs? 461 * 462 * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers. 463 * On systems with multiple PRM MPU IRQ registers, the bitfields read from 464 * the registers are concatenated, so @offset could be > 31 on these systems - 465 * see omap_prm_irq_handler() for more details. I/O ring interrupts should 466 * have @priority set to true. 467 */ 468struct omap_prcm_irq { 469 const char *name; 470 unsigned int offset; 471 bool priority; 472}; 473 474/** 475 * struct omap_prcm_irq_setup - PRCM interrupt controller details 476 * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register 477 * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register 478 * @pm_ctrl: PRM register offset for the PRM_IO_PMCTRL register 479 * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers 480 * @nr_irqs: number of entries in the @irqs array 481 * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs) 482 * @irq: MPU IRQ asserted when a PRCM interrupt arrives 483 * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending 484 * @ocp_barrier: fn ptr to force buffered PRM writes to complete 485 * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs 486 * @restore_irqen: fn ptr to save and clear IRQENABLE regs 487 * @reconfigure_io_chain: fn ptr to reconfigure IO chain 488 * @saved_mask: IRQENABLE regs are saved here during suspend 489 * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true 490 * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init 491 * @suspended: set to true after Linux suspend code has called our ->prepare() 492 * @suspend_save_flag: set to true after IRQ masks have been saved and disabled 493 * 494 * @saved_mask, @priority_mask, @base_irq, @suspended, and 495 * @suspend_save_flag are populated dynamically, and are not to be 496 * specified in static initializers. 497 */ 498struct omap_prcm_irq_setup { 499 u16 ack; 500 u16 mask; 501 u16 pm_ctrl; 502 u8 nr_regs; 503 u8 nr_irqs; 504 const struct omap_prcm_irq *irqs; 505 int irq; 506 void (*read_pending_irqs)(unsigned long *events); 507 void (*ocp_barrier)(void); 508 void (*save_and_clear_irqen)(u32 *saved_mask); 509 void (*restore_irqen)(u32 *saved_mask); 510 void (*reconfigure_io_chain)(void); 511 u32 *saved_mask; 512 u32 *priority_mask; 513 int base_irq; 514 bool suspended; 515 bool suspend_save_flag; 516}; 517 518/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */ 519#define OMAP_PRCM_IRQ(_name, _offset, _priority) { \ 520 .name = _name, \ 521 .offset = _offset, \ 522 .priority = _priority \ 523 } 524 525struct omap_domain_base { 526 u32 pa; 527 void __iomem *va; 528 s16 offset; 529}; 530 531/** 532 * struct omap_prcm_init_data - PRCM driver init data 533 * @index: clock memory mapping index to be used 534 * @mem: IO mem pointer for this module 535 * @phys: IO mem physical base address for this module 536 * @offset: module base address offset from the IO base 537 * @flags: PRCM module init flags 538 * @device_inst_offset: device instance offset within the module address space 539 * @init: low level PRCM init function for this module 540 * @np: device node for this PRCM module 541 */ 542struct omap_prcm_init_data { 543 int index; 544 void __iomem *mem; 545 u32 phys; 546 s16 offset; 547 u16 flags; 548 s32 device_inst_offset; 549 int (*init)(const struct omap_prcm_init_data *data); 550 struct device_node *np; 551}; 552 553extern void omap_prcm_irq_cleanup(void); 554extern int omap_prcm_register_chain_handler( 555 struct omap_prcm_irq_setup *irq_setup); 556extern int omap_prcm_event_to_irq(const char *event); 557extern void omap_prcm_irq_prepare(void); 558extern void omap_prcm_irq_complete(void); 559 560# endif 561 562#endif 563 564