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13#include <linux/types.h>
14#include <linux/init.h>
15#include <linux/pgtable.h>
16
17#include <asm/numachip/numachip.h>
18#include <asm/numachip/numachip_csr.h>
19
20
21#include "local.h"
22
23u8 numachip_system __read_mostly;
24static const struct apic apic_numachip1;
25static const struct apic apic_numachip2;
26static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly;
27
28static unsigned int numachip1_get_apic_id(unsigned long x)
29{
30 unsigned long value;
31 unsigned int id = (x >> 24) & 0xff;
32
33 if (static_cpu_has(X86_FEATURE_NODEID_MSR)) {
34 rdmsrl(MSR_FAM10H_NODE_ID, value);
35 id |= (value << 2) & 0xff00;
36 }
37
38 return id;
39}
40
41static u32 numachip1_set_apic_id(unsigned int id)
42{
43 return (id & 0xff) << 24;
44}
45
46static unsigned int numachip2_get_apic_id(unsigned long x)
47{
48 u64 mcfg;
49
50 rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg);
51 return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24);
52}
53
54static u32 numachip2_set_apic_id(unsigned int id)
55{
56 return id << 24;
57}
58
59static int numachip_apic_id_valid(u32 apicid)
60{
61
62 return 1;
63}
64
65static int numachip_apic_id_registered(void)
66{
67 return 1;
68}
69
70static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
71{
72 return initial_apic_id >> index_msb;
73}
74
75static void numachip1_apic_icr_write(int apicid, unsigned int val)
76{
77 write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val);
78}
79
80static void numachip2_apic_icr_write(int apicid, unsigned int val)
81{
82 numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val);
83}
84
85static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
86{
87 numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);
88 numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP |
89 (start_rip >> 12));
90
91 return 0;
92}
93
94static void numachip_send_IPI_one(int cpu, int vector)
95{
96 int local_apicid, apicid = per_cpu(x86_cpu_to_apicid, cpu);
97 unsigned int dmode;
98
99 preempt_disable();
100 local_apicid = __this_cpu_read(x86_cpu_to_apicid);
101
102
103 if (!((apicid ^ local_apicid) >> NUMACHIP_LAPIC_BITS)) {
104 unsigned long flags;
105
106 local_irq_save(flags);
107 __default_send_IPI_dest_field(apicid, vector,
108 APIC_DEST_PHYSICAL);
109 local_irq_restore(flags);
110 preempt_enable();
111 return;
112 }
113 preempt_enable();
114
115 dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED;
116 numachip_apic_icr_write(apicid, dmode | vector);
117}
118
119static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
120{
121 unsigned int cpu;
122
123 for_each_cpu(cpu, mask)
124 numachip_send_IPI_one(cpu, vector);
125}
126
127static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
128 int vector)
129{
130 unsigned int this_cpu = smp_processor_id();
131 unsigned int cpu;
132
133 for_each_cpu(cpu, mask) {
134 if (cpu != this_cpu)
135 numachip_send_IPI_one(cpu, vector);
136 }
137}
138
139static void numachip_send_IPI_allbutself(int vector)
140{
141 unsigned int this_cpu = smp_processor_id();
142 unsigned int cpu;
143
144 for_each_online_cpu(cpu) {
145 if (cpu != this_cpu)
146 numachip_send_IPI_one(cpu, vector);
147 }
148}
149
150static void numachip_send_IPI_all(int vector)
151{
152 numachip_send_IPI_mask(cpu_online_mask, vector);
153}
154
155static void numachip_send_IPI_self(int vector)
156{
157 apic_write(APIC_SELF_IPI, vector);
158}
159
160static int __init numachip1_probe(void)
161{
162 return apic == &apic_numachip1;
163}
164
165static int __init numachip2_probe(void)
166{
167 return apic == &apic_numachip2;
168}
169
170static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
171{
172 u64 val;
173 u32 nodes = 1;
174
175 this_cpu_write(cpu_llc_id, node);
176
177
178 if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
179 rdmsrl(MSR_FAM10H_NODE_ID, val);
180 nodes = ((val >> 3) & 7) + 1;
181 }
182
183 c->phys_proc_id = node / nodes;
184}
185
186static int __init numachip_system_init(void)
187{
188
189 switch (numachip_system) {
190 case 1:
191 init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
192 numachip_apic_icr_write = numachip1_apic_icr_write;
193 break;
194 case 2:
195 init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE);
196 numachip_apic_icr_write = numachip2_apic_icr_write;
197 break;
198 default:
199 return 0;
200 }
201
202 x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
203 x86_init.pci.arch_init = pci_numachip_init;
204
205 return 0;
206}
207early_initcall(numachip_system_init);
208
209static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
210{
211 if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
212 (strncmp(oem_table_id, "NCONNECT", 8) != 0))
213 return 0;
214
215 numachip_system = 1;
216
217 return 1;
218}
219
220static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
221{
222 if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
223 (strncmp(oem_table_id, "NCONECT2", 8) != 0))
224 return 0;
225
226 numachip_system = 2;
227
228 return 1;
229}
230
231
232static void numachip_apic_wait_icr_idle(void)
233{
234}
235
236
237static u32 numachip_safe_apic_wait_icr_idle(void)
238{
239 return 0;
240}
241
242static const struct apic apic_numachip1 __refconst = {
243 .name = "NumaConnect system",
244 .probe = numachip1_probe,
245 .acpi_madt_oem_check = numachip1_acpi_madt_oem_check,
246 .apic_id_valid = numachip_apic_id_valid,
247 .apic_id_registered = numachip_apic_id_registered,
248
249 .delivery_mode = APIC_DELIVERY_MODE_FIXED,
250 .dest_mode_logical = false,
251
252 .disable_esr = 0,
253
254 .check_apicid_used = NULL,
255 .init_apic_ldr = flat_init_apic_ldr,
256 .ioapic_phys_id_map = NULL,
257 .setup_apic_routing = NULL,
258 .cpu_present_to_apicid = default_cpu_present_to_apicid,
259 .apicid_to_cpu_present = NULL,
260 .check_phys_apicid_present = default_check_phys_apicid_present,
261 .phys_pkg_id = numachip_phys_pkg_id,
262
263 .get_apic_id = numachip1_get_apic_id,
264 .set_apic_id = numachip1_set_apic_id,
265
266 .calc_dest_apicid = apic_default_calc_apicid,
267
268 .send_IPI = numachip_send_IPI_one,
269 .send_IPI_mask = numachip_send_IPI_mask,
270 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
271 .send_IPI_allbutself = numachip_send_IPI_allbutself,
272 .send_IPI_all = numachip_send_IPI_all,
273 .send_IPI_self = numachip_send_IPI_self,
274
275 .wakeup_secondary_cpu = numachip_wakeup_secondary,
276 .inquire_remote_apic = NULL,
277
278 .read = native_apic_mem_read,
279 .write = native_apic_mem_write,
280 .eoi_write = native_apic_mem_write,
281 .icr_read = native_apic_icr_read,
282 .icr_write = native_apic_icr_write,
283 .wait_icr_idle = numachip_apic_wait_icr_idle,
284 .safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle,
285};
286
287apic_driver(apic_numachip1);
288
289static const struct apic apic_numachip2 __refconst = {
290 .name = "NumaConnect2 system",
291 .probe = numachip2_probe,
292 .acpi_madt_oem_check = numachip2_acpi_madt_oem_check,
293 .apic_id_valid = numachip_apic_id_valid,
294 .apic_id_registered = numachip_apic_id_registered,
295
296 .delivery_mode = APIC_DELIVERY_MODE_FIXED,
297 .dest_mode_logical = false,
298
299 .disable_esr = 0,
300
301 .check_apicid_used = NULL,
302 .init_apic_ldr = flat_init_apic_ldr,
303 .ioapic_phys_id_map = NULL,
304 .setup_apic_routing = NULL,
305 .cpu_present_to_apicid = default_cpu_present_to_apicid,
306 .apicid_to_cpu_present = NULL,
307 .check_phys_apicid_present = default_check_phys_apicid_present,
308 .phys_pkg_id = numachip_phys_pkg_id,
309
310 .get_apic_id = numachip2_get_apic_id,
311 .set_apic_id = numachip2_set_apic_id,
312
313 .calc_dest_apicid = apic_default_calc_apicid,
314
315 .send_IPI = numachip_send_IPI_one,
316 .send_IPI_mask = numachip_send_IPI_mask,
317 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
318 .send_IPI_allbutself = numachip_send_IPI_allbutself,
319 .send_IPI_all = numachip_send_IPI_all,
320 .send_IPI_self = numachip_send_IPI_self,
321
322 .wakeup_secondary_cpu = numachip_wakeup_secondary,
323 .inquire_remote_apic = NULL,
324
325 .read = native_apic_mem_read,
326 .write = native_apic_mem_write,
327 .eoi_write = native_apic_mem_write,
328 .icr_read = native_apic_icr_read,
329 .icr_write = native_apic_icr_write,
330 .wait_icr_idle = numachip_apic_wait_icr_idle,
331 .safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle,
332};
333
334apic_driver(apic_numachip2);
335
