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11#include <linux/crash_dump.h>
12#include <linux/cpuhotplug.h>
13#include <linux/cpumask.h>
14#include <linux/proc_fs.h>
15#include <linux/memory.h>
16#include <linux/export.h>
17#include <linux/pci.h>
18#include <linux/acpi.h>
19#include <linux/efi.h>
20
21#include <asm/e820/api.h>
22#include <asm/uv/uv_mmrs.h>
23#include <asm/uv/uv_hub.h>
24#include <asm/uv/bios.h>
25#include <asm/uv/uv.h>
26#include <asm/apic.h>
27
28static enum uv_system_type uv_system_type;
29static int uv_hubbed_system;
30static int uv_hubless_system;
31static u64 gru_start_paddr, gru_end_paddr;
32static union uvh_apicid uvh_apicid;
33static int uv_node_id;
34
35
36static u8 uv_archtype[UV_AT_SIZE + 1];
37static u8 oem_id[ACPI_OEM_ID_SIZE + 1];
38static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
39
40
41static struct {
42 unsigned int apicid_shift;
43 unsigned int apicid_mask;
44 unsigned int socketid_shift;
45 unsigned int pnode_mask;
46 unsigned int nasid_shift;
47 unsigned int gpa_shift;
48 unsigned int gnode_shift;
49 unsigned int m_skt;
50 unsigned int n_skt;
51} uv_cpuid;
52
53static int uv_min_hub_revision_id;
54
55static struct apic apic_x2apic_uv_x;
56static struct uv_hub_info_s uv_hub_info_node0;
57
58
59static int disable_uv_undefined_panic = 1;
60
61unsigned long uv_undefined(char *str)
62{
63 if (likely(!disable_uv_undefined_panic))
64 panic("UV: error: undefined MMR: %s\n", str);
65 else
66 pr_crit("UV: error: undefined MMR: %s\n", str);
67
68
69 return ~0ul;
70}
71EXPORT_SYMBOL(uv_undefined);
72
73static unsigned long __init uv_early_read_mmr(unsigned long addr)
74{
75 unsigned long val, *mmr;
76
77 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
78 val = *mmr;
79 early_iounmap(mmr, sizeof(*mmr));
80
81 return val;
82}
83
84static inline bool is_GRU_range(u64 start, u64 end)
85{
86 if (!gru_start_paddr)
87 return false;
88
89 return start >= gru_start_paddr && end <= gru_end_paddr;
90}
91
92static bool uv_is_untracked_pat_range(u64 start, u64 end)
93{
94 return is_ISA_range(start, end) || is_GRU_range(start, end);
95}
96
97static void __init early_get_pnodeid(void)
98{
99 int pnode;
100
101 uv_cpuid.m_skt = 0;
102 if (UVH_RH10_GAM_ADDR_MAP_CONFIG) {
103 union uvh_rh10_gam_addr_map_config_u m_n_config;
104
105 m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG);
106 uv_cpuid.n_skt = m_n_config.s.n_skt;
107 uv_cpuid.nasid_shift = 0;
108 } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) {
109 union uvh_rh_gam_addr_map_config_u m_n_config;
110
111 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG);
112 uv_cpuid.n_skt = m_n_config.s.n_skt;
113 if (is_uv(UV3))
114 uv_cpuid.m_skt = m_n_config.s3.m_skt;
115 if (is_uv(UV2))
116 uv_cpuid.m_skt = m_n_config.s2.m_skt;
117 uv_cpuid.nasid_shift = 1;
118 } else {
119 unsigned long GAM_ADDR_MAP_CONFIG = 0;
120
121 WARN(GAM_ADDR_MAP_CONFIG == 0,
122 "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n");
123 uv_cpuid.n_skt = 0;
124 uv_cpuid.nasid_shift = 0;
125 }
126
127 if (is_uv(UV4|UVY))
128 uv_cpuid.gnode_shift = 2;
129
130 uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1;
131 pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask;
132 uv_cpuid.gpa_shift = 46;
133
134 pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n",
135 uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode);
136}
137
138
139static int __init early_set_hub_type(void)
140{
141 union uvh_node_id_u node_id;
142
143
144
145
146
147
148
149
150 node_id.v = uv_early_read_mmr(UVH_NODE_ID);
151 uv_node_id = node_id.sx.node_id;
152
153 switch (node_id.s.part_number) {
154
155 case UV5_HUB_PART_NUMBER:
156 uv_min_hub_revision_id = node_id.s.revision
157 + UV5_HUB_REVISION_BASE;
158 uv_hub_type_set(UV5);
159 break;
160
161
162 case UV4_HUB_PART_NUMBER:
163 uv_min_hub_revision_id = node_id.s.revision
164 + UV4_HUB_REVISION_BASE - 1;
165 uv_hub_type_set(UV4);
166 if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE)
167 uv_hub_type_set(UV4|UV4A);
168 break;
169
170 case UV3_HUB_PART_NUMBER:
171 case UV3_HUB_PART_NUMBER_X:
172 uv_min_hub_revision_id = node_id.s.revision
173 + UV3_HUB_REVISION_BASE;
174 uv_hub_type_set(UV3);
175 break;
176
177 case UV2_HUB_PART_NUMBER:
178 case UV2_HUB_PART_NUMBER_X:
179 uv_min_hub_revision_id = node_id.s.revision
180 + UV2_HUB_REVISION_BASE - 1;
181 uv_hub_type_set(UV2);
182 break;
183
184 default:
185 return 0;
186 }
187
188 pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n",
189 node_id.s.part_number, node_id.s.revision,
190 uv_min_hub_revision_id, is_uv(~0));
191
192 return 1;
193}
194
195static void __init uv_tsc_check_sync(void)
196{
197 u64 mmr;
198 int sync_state;
199 int mmr_shift;
200 char *state;
201
202
203 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
204 mmr_shift =
205 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
206 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
207
208
209 switch (sync_state) {
210 case UVH_TSC_SYNC_VALID:
211 state = "in sync";
212 mark_tsc_async_resets("UV BIOS");
213 break;
214
215
216 case UVH_TSC_SYNC_UNKNOWN:
217 state = "unknown";
218 break;
219
220
221 default:
222 state = "unstable";
223 mark_tsc_unstable("UV BIOS");
224 break;
225 }
226 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
227}
228
229
230#define uvxy_field(sname, field, undef) ( \
231 is_uv(UV4A) ? sname.s4a.field : \
232 is_uv(UV4) ? sname.s4.field : \
233 is_uv(UV3) ? sname.s3.field : \
234 undef)
235
236
237
238#define SMT_LEVEL 0
239#define INVALID_TYPE 0
240#define SMT_TYPE 1
241#define CORE_TYPE 2
242#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
243#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
244
245static void set_x2apic_bits(void)
246{
247 unsigned int eax, ebx, ecx, edx, sub_index;
248 unsigned int sid_shift;
249
250 cpuid(0, &eax, &ebx, &ecx, &edx);
251 if (eax < 0xb) {
252 pr_info("UV: CPU does not have CPUID.11\n");
253 return;
254 }
255
256 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
257 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
258 pr_info("UV: CPUID.11 not implemented\n");
259 return;
260 }
261
262 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
263 sub_index = 1;
264 do {
265 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
266 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
267 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
268 break;
269 }
270 sub_index++;
271 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
272
273 uv_cpuid.apicid_shift = 0;
274 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
275 uv_cpuid.socketid_shift = sid_shift;
276}
277
278static void __init early_get_apic_socketid_shift(void)
279{
280 if (is_uv2_hub() || is_uv3_hub())
281 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
282
283 set_x2apic_bits();
284
285 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
286 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
287}
288
289static void __init uv_stringify(int len, char *to, char *from)
290{
291
292 strncpy(to, from, len-1);
293
294
295 (void)strim(to);
296}
297
298
299static unsigned long __init early_find_archtype(struct uv_systab *st)
300{
301 int i;
302
303 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
304 unsigned long ptr = st->entry[i].offset;
305
306 if (!ptr)
307 continue;
308 ptr += (unsigned long)st;
309 if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE)
310 return ptr;
311 }
312 return 0;
313}
314
315
316static int __init decode_arch_type(unsigned long ptr)
317{
318 struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr;
319 int n = strlen(uv_ate->archtype);
320
321 if (n > 0 && n < sizeof(uv_ate->archtype)) {
322 pr_info("UV: UVarchtype received from BIOS\n");
323 uv_stringify(sizeof(uv_archtype), uv_archtype, uv_ate->archtype);
324 return 1;
325 }
326 return 0;
327}
328
329
330static int __init early_get_arch_type(void)
331{
332 unsigned long uvst_physaddr, uvst_size, ptr;
333 struct uv_systab *st;
334 u32 rev;
335 int ret;
336
337 uvst_physaddr = get_uv_systab_phys(0);
338 if (!uvst_physaddr)
339 return 0;
340
341 st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab));
342 if (!st) {
343 pr_err("UV: Cannot access UVsystab, remap failed\n");
344 return 0;
345 }
346
347 rev = st->revision;
348 if (rev < UV_SYSTAB_VERSION_UV5) {
349 early_memunmap(st, sizeof(struct uv_systab));
350 return 0;
351 }
352
353 uvst_size = st->size;
354 early_memunmap(st, sizeof(struct uv_systab));
355 st = early_memremap_ro(uvst_physaddr, uvst_size);
356 if (!st) {
357 pr_err("UV: Cannot access UVarchtype, remap failed\n");
358 return 0;
359 }
360
361 ptr = early_find_archtype(st);
362 if (!ptr) {
363 early_memunmap(st, uvst_size);
364 return 0;
365 }
366
367 ret = decode_arch_type(ptr);
368 early_memunmap(st, uvst_size);
369 return ret;
370}
371
372
373static void __init early_set_apic_mode(void)
374{
375 if (x2apic_enabled())
376 uv_system_type = UV_X2APIC;
377 else
378 uv_system_type = UV_LEGACY_APIC;
379}
380
381static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id)
382{
383
384 uv_stringify(sizeof(oem_id), oem_id, _oem_id);
385
386
387 if (!early_get_arch_type())
388
389
390 uv_stringify(sizeof(uv_archtype), uv_archtype, oem_id);
391
392
393 if (strncmp(uv_archtype, "SGI", 3) != 0) {
394
395
396 if (strncmp(uv_archtype, "NSGI", 4) != 0)
397
398
399 return 0;
400
401
402 uv_hubless_system = 0x01;
403
404
405 if (strncmp(uv_archtype, "NSGI5", 5) == 0)
406 uv_hubless_system |= 0x20;
407
408
409 else if (strncmp(uv_archtype, "NSGI4", 5) == 0)
410 uv_hubless_system |= 0x10;
411
412
413 else
414 uv_hubless_system |= 0x8;
415
416
417 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
418
419 pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n",
420 oem_id, oem_table_id, uv_system_type, uv_hubless_system);
421
422 return 0;
423 }
424
425 if (numa_off) {
426 pr_err("UV: NUMA is off, disabling UV support\n");
427 return 0;
428 }
429
430
431 uv_hub_info->hub_revision =
432 !strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE :
433 !strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
434 !strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
435 !strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0;
436
437 switch (uv_hub_info->hub_revision) {
438 case UV5_HUB_REVISION_BASE:
439 uv_hubbed_system = 0x21;
440 uv_hub_type_set(UV5);
441 break;
442
443 case UV4_HUB_REVISION_BASE:
444 uv_hubbed_system = 0x11;
445 uv_hub_type_set(UV4);
446 break;
447
448 case UV3_HUB_REVISION_BASE:
449 uv_hubbed_system = 0x9;
450 uv_hub_type_set(UV3);
451 break;
452
453 case UV2_HUB_REVISION_BASE:
454 uv_hubbed_system = 0x5;
455 uv_hub_type_set(UV2);
456 break;
457
458 default:
459 return 0;
460 }
461
462
463 early_set_hub_type();
464
465
466 early_set_apic_mode();
467 early_get_pnodeid();
468 early_get_apic_socketid_shift();
469 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
470 x86_platform.nmi_init = uv_nmi_init;
471 uv_tsc_check_sync();
472
473 return 1;
474}
475
476
477static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
478{
479
480 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
481
482
483 if (uv_set_system_type(_oem_id, _oem_table_id) == 0)
484 return 0;
485
486
487 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
488
489 pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n",
490 oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY),
491 uv_min_hub_revision_id);
492
493 return 0;
494}
495
496enum uv_system_type get_uv_system_type(void)
497{
498 return uv_system_type;
499}
500
501int uv_get_hubless_system(void)
502{
503 return uv_hubless_system;
504}
505EXPORT_SYMBOL_GPL(uv_get_hubless_system);
506
507ssize_t uv_get_archtype(char *buf, int len)
508{
509 return scnprintf(buf, len, "%s/%s", uv_archtype, oem_table_id);
510}
511EXPORT_SYMBOL_GPL(uv_get_archtype);
512
513int is_uv_system(void)
514{
515 return uv_system_type != UV_NONE;
516}
517EXPORT_SYMBOL_GPL(is_uv_system);
518
519int is_uv_hubbed(int uvtype)
520{
521 return (uv_hubbed_system & uvtype);
522}
523EXPORT_SYMBOL_GPL(is_uv_hubbed);
524
525static int is_uv_hubless(int uvtype)
526{
527 return (uv_hubless_system & uvtype);
528}
529
530void **__uv_hub_info_list;
531EXPORT_SYMBOL_GPL(__uv_hub_info_list);
532
533DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
534EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
535
536short uv_possible_blades;
537EXPORT_SYMBOL_GPL(uv_possible_blades);
538
539unsigned long sn_rtc_cycles_per_second;
540EXPORT_SYMBOL(sn_rtc_cycles_per_second);
541
542
543static __initdata unsigned short *_node_to_pnode;
544static __initdata unsigned short _min_socket, _max_socket;
545static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
546static __initdata struct uv_gam_range_entry *uv_gre_table;
547static __initdata struct uv_gam_parameters *uv_gp_table;
548static __initdata unsigned short *_socket_to_node;
549static __initdata unsigned short *_socket_to_pnode;
550static __initdata unsigned short *_pnode_to_socket;
551
552static __initdata struct uv_gam_range_s *_gr_table;
553
554#define SOCK_EMPTY ((unsigned short)~0)
555
556
557static unsigned long mem_block_size __initdata = (2UL << 30);
558
559
560static int __init parse_mem_block_size(char *ptr)
561{
562 unsigned long size = memparse(ptr, NULL);
563
564
565 mem_block_size = size;
566 return 0;
567}
568early_param("uv_memblksize", parse_mem_block_size);
569
570static __init int adj_blksize(u32 lgre)
571{
572 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
573 unsigned long size;
574
575 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
576 if (IS_ALIGNED(base, size))
577 break;
578
579 if (size >= mem_block_size)
580 return 0;
581
582 mem_block_size = size;
583 return 1;
584}
585
586static __init void set_block_size(void)
587{
588 unsigned int order = ffs(mem_block_size);
589
590 if (order) {
591
592 set_memory_block_size_order(order - 1);
593 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
594 } else {
595
596 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
597 set_memory_block_size_order(31);
598 }
599}
600
601
602static __init void build_uv_gr_table(void)
603{
604 struct uv_gam_range_entry *gre = uv_gre_table;
605 struct uv_gam_range_s *grt;
606 unsigned long last_limit = 0, ram_limit = 0;
607 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
608
609 if (!gre)
610 return;
611
612 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
613 grt = kzalloc(bytes, GFP_KERNEL);
614 BUG_ON(!grt);
615 _gr_table = grt;
616
617 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
618 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
619 if (!ram_limit) {
620
621 ram_limit = last_limit;
622 last_limit = gre->limit;
623 lsid++;
624 continue;
625 }
626 last_limit = gre->limit;
627 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
628 continue;
629 }
630 if (_max_socket < gre->sockid) {
631 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
632 continue;
633 }
634 sid = gre->sockid - _min_socket;
635 if (lsid < sid) {
636
637 grt = &_gr_table[indx];
638 grt->base = lindx;
639 grt->nasid = gre->nasid;
640 grt->limit = last_limit = gre->limit;
641 lsid = sid;
642 lindx = indx++;
643 continue;
644 }
645
646 if (lsid == sid && !ram_limit) {
647
648 if (grt->limit == last_limit) {
649 grt->limit = last_limit = gre->limit;
650 continue;
651 }
652 }
653
654 if (!ram_limit) {
655 grt++;
656 grt->base = lindx;
657 grt->nasid = gre->nasid;
658 grt->limit = last_limit = gre->limit;
659 continue;
660 }
661
662 grt++;
663
664 grt->base = grt - _gr_table;
665 grt->nasid = gre->nasid;
666 grt->limit = last_limit = gre->limit;
667 lsid++;
668 }
669
670
671 grt++;
672 i = grt - _gr_table;
673 if (i < _gr_table_len) {
674 void *ret;
675
676 bytes = i * sizeof(struct uv_gam_range_s);
677 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
678 if (ret) {
679 _gr_table = ret;
680 _gr_table_len = i;
681 }
682 }
683
684
685 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
686 unsigned long start, end;
687 int gb = grt->base;
688
689 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
690 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
691
692 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
693 }
694}
695
696static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
697{
698 unsigned long val;
699 int pnode;
700
701 pnode = uv_apicid_to_pnode(phys_apicid);
702
703 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
704 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
705 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
706 APIC_DM_INIT;
707
708 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
709
710 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
711 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
712 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
713 APIC_DM_STARTUP;
714
715 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
716
717 return 0;
718}
719
720static void uv_send_IPI_one(int cpu, int vector)
721{
722 unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu);
723 int pnode = uv_apicid_to_pnode(apicid);
724 unsigned long dmode, val;
725
726 if (vector == NMI_VECTOR)
727 dmode = APIC_DELIVERY_MODE_NMI;
728 else
729 dmode = APIC_DELIVERY_MODE_FIXED;
730
731 val = (1UL << UVH_IPI_INT_SEND_SHFT) |
732 (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
733 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
734 (vector << UVH_IPI_INT_VECTOR_SHFT);
735
736 uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
737}
738
739static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
740{
741 unsigned int cpu;
742
743 for_each_cpu(cpu, mask)
744 uv_send_IPI_one(cpu, vector);
745}
746
747static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
748{
749 unsigned int this_cpu = smp_processor_id();
750 unsigned int cpu;
751
752 for_each_cpu(cpu, mask) {
753 if (cpu != this_cpu)
754 uv_send_IPI_one(cpu, vector);
755 }
756}
757
758static void uv_send_IPI_allbutself(int vector)
759{
760 unsigned int this_cpu = smp_processor_id();
761 unsigned int cpu;
762
763 for_each_online_cpu(cpu) {
764 if (cpu != this_cpu)
765 uv_send_IPI_one(cpu, vector);
766 }
767}
768
769static void uv_send_IPI_all(int vector)
770{
771 uv_send_IPI_mask(cpu_online_mask, vector);
772}
773
774static int uv_apic_id_valid(u32 apicid)
775{
776 return 1;
777}
778
779static int uv_apic_id_registered(void)
780{
781 return 1;
782}
783
784static void uv_init_apic_ldr(void)
785{
786}
787
788static u32 apic_uv_calc_apicid(unsigned int cpu)
789{
790 return apic_default_calc_apicid(cpu);
791}
792
793static unsigned int x2apic_get_apic_id(unsigned long id)
794{
795 return id;
796}
797
798static u32 set_apic_id(unsigned int id)
799{
800 return id;
801}
802
803static unsigned int uv_read_apic_id(void)
804{
805 return x2apic_get_apic_id(apic_read(APIC_ID));
806}
807
808static int uv_phys_pkg_id(int initial_apicid, int index_msb)
809{
810 return uv_read_apic_id() >> index_msb;
811}
812
813static void uv_send_IPI_self(int vector)
814{
815 apic_write(APIC_SELF_IPI, vector);
816}
817
818static int uv_probe(void)
819{
820 return apic == &apic_x2apic_uv_x;
821}
822
823static struct apic apic_x2apic_uv_x __ro_after_init = {
824
825 .name = "UV large system",
826 .probe = uv_probe,
827 .acpi_madt_oem_check = uv_acpi_madt_oem_check,
828 .apic_id_valid = uv_apic_id_valid,
829 .apic_id_registered = uv_apic_id_registered,
830
831 .delivery_mode = APIC_DELIVERY_MODE_FIXED,
832 .dest_mode_logical = false,
833
834 .disable_esr = 0,
835
836 .check_apicid_used = NULL,
837 .init_apic_ldr = uv_init_apic_ldr,
838 .ioapic_phys_id_map = NULL,
839 .setup_apic_routing = NULL,
840 .cpu_present_to_apicid = default_cpu_present_to_apicid,
841 .apicid_to_cpu_present = NULL,
842 .check_phys_apicid_present = default_check_phys_apicid_present,
843 .phys_pkg_id = uv_phys_pkg_id,
844
845 .get_apic_id = x2apic_get_apic_id,
846 .set_apic_id = set_apic_id,
847
848 .calc_dest_apicid = apic_uv_calc_apicid,
849
850 .send_IPI = uv_send_IPI_one,
851 .send_IPI_mask = uv_send_IPI_mask,
852 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself,
853 .send_IPI_allbutself = uv_send_IPI_allbutself,
854 .send_IPI_all = uv_send_IPI_all,
855 .send_IPI_self = uv_send_IPI_self,
856
857 .wakeup_secondary_cpu = uv_wakeup_secondary,
858 .inquire_remote_apic = NULL,
859
860 .read = native_apic_msr_read,
861 .write = native_apic_msr_write,
862 .eoi_write = native_apic_msr_eoi_write,
863 .icr_read = native_x2apic_icr_read,
864 .icr_write = native_x2apic_icr_write,
865 .wait_icr_idle = native_x2apic_wait_icr_idle,
866 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
867};
868
869#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
870#define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT
871
872static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
873{
874 union uvh_rh_gam_alias_2_overlay_config_u alias;
875 union uvh_rh_gam_alias_2_redirect_config_u redirect;
876 unsigned long m_redirect;
877 unsigned long m_overlay;
878 int i;
879
880 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
881 switch (i) {
882 case 0:
883 m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG;
884 m_overlay = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG;
885 break;
886 case 1:
887 m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG;
888 m_overlay = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG;
889 break;
890 case 2:
891 m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG;
892 m_overlay = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG;
893 break;
894 }
895 alias.v = uv_read_local_mmr(m_overlay);
896 if (alias.s.enable && alias.s.base == 0) {
897 *size = (1UL << alias.s.m_alias);
898 redirect.v = uv_read_local_mmr(m_redirect);
899 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
900 return;
901 }
902 }
903 *base = *size = 0;
904}
905
906enum map_type {map_wb, map_uc};
907static const char * const mt[] = { "WB", "UC" };
908
909static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
910{
911 unsigned long bytes, paddr;
912
913 paddr = base << pshift;
914 bytes = (1UL << bshift) * (max_pnode + 1);
915 if (!paddr) {
916 pr_info("UV: Map %s_HI base address NULL\n", id);
917 return;
918 }
919 if (map_type == map_uc)
920 init_extra_mapping_uc(paddr, bytes);
921 else
922 init_extra_mapping_wb(paddr, bytes);
923
924 pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n",
925 id, paddr, paddr + bytes, mt[map_type], max_pnode + 1);
926}
927
928static __init void map_gru_high(int max_pnode)
929{
930 union uvh_rh_gam_gru_overlay_config_u gru;
931 unsigned long mask, base;
932 int shift;
933
934 if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) {
935 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG);
936 shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
937 mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
938 } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) {
939 gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG);
940 shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
941 mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
942 } else {
943 pr_err("UV: GRU unavailable (no MMR)\n");
944 return;
945 }
946
947 if (!gru.s.enable) {
948 pr_info("UV: GRU disabled (by BIOS)\n");
949 return;
950 }
951
952 base = (gru.v & mask) >> shift;
953 map_high("GRU", base, shift, shift, max_pnode, map_wb);
954 gru_start_paddr = ((u64)base << shift);
955 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
956}
957
958static __init void map_mmr_high(int max_pnode)
959{
960 unsigned long base;
961 int shift;
962 bool enable;
963
964 if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) {
965 union uvh_rh10_gam_mmr_overlay_config_u mmr;
966
967 mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG);
968 enable = mmr.s.enable;
969 base = mmr.s.base;
970 shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
971 } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) {
972 union uvh_rh_gam_mmr_overlay_config_u mmr;
973
974 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG);
975 enable = mmr.s.enable;
976 base = mmr.s.base;
977 shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
978 } else {
979 pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n",
980 __func__);
981 return;
982 }
983
984 if (enable)
985 map_high("MMR", base, shift, shift, max_pnode, map_uc);
986 else
987 pr_info("UV: MMR disabled\n");
988}
989
990
991enum mmioh_arch {
992 UV2_MMIOH = -1,
993 UVY_MMIOH0, UVY_MMIOH1,
994 UVX_MMIOH0, UVX_MMIOH1,
995};
996
997
998static void __init calc_mmioh_map(enum mmioh_arch index,
999 int min_pnode, int max_pnode,
1000 int shift, unsigned long base, int m_io, int n_io)
1001{
1002 unsigned long mmr, nasid_mask;
1003 int nasid, min_nasid, max_nasid, lnasid, mapped;
1004 int i, fi, li, n, max_io;
1005 char id[8];
1006
1007
1008 if (index == UV2_MMIOH) {
1009 strncpy(id, "MMIOH", sizeof(id));
1010 max_io = max_pnode;
1011 mapped = 0;
1012 goto map_exit;
1013 }
1014
1015
1016 switch (index) {
1017 case UVY_MMIOH0:
1018 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0;
1019 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
1020 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1021 min_nasid = min_pnode;
1022 max_nasid = max_pnode;
1023 mapped = 1;
1024 break;
1025 case UVY_MMIOH1:
1026 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1;
1027 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
1028 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1029 min_nasid = min_pnode;
1030 max_nasid = max_pnode;
1031 mapped = 1;
1032 break;
1033 case UVX_MMIOH0:
1034 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0;
1035 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
1036 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1037 min_nasid = min_pnode * 2;
1038 max_nasid = max_pnode * 2;
1039 mapped = 1;
1040 break;
1041 case UVX_MMIOH1:
1042 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1;
1043 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
1044 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1045 min_nasid = min_pnode * 2;
1046 max_nasid = max_pnode * 2;
1047 mapped = 1;
1048 break;
1049 default:
1050 pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index);
1051 return;
1052 }
1053
1054
1055 snprintf(id, sizeof(id), "MMIOH%d", index%2);
1056
1057 max_io = lnasid = fi = li = -1;
1058 for (i = 0; i < n; i++) {
1059 unsigned long m_redirect = mmr + i * 8;
1060 unsigned long redirect = uv_read_local_mmr(m_redirect);
1061
1062 nasid = redirect & nasid_mask;
1063 if (i == 0)
1064 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
1065 id, redirect, m_redirect, nasid);
1066
1067
1068 if (nasid < min_nasid || max_nasid < nasid) {
1069 pr_err("UV:%s:Invalid NASID:%x (range:%x..%x)\n",
1070 __func__, index, min_nasid, max_nasid);
1071 nasid = -1;
1072 }
1073
1074 if (nasid == lnasid) {
1075 li = i;
1076
1077 if (i != n-1)
1078 continue;
1079 }
1080
1081
1082 if (lnasid != -1 || (i == n-1 && nasid != -1)) {
1083 unsigned long addr1, addr2;
1084 int f, l;
1085
1086 if (lnasid == -1) {
1087 f = l = i;
1088 lnasid = nasid;
1089 } else {
1090 f = fi;
1091 l = li;
1092 }
1093 addr1 = (base << shift) + f * (1ULL << m_io);
1094 addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
1095 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
1096 id, fi, li, lnasid, addr1, addr2);
1097 if (max_io < l)
1098 max_io = l;
1099 }
1100 fi = li = i;
1101 lnasid = nasid;
1102 }
1103
1104map_exit:
1105 pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n",
1106 id, base, shift, m_io, max_io, max_pnode);
1107
1108 if (max_io >= 0 && !mapped)
1109 map_high(id, base, shift, m_io, max_io, map_uc);
1110}
1111
1112static __init void map_mmioh_high(int min_pnode, int max_pnode)
1113{
1114
1115 if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) {
1116 union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0;
1117 union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1;
1118
1119 mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0);
1120 if (unlikely(mmioh0.s.enable == 0))
1121 pr_info("UV: MMIOH0 disabled\n");
1122 else
1123 calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode,
1124 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1125 mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io);
1126
1127 mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1);
1128 if (unlikely(mmioh1.s.enable == 0))
1129 pr_info("UV: MMIOH1 disabled\n");
1130 else
1131 calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode,
1132 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1133 mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io);
1134 return;
1135 }
1136
1137 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) {
1138 union uvh_rh_gam_mmioh_overlay_config0_u mmioh0;
1139 union uvh_rh_gam_mmioh_overlay_config1_u mmioh1;
1140
1141 mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0);
1142 if (unlikely(mmioh0.s.enable == 0))
1143 pr_info("UV: MMIOH0 disabled\n");
1144 else {
1145 unsigned long base = uvxy_field(mmioh0, base, 0);
1146 int m_io = uvxy_field(mmioh0, m_io, 0);
1147 int n_io = uvxy_field(mmioh0, n_io, 0);
1148
1149 calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode,
1150 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1151 base, m_io, n_io);
1152 }
1153
1154 mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1);
1155 if (unlikely(mmioh1.s.enable == 0))
1156 pr_info("UV: MMIOH1 disabled\n");
1157 else {
1158 unsigned long base = uvxy_field(mmioh1, base, 0);
1159 int m_io = uvxy_field(mmioh1, m_io, 0);
1160 int n_io = uvxy_field(mmioh1, n_io, 0);
1161
1162 calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode,
1163 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1164 base, m_io, n_io);
1165 }
1166 return;
1167 }
1168
1169
1170 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) {
1171 union uvh_rh_gam_mmioh_overlay_config_u mmioh;
1172
1173 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG);
1174 if (unlikely(mmioh.s2.enable == 0))
1175 pr_info("UV: MMIOH disabled\n");
1176 else
1177 calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode,
1178 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT,
1179 mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io);
1180 return;
1181 }
1182}
1183
1184static __init void map_low_mmrs(void)
1185{
1186 if (UV_GLOBAL_MMR32_BASE)
1187 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
1188
1189 if (UV_LOCAL_MMR_BASE)
1190 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
1191}
1192
1193static __init void uv_rtc_init(void)
1194{
1195 long status;
1196 u64 ticks_per_sec;
1197
1198 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
1199
1200 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
1201 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
1202
1203
1204 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
1205 } else {
1206 sn_rtc_cycles_per_second = ticks_per_sec;
1207 }
1208}
1209
1210
1211static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1212{
1213 int domain, bus, rc;
1214
1215 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1216 return 0;
1217
1218 if ((command_bits & PCI_COMMAND_IO) == 0)
1219 return 0;
1220
1221 domain = pci_domain_nr(pdev->bus);
1222 bus = pdev->bus->number;
1223
1224 rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1225
1226 return rc;
1227}
1228
1229
1230
1231
1232
1233void uv_cpu_init(void)
1234{
1235
1236 if (smp_processor_id() == 0)
1237 return;
1238
1239 uv_hub_info->nr_online_cpus++;
1240}
1241
1242struct mn {
1243 unsigned char m_val;
1244 unsigned char n_val;
1245 unsigned char m_shift;
1246 unsigned char n_lshift;
1247};
1248
1249
1250static void get_mn(struct mn *mnp)
1251{
1252 memset(mnp, 0, sizeof(*mnp));
1253 mnp->n_val = uv_cpuid.n_skt;
1254 if (is_uv(UV4|UVY)) {
1255 mnp->m_val = 0;
1256 mnp->n_lshift = 0;
1257 } else if (is_uv3_hub()) {
1258 union uvyh_gr0_gam_gr_config_u m_gr_config;
1259
1260 mnp->m_val = uv_cpuid.m_skt;
1261 m_gr_config.v = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG);
1262 mnp->n_lshift = m_gr_config.s3.m_skt;
1263 } else if (is_uv2_hub()) {
1264 mnp->m_val = uv_cpuid.m_skt;
1265 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1266 }
1267 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1268}
1269
1270static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1271{
1272 struct mn mn;
1273
1274 get_mn(&mn);
1275 hi->gpa_mask = mn.m_val ?
1276 (1UL << (mn.m_val + mn.n_val)) - 1 :
1277 (1UL << uv_cpuid.gpa_shift) - 1;
1278
1279 hi->m_val = mn.m_val;
1280 hi->n_val = mn.n_val;
1281 hi->m_shift = mn.m_shift;
1282 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
1283 hi->hub_revision = uv_hub_info->hub_revision;
1284 hi->hub_type = uv_hub_info->hub_type;
1285 hi->pnode_mask = uv_cpuid.pnode_mask;
1286 hi->nasid_shift = uv_cpuid.nasid_shift;
1287 hi->min_pnode = _min_pnode;
1288 hi->min_socket = _min_socket;
1289 hi->pnode_to_socket = _pnode_to_socket;
1290 hi->socket_to_node = _socket_to_node;
1291 hi->socket_to_pnode = _socket_to_pnode;
1292 hi->gr_table_len = _gr_table_len;
1293 hi->gr_table = _gr_table;
1294
1295 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1296 hi->gnode_extra = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1297 if (mn.m_val)
1298 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1299
1300 if (uv_gp_table) {
1301 hi->global_mmr_base = uv_gp_table->mmr_base;
1302 hi->global_mmr_shift = uv_gp_table->mmr_shift;
1303 hi->global_gru_base = uv_gp_table->gru_base;
1304 hi->global_gru_shift = uv_gp_table->gru_shift;
1305 hi->gpa_shift = uv_gp_table->gpa_shift;
1306 hi->gpa_mask = (1UL << hi->gpa_shift) - 1;
1307 } else {
1308 hi->global_mmr_base =
1309 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) &
1310 ~UV_MMR_ENABLE;
1311 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1312 }
1313
1314 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1315
1316 hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1317
1318
1319 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1320 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1321 pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift);
1322 if (hi->global_gru_base)
1323 pr_info("UV: gru_base/shift:0x%lx/%ld\n",
1324 hi->global_gru_base, hi->global_gru_shift);
1325
1326 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1327}
1328
1329static void __init decode_gam_params(unsigned long ptr)
1330{
1331 uv_gp_table = (struct uv_gam_parameters *)ptr;
1332
1333 pr_info("UV: GAM Params...\n");
1334 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1335 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1336 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1337 uv_gp_table->gpa_shift);
1338}
1339
1340static void __init decode_gam_rng_tbl(unsigned long ptr)
1341{
1342 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1343 unsigned long lgre = 0;
1344 int index = 0;
1345 int sock_min = 999999, pnode_min = 99999;
1346 int sock_max = -1, pnode_max = -1;
1347
1348 uv_gre_table = gre;
1349 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1350 unsigned long size = ((unsigned long)(gre->limit - lgre)
1351 << UV_GAM_RANGE_SHFT);
1352 int order = 0;
1353 char suffix[] = " KMGTPE";
1354 int flag = ' ';
1355
1356 while (size > 9999 && order < sizeof(suffix)) {
1357 size /= 1024;
1358 order++;
1359 }
1360
1361
1362 if (gre->type == 1 || gre->type == 2)
1363 if (adj_blksize(lgre))
1364 flag = '*';
1365
1366 if (!index) {
1367 pr_info("UV: GAM Range Table...\n");
1368 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1369 }
1370 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n",
1371 index++,
1372 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1373 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1374 flag, size, suffix[order],
1375 gre->type, gre->nasid, gre->sockid, gre->pnode);
1376
1377
1378 lgre = gre->limit;
1379 if (sock_min > gre->sockid)
1380 sock_min = gre->sockid;
1381 if (sock_max < gre->sockid)
1382 sock_max = gre->sockid;
1383 if (pnode_min > gre->pnode)
1384 pnode_min = gre->pnode;
1385 if (pnode_max < gre->pnode)
1386 pnode_max = gre->pnode;
1387 }
1388 _min_socket = sock_min;
1389 _max_socket = sock_max;
1390 _min_pnode = pnode_min;
1391 _max_pnode = pnode_max;
1392 _gr_table_len = index;
1393
1394 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1395}
1396
1397
1398static int __init decode_uv_systab(void)
1399{
1400 struct uv_systab *st;
1401 int i;
1402
1403
1404 st = uv_systab;
1405
1406
1407 if (st && st->revision == UV_SYSTAB_VERSION_1)
1408 return 0;
1409
1410 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1411 int rev = st ? st->revision : 0;
1412
1413 pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n",
1414 rev, UV_SYSTAB_VERSION_UV4_LATEST);
1415 pr_err("UV: Does not support UV, switch to non-UV x86_64\n");
1416 uv_system_type = UV_NONE;
1417
1418 return -EINVAL;
1419 }
1420
1421 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1422 unsigned long ptr = st->entry[i].offset;
1423
1424 if (!ptr)
1425 continue;
1426
1427
1428 ptr += (unsigned long)st;
1429
1430 switch (st->entry[i].type) {
1431 case UV_SYSTAB_TYPE_GAM_PARAMS:
1432 decode_gam_params(ptr);
1433 break;
1434
1435 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1436 decode_gam_rng_tbl(ptr);
1437 break;
1438
1439 case UV_SYSTAB_TYPE_ARCH_TYPE:
1440
1441 break;
1442
1443 default:
1444 pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n",
1445 __func__, st->entry[i].type);
1446 break;
1447 }
1448 }
1449 return 0;
1450}
1451
1452
1453static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1454{
1455 unsigned long np;
1456 int i, uv_pb = 0;
1457
1458 if (UVH_NODE_PRESENT_TABLE) {
1459 pr_info("UV: NODE_PRESENT_DEPTH = %d\n",
1460 UVH_NODE_PRESENT_TABLE_DEPTH);
1461 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1462 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1463 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1464 uv_pb += hweight64(np);
1465 }
1466 }
1467 if (UVH_NODE_PRESENT_0) {
1468 np = uv_read_local_mmr(UVH_NODE_PRESENT_0);
1469 pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np);
1470 uv_pb += hweight64(np);
1471 }
1472 if (UVH_NODE_PRESENT_1) {
1473 np = uv_read_local_mmr(UVH_NODE_PRESENT_1);
1474 pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np);
1475 uv_pb += hweight64(np);
1476 }
1477 if (uv_possible_blades != uv_pb)
1478 uv_possible_blades = uv_pb;
1479
1480 pr_info("UV: number nodes/possible blades %d\n", uv_pb);
1481}
1482
1483static void __init build_socket_tables(void)
1484{
1485 struct uv_gam_range_entry *gre = uv_gre_table;
1486 int num, nump;
1487 int cpu, i, lnid;
1488 int minsock = _min_socket;
1489 int maxsock = _max_socket;
1490 int minpnode = _min_pnode;
1491 int maxpnode = _max_pnode;
1492 size_t bytes;
1493
1494 if (!gre) {
1495 if (is_uv2_hub() || is_uv3_hub()) {
1496 pr_info("UV: No UVsystab socket table, ignoring\n");
1497 return;
1498 }
1499 pr_err("UV: Error: UVsystab address translations not available!\n");
1500 BUG();
1501 }
1502
1503
1504 num = maxsock - minsock + 1;
1505 bytes = num * sizeof(_socket_to_node[0]);
1506 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1507 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1508
1509 nump = maxpnode - minpnode + 1;
1510 bytes = nump * sizeof(_pnode_to_socket[0]);
1511 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1512 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1513
1514 for (i = 0; i < num; i++)
1515 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1516
1517 for (i = 0; i < nump; i++)
1518 _pnode_to_socket[i] = SOCK_EMPTY;
1519
1520
1521 pr_info("UV: GAM Building socket/pnode conversion tables\n");
1522 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1523 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1524 continue;
1525 i = gre->sockid - minsock;
1526
1527 if (_socket_to_pnode[i] != SOCK_EMPTY)
1528 continue;
1529 _socket_to_pnode[i] = gre->pnode;
1530
1531 i = gre->pnode - minpnode;
1532 _pnode_to_socket[i] = gre->sockid;
1533
1534 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1535 gre->sockid, gre->type, gre->nasid,
1536 _socket_to_pnode[gre->sockid - minsock],
1537 _pnode_to_socket[gre->pnode - minpnode]);
1538 }
1539
1540
1541 lnid = NUMA_NO_NODE;
1542 for_each_present_cpu(cpu) {
1543 int nid = cpu_to_node(cpu);
1544 int apicid, sockid;
1545
1546 if (lnid == nid)
1547 continue;
1548 lnid = nid;
1549 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1550 sockid = apicid >> uv_cpuid.socketid_shift;
1551 _socket_to_node[sockid - minsock] = nid;
1552 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1553 sockid, apicid, nid);
1554 }
1555
1556
1557 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1558 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1559 BUG_ON(!_node_to_pnode);
1560
1561 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1562 unsigned short sockid;
1563
1564 for (sockid = minsock; sockid <= maxsock; sockid++) {
1565 if (lnid == _socket_to_node[sockid - minsock]) {
1566 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1567 break;
1568 }
1569 }
1570 if (sockid > maxsock) {
1571 pr_err("UV: socket for node %d not found!\n", lnid);
1572 BUG();
1573 }
1574 }
1575
1576
1577
1578
1579
1580 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1581 if (minsock == 0) {
1582 for (i = 0; i < num; i++)
1583 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1584 break;
1585 if (i >= num) {
1586 kfree(_socket_to_node);
1587 _socket_to_node = NULL;
1588 pr_info("UV: 1:1 socket_to_node table removed\n");
1589 }
1590 }
1591 if (minsock == minpnode) {
1592 for (i = 0; i < num; i++)
1593 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1594 _socket_to_pnode[i] != i + minpnode)
1595 break;
1596 if (i >= num) {
1597 kfree(_socket_to_pnode);
1598 _socket_to_pnode = NULL;
1599 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1600 }
1601 }
1602}
1603
1604
1605static void check_efi_reboot(void)
1606{
1607
1608 if (!efi_enabled(EFI_BOOT))
1609 reboot_type = BOOT_ACPI;
1610}
1611
1612
1613
1614
1615
1616static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data)
1617{
1618 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubbed, use /sys/firmware/sgi_uv/hub_type\n",
1619 current->comm);
1620 seq_printf(file, "0x%x\n", uv_hubbed_system);
1621 return 0;
1622}
1623
1624static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data)
1625{
1626 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubless, use /sys/firmware/sgi_uv/hubless\n",
1627 current->comm);
1628 seq_printf(file, "0x%x\n", uv_hubless_system);
1629 return 0;
1630}
1631
1632static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data)
1633{
1634 pr_notice_once("%s: using deprecated /proc/sgi_uv/archtype, use /sys/firmware/sgi_uv/archtype\n",
1635 current->comm);
1636 seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id);
1637 return 0;
1638}
1639
1640static __init void uv_setup_proc_files(int hubless)
1641{
1642 struct proc_dir_entry *pde;
1643
1644 pde = proc_mkdir(UV_PROC_NODE, NULL);
1645 proc_create_single("archtype", 0, pde, proc_archtype_show);
1646 if (hubless)
1647 proc_create_single("hubless", 0, pde, proc_hubless_show);
1648 else
1649 proc_create_single("hubbed", 0, pde, proc_hubbed_show);
1650}
1651
1652
1653static __init int uv_system_init_hubless(void)
1654{
1655 int rc;
1656
1657
1658 uv_nmi_setup_hubless();
1659
1660
1661 rc = uv_bios_init();
1662 if (rc < 0)
1663 return rc;
1664
1665
1666 rc = decode_uv_systab();
1667 if (rc < 0)
1668 return rc;
1669
1670
1671 set_block_size();
1672
1673
1674 if (rc >= 0)
1675 uv_setup_proc_files(1);
1676
1677 check_efi_reboot();
1678
1679 return rc;
1680}
1681
1682static void __init uv_system_init_hub(void)
1683{
1684 struct uv_hub_info_s hub_info = {0};
1685 int bytes, cpu, nodeid;
1686 unsigned short min_pnode = 9999, max_pnode = 0;
1687 char *hub = is_uv5_hub() ? "UV500" :
1688 is_uv4_hub() ? "UV400" :
1689 is_uv3_hub() ? "UV300" :
1690 is_uv2_hub() ? "UV2000/3000" : NULL;
1691
1692 if (!hub) {
1693 pr_err("UV: Unknown/unsupported UV hub\n");
1694 return;
1695 }
1696 pr_info("UV: Found %s hub\n", hub);
1697
1698 map_low_mmrs();
1699
1700
1701 uv_bios_init();
1702
1703
1704 if (decode_uv_systab() < 0) {
1705 pr_err("UV: Mangled UVsystab format\n");
1706 return;
1707 }
1708
1709 build_socket_tables();
1710 build_uv_gr_table();
1711 set_block_size();
1712 uv_init_hub_info(&hub_info);
1713 uv_possible_blades = num_possible_nodes();
1714 if (!_node_to_pnode)
1715 boot_init_possible_blades(&hub_info);
1716
1717
1718 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1719
1720 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1721 hub_info.coherency_domain_number = sn_coherency_id;
1722 uv_rtc_init();
1723
1724 bytes = sizeof(void *) * uv_num_possible_blades();
1725 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1726 BUG_ON(!__uv_hub_info_list);
1727
1728 bytes = sizeof(struct uv_hub_info_s);
1729 for_each_node(nodeid) {
1730 struct uv_hub_info_s *new_hub;
1731
1732 if (__uv_hub_info_list[nodeid]) {
1733 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1734 BUG();
1735 }
1736
1737
1738 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1739 BUG_ON(!new_hub);
1740 __uv_hub_info_list[nodeid] = new_hub;
1741 new_hub = uv_hub_info_list(nodeid);
1742 BUG_ON(!new_hub);
1743 *new_hub = hub_info;
1744
1745
1746 if (_node_to_pnode)
1747 new_hub->pnode = _node_to_pnode[nodeid];
1748 else
1749 new_hub->pnode = 0xffff;
1750
1751 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1752 new_hub->memory_nid = NUMA_NO_NODE;
1753 new_hub->nr_possible_cpus = 0;
1754 new_hub->nr_online_cpus = 0;
1755 }
1756
1757
1758 for_each_possible_cpu(cpu) {
1759 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1760 int numa_node_id;
1761 unsigned short pnode;
1762
1763 nodeid = cpu_to_node(cpu);
1764 numa_node_id = numa_cpu_node(cpu);
1765 pnode = uv_apicid_to_pnode(apicid);
1766
1767 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1768 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1769 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1770 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1771
1772
1773 if (nodeid != numa_node_id &&
1774 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1775 uv_hub_info_list(numa_node_id)->pnode = pnode;
1776 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1777 uv_cpu_hub_info(cpu)->pnode = pnode;
1778 }
1779
1780 for_each_node(nodeid) {
1781 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1782
1783
1784 if (pnode == 0xffff) {
1785 unsigned long paddr;
1786
1787 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1788 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1789 uv_hub_info_list(nodeid)->pnode = pnode;
1790 }
1791 min_pnode = min(pnode, min_pnode);
1792 max_pnode = max(pnode, max_pnode);
1793 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1794 nodeid,
1795 uv_hub_info_list(nodeid)->pnode,
1796 uv_hub_info_list(nodeid)->nr_possible_cpus);
1797 }
1798
1799 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1800 map_gru_high(max_pnode);
1801 map_mmr_high(max_pnode);
1802 map_mmioh_high(min_pnode, max_pnode);
1803
1804 uv_nmi_setup();
1805 uv_cpu_init();
1806 uv_setup_proc_files(0);
1807
1808
1809 pci_register_set_vga_state(uv_set_vga_state);
1810
1811 check_efi_reboot();
1812}
1813
1814
1815
1816
1817
1818void __init uv_system_init(void)
1819{
1820 if (likely(!is_uv_system() && !is_uv_hubless(1)))
1821 return;
1822
1823 if (is_uv_system())
1824 uv_system_init_hub();
1825 else
1826 uv_system_init_hubless();
1827}
1828
1829apic_driver(apic_x2apic_uv_x);
1830
