1
2
3
4
5#include <linux/slab.h>
6#include <linux/clk-provider.h>
7#include <linux/of_device.h>
8#include <linux/of_address.h>
9#include <linux/platform_device.h>
10
11#include <dt-bindings/clock/stratix10-clock.h>
12
13#include "stratix10-clk.h"
14
15static const struct clk_parent_data pll_mux[] = {
16 { .fw_name = "osc1",
17 .name = "osc1" },
18 { .fw_name = "cb-intosc-hs-div2-clk",
19 .name = "cb-intosc-hs-div2-clk" },
20 { .fw_name = "f2s-free-clk",
21 .name = "f2s-free-clk" },
22};
23
24static const struct clk_parent_data cntr_mux[] = {
25 { .fw_name = "main_pll",
26 .name = "main_pll", },
27 { .fw_name = "periph_pll",
28 .name = "periph_pll", },
29 { .fw_name = "osc1",
30 .name = "osc1", },
31 { .fw_name = "cb-intosc-hs-div2-clk",
32 .name = "cb-intosc-hs-div2-clk", },
33 { .fw_name = "f2s-free-clk",
34 .name = "f2s-free-clk", },
35};
36
37static const struct clk_parent_data boot_mux[] = {
38 { .fw_name = "osc1",
39 .name = "osc1" },
40 { .fw_name = "cb-intosc-hs-div2-clk",
41 .name = "cb-intosc-hs-div2-clk" },
42};
43
44static const struct clk_parent_data noc_free_mux[] = {
45 { .fw_name = "main_noc_base_clk",
46 .name = "main_noc_base_clk", },
47 { .fw_name = "peri_noc_base_clk",
48 .name = "peri_noc_base_clk", },
49 { .fw_name = "osc1",
50 .name = "osc1", },
51 { .fw_name = "cb-intosc-hs-div2-clk",
52 .name = "cb-intosc-hs-div2-clk", },
53 { .fw_name = "f2s-free-clk",
54 .name = "f2s-free-clk", },
55};
56
57static const struct clk_parent_data emaca_free_mux[] = {
58 { .fw_name = "peri_emaca_clk",
59 .name = "peri_emaca_clk", },
60 { .fw_name = "boot_clk",
61 .name = "boot_clk", },
62};
63
64static const struct clk_parent_data emacb_free_mux[] = {
65 { .fw_name = "peri_emacb_clk",
66 .name = "peri_emacb_clk", },
67 { .fw_name = "boot_clk",
68 .name = "boot_clk", },
69};
70
71static const struct clk_parent_data emac_ptp_free_mux[] = {
72 { .fw_name = "peri_emac_ptp_clk",
73 .name = "peri_emac_ptp_clk", },
74 { .fw_name = "boot_clk",
75 .name = "boot_clk", },
76};
77
78static const struct clk_parent_data gpio_db_free_mux[] = {
79 { .fw_name = "peri_gpio_db_clk",
80 .name = "peri_gpio_db_clk", },
81 { .fw_name = "boot_clk",
82 .name = "boot_clk", },
83};
84
85static const struct clk_parent_data sdmmc_free_mux[] = {
86 { .fw_name = "main_sdmmc_clk",
87 .name = "main_sdmmc_clk", },
88 { .fw_name = "boot_clk",
89 .name = "boot_clk", },
90};
91
92static const struct clk_parent_data s2f_usr1_free_mux[] = {
93 { .fw_name = "peri_s2f_usr1_clk",
94 .name = "peri_s2f_usr1_clk", },
95 { .fw_name = "boot_clk",
96 .name = "boot_clk", },
97};
98
99static const struct clk_parent_data psi_ref_free_mux[] = {
100 { .fw_name = "peri_psi_ref_clk",
101 .name = "peri_psi_ref_clk", },
102 { .fw_name = "boot_clk",
103 .name = "boot_clk", },
104};
105
106static const struct clk_parent_data mpu_mux[] = {
107 { .fw_name = "mpu_free_clk",
108 .name = "mpu_free_clk", },
109 { .fw_name = "boot_clk",
110 .name = "boot_clk", },
111};
112
113static const struct clk_parent_data s2f_usr0_mux[] = {
114 { .fw_name = "f2s-free-clk",
115 .name = "f2s-free-clk", },
116 { .fw_name = "boot_clk",
117 .name = "boot_clk", },
118};
119
120static const struct clk_parent_data emac_mux[] = {
121 { .fw_name = "emaca_free_clk",
122 .name = "emaca_free_clk", },
123 { .fw_name = "emacb_free_clk",
124 .name = "emacb_free_clk", },
125};
126
127static const struct clk_parent_data noc_mux[] = {
128 { .fw_name = "noc_free_clk",
129 .name = "noc_free_clk", },
130 { .fw_name = "boot_clk",
131 .name = "boot_clk", },
132};
133
134static const struct clk_parent_data mpu_free_mux[] = {
135 { .fw_name = "main_mpu_base_clk",
136 .name = "main_mpu_base_clk", },
137 { .fw_name = "peri_mpu_base_clk",
138 .name = "peri_mpu_base_clk", },
139 { .fw_name = "osc1",
140 .name = "osc1", },
141 { .fw_name = "cb-intosc-hs-div2-clk",
142 .name = "cb-intosc-hs-div2-clk", },
143 { .fw_name = "f2s-free-clk",
144 .name = "f2s-free-clk", },
145};
146
147static const struct clk_parent_data sdmmc_mux[] = {
148 { .fw_name = "sdmmc_free_clk",
149 .name = "sdmmc_free_clk", },
150 { .fw_name = "boot_clk",
151 .name = "boot_clk", },
152};
153
154static const struct clk_parent_data s2f_user1_mux[] = {
155 { .fw_name = "s2f_user1_free_clk",
156 .name = "s2f_user1_free_clk", },
157 { .fw_name = "boot_clk",
158 .name = "boot_clk", },
159};
160
161static const struct clk_parent_data psi_mux[] = {
162 { .fw_name = "psi_ref_free_clk",
163 .name = "psi_ref_free_clk", },
164 { .fw_name = "boot_clk",
165 .name = "boot_clk", },
166};
167
168static const struct clk_parent_data gpio_db_mux[] = {
169 { .fw_name = "gpio_db_free_clk",
170 .name = "gpio_db_free_clk", },
171 { .fw_name = "boot_clk",
172 .name = "boot_clk", },
173};
174
175static const struct clk_parent_data emac_ptp_mux[] = {
176 { .fw_name = "emac_ptp_free_clk",
177 .name = "emac_ptp_free_clk", },
178 { .fw_name = "boot_clk",
179 .name = "boot_clk", },
180};
181
182
183static const struct stratix10_pll_clock s10_pll_clks[] = {
184 { STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
185 0x0},
186 { STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
187 0, 0x74},
188 { STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
189 0, 0xe4},
190};
191
192static const struct stratix10_perip_c_clock s10_main_perip_c_clks[] = {
193 { STRATIX10_MAIN_MPU_BASE_CLK, "main_mpu_base_clk", "main_pll", NULL, 1, 0, 0x84},
194 { STRATIX10_MAIN_NOC_BASE_CLK, "main_noc_base_clk", "main_pll", NULL, 1, 0, 0x88},
195 { STRATIX10_PERI_MPU_BASE_CLK, "peri_mpu_base_clk", "periph_pll", NULL, 1, 0,
196 0xF4},
197 { STRATIX10_PERI_NOC_BASE_CLK, "peri_noc_base_clk", "periph_pll", NULL, 1, 0,
198 0xF8},
199};
200
201static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
202 { STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
203 0, 0x48, 0, 0, 0},
204 { STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
205 0, 0x4C, 0, 0x3C, 1},
206 { STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0,
207 0x50, 0, 0, 0},
208 { STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0,
209 0x54, 0, 0, 0},
210 { STRATIX10_MAIN_EMAC_PTP_CLK, "main_emac_ptp_clk", "main_noc_base_clk", NULL, 1, 0,
211 0x58, 0, 0, 0},
212 { STRATIX10_MAIN_GPIO_DB_CLK, "main_gpio_db_clk", "main_noc_base_clk", NULL, 1, 0,
213 0x5C, 0, 0, 0},
214 { STRATIX10_MAIN_SDMMC_CLK, "main_sdmmc_clk", "main_noc_base_clk", NULL, 1, 0,
215 0x60, 0, 0, 0},
216 { STRATIX10_MAIN_S2F_USR0_CLK, "main_s2f_usr0_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
217 0, 0x64, 0, 0, 0},
218 { STRATIX10_MAIN_S2F_USR1_CLK, "main_s2f_usr1_clk", "main_noc_base_clk", NULL, 1, 0,
219 0x68, 0, 0, 0},
220 { STRATIX10_MAIN_PSI_REF_CLK, "main_psi_ref_clk", "main_noc_base_clk", NULL, 1, 0,
221 0x6C, 0, 0, 0},
222 { STRATIX10_PERI_EMACA_CLK, "peri_emaca_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
223 0, 0xBC, 0, 0, 0},
224 { STRATIX10_PERI_EMACB_CLK, "peri_emacb_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
225 0, 0xC0, 0, 0, 0},
226 { STRATIX10_PERI_EMAC_PTP_CLK, "peri_emac_ptp_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
227 0, 0xC4, 0, 0, 0},
228 { STRATIX10_PERI_GPIO_DB_CLK, "peri_gpio_db_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
229 0, 0xC8, 0, 0, 0},
230 { STRATIX10_PERI_SDMMC_CLK, "peri_sdmmc_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
231 0, 0xCC, 0, 0, 0},
232 { STRATIX10_PERI_S2F_USR0_CLK, "peri_s2f_usr0_clk", "peri_noc_base_clk", NULL, 1, 0,
233 0xD0, 0, 0, 0},
234 { STRATIX10_PERI_S2F_USR1_CLK, "peri_s2f_usr1_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
235 0, 0xD4, 0, 0, 0},
236 { STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0,
237 0xD8, 0, 0, 0},
238 { STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
239 0, 4, 0x3C, 1},
240 { STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
241 0, 0, 2, 0xB0, 0},
242 { STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
243 0, 0, 2, 0xB0, 1},
244 { STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
245 ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 2, 0xB0, 2},
246 { STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
247 ARRAY_SIZE(gpio_db_free_mux), 0, 0, 0, 0xB0, 3},
248 { STRATIX10_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
249 ARRAY_SIZE(sdmmc_free_mux), 0, 0, 0, 0xB0, 4},
250 { STRATIX10_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
251 ARRAY_SIZE(s2f_usr1_free_mux), 0, 0, 0, 0xB0, 5},
252 { STRATIX10_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
253 ARRAY_SIZE(psi_ref_free_mux), 0, 0, 0, 0xB0, 6},
254};
255
256static const struct stratix10_gate_clock s10_gate_clks[] = {
257 { STRATIX10_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x30,
258 0, 0, 0, 0, 0x3C, 0, 0},
259 { STRATIX10_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x30,
260 0, 0, 0, 0, 0, 0, 4},
261 { STRATIX10_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x30,
262 0, 0, 0, 0, 0, 0, 2},
263 { STRATIX10_L4_MAIN_CLK, "l4_main_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
264 1, 0x70, 0, 2, 0x3C, 1, 0},
265 { STRATIX10_L4_MP_CLK, "l4_mp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
266 2, 0x70, 8, 2, 0x3C, 1, 0},
267 { STRATIX10_L4_SP_CLK, "l4_sp_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), CLK_IS_CRITICAL, 0x30,
268 3, 0x70, 16, 2, 0x3C, 1, 0},
269 { STRATIX10_CS_AT_CLK, "cs_at_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
270 4, 0x70, 24, 2, 0x3C, 1, 0},
271 { STRATIX10_CS_TRACE_CLK, "cs_trace_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
272 4, 0x70, 26, 2, 0x3C, 1, 0},
273 { STRATIX10_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x30,
274 4, 0x70, 28, 1, 0, 0, 0},
275 { STRATIX10_CS_TIMER_CLK, "cs_timer_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0, 0x30,
276 5, 0, 0, 0, 0x3C, 1, 0},
277 { STRATIX10_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x30,
278 6, 0, 0, 0, 0, 0, 0},
279 { STRATIX10_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
280 0, 0, 0, 0, 0xDC, 26, 0},
281 { STRATIX10_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
282 1, 0, 0, 0, 0xDC, 27, 0},
283 { STRATIX10_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4,
284 2, 0, 0, 0, 0xDC, 28, 0},
285 { STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", NULL, emac_ptp_mux, ARRAY_SIZE(emac_ptp_mux), 0, 0xA4,
286 3, 0, 0, 0, 0xB0, 2, 0},
287 { STRATIX10_GPIO_DB_CLK, "gpio_db_clk", NULL, gpio_db_mux, ARRAY_SIZE(gpio_db_mux), 0, 0xA4,
288 4, 0xE0, 0, 16, 0xB0, 3, 0},
289 { STRATIX10_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0xA4,
290 5, 0, 0, 0, 0xB0, 4, 4},
291 { STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0xA4,
292 6, 0, 0, 0, 0xB0, 5, 0},
293 { STRATIX10_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0xA4,
294 7, 0, 0, 0, 0xB0, 6, 0},
295 { STRATIX10_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
296 8, 0, 0, 0, 0, 0, 0},
297 { STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
298 9, 0, 0, 0, 0, 0, 0},
299 { STRATIX10_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0xA4,
300 10, 0, 0, 0, 0, 0, 0},
301 { STRATIX10_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
302 10, 0, 0, 0, 0, 0, 4},
303 { STRATIX10_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0xA4,
304 10, 0, 0, 0, 0, 0, 4},
305};
306
307static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
308 int nums, struct stratix10_clock_data *data)
309{
310 struct clk_hw *hw_clk;
311 void __iomem *base = data->base;
312 int i;
313
314 for (i = 0; i < nums; i++) {
315 hw_clk = s10_register_periph(&clks[i], base);
316 if (IS_ERR(hw_clk)) {
317 pr_err("%s: failed to register clock %s\n",
318 __func__, clks[i].name);
319 continue;
320 }
321 data->clk_data.hws[clks[i].id] = hw_clk;
322 }
323 return 0;
324}
325
326static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
327 int nums, struct stratix10_clock_data *data)
328{
329 struct clk_hw *hw_clk;
330 void __iomem *base = data->base;
331 int i;
332
333 for (i = 0; i < nums; i++) {
334 hw_clk = s10_register_cnt_periph(&clks[i], base);
335 if (IS_ERR(hw_clk)) {
336 pr_err("%s: failed to register clock %s\n",
337 __func__, clks[i].name);
338 continue;
339 }
340 data->clk_data.hws[clks[i].id] = hw_clk;
341 }
342
343 return 0;
344}
345
346static int s10_clk_register_gate(const struct stratix10_gate_clock *clks,
347 int nums, struct stratix10_clock_data *data)
348{
349 struct clk_hw *hw_clk;
350 void __iomem *base = data->base;
351 int i;
352
353 for (i = 0; i < nums; i++) {
354 hw_clk = s10_register_gate(&clks[i], base);
355 if (IS_ERR(hw_clk)) {
356 pr_err("%s: failed to register clock %s\n",
357 __func__, clks[i].name);
358 continue;
359 }
360 data->clk_data.hws[clks[i].id] = hw_clk;
361 }
362
363 return 0;
364}
365
366static int s10_clk_register_pll(const struct stratix10_pll_clock *clks,
367 int nums, struct stratix10_clock_data *data)
368{
369 struct clk_hw *hw_clk;
370 void __iomem *base = data->base;
371 int i;
372
373 for (i = 0; i < nums; i++) {
374 hw_clk = s10_register_pll(&clks[i], base);
375 if (IS_ERR(hw_clk)) {
376 pr_err("%s: failed to register clock %s\n",
377 __func__, clks[i].name);
378 continue;
379 }
380 data->clk_data.hws[clks[i].id] = hw_clk;
381 }
382
383 return 0;
384}
385
386static int s10_clkmgr_init(struct platform_device *pdev)
387{
388 struct device_node *np = pdev->dev.of_node;
389 struct device *dev = &pdev->dev;
390 struct stratix10_clock_data *clk_data;
391 struct resource *res;
392 void __iomem *base;
393 int i, num_clks;
394
395 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
396 base = devm_ioremap_resource(dev, res);
397 if (IS_ERR(base)) {
398 pr_err("%s: failed to map clock registers\n", __func__);
399 return PTR_ERR(base);
400 }
401
402 num_clks = STRATIX10_NUM_CLKS;
403 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
404 num_clks), GFP_KERNEL);
405 if (!clk_data)
406 return -ENOMEM;
407
408 for (i = 0; i < num_clks; i++)
409 clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
410
411 clk_data->base = base;
412 clk_data->clk_data.num = num_clks;
413
414 s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data);
415
416 s10_clk_register_c_perip(s10_main_perip_c_clks,
417 ARRAY_SIZE(s10_main_perip_c_clks), clk_data);
418
419 s10_clk_register_cnt_perip(s10_main_perip_cnt_clks,
420 ARRAY_SIZE(s10_main_perip_cnt_clks),
421 clk_data);
422
423 s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks),
424 clk_data);
425
426 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
427 return 0;
428}
429
430static int s10_clkmgr_probe(struct platform_device *pdev)
431{
432 return s10_clkmgr_init(pdev);
433}
434
435static const struct of_device_id stratix10_clkmgr_match_table[] = {
436 { .compatible = "intel,stratix10-clkmgr",
437 .data = s10_clkmgr_init },
438 { }
439};
440
441static struct platform_driver stratix10_clkmgr_driver = {
442 .probe = s10_clkmgr_probe,
443 .driver = {
444 .name = "stratix10-clkmgr",
445 .suppress_bind_attrs = true,
446 .of_match_table = stratix10_clkmgr_match_table,
447 },
448};
449
450static int __init s10_clk_init(void)
451{
452 return platform_driver_register(&stratix10_clkmgr_driver);
453}
454core_initcall(s10_clk_init);
455
