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41#include <linux/slab.h>
42#include "pm8001_sas.h"
43#include "pm8001_chips.h"
44#include "pm80xx_hwi.h"
45
46static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
47module_param(logging_level, ulong, 0644);
48MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
49
50static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
51module_param(link_rate, ulong, 0644);
52MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
53 " 1: Link rate 1.5G\n"
54 " 2: Link rate 3.0G\n"
55 " 4: Link rate 6.0G\n"
56 " 8: Link rate 12.0G\n");
57
58static struct scsi_transport_template *pm8001_stt;
59static int pm8001_init_ccb_tag(struct pm8001_hba_info *, struct Scsi_Host *, struct pci_dev *);
60
61
62
63
64
65static const struct pm8001_chip_info pm8001_chips[] = {
66 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
67 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
68 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
69 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
70 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
71 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
72 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
73 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
74 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
75 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
76 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
77};
78static int pm8001_id;
79
80LIST_HEAD(hba_list);
81
82struct workqueue_struct *pm8001_wq;
83
84
85
86
87static struct scsi_host_template pm8001_sht = {
88 .module = THIS_MODULE,
89 .name = DRV_NAME,
90 .queuecommand = sas_queuecommand,
91 .dma_need_drain = ata_scsi_dma_need_drain,
92 .target_alloc = sas_target_alloc,
93 .slave_configure = sas_slave_configure,
94 .scan_finished = pm8001_scan_finished,
95 .scan_start = pm8001_scan_start,
96 .change_queue_depth = sas_change_queue_depth,
97 .bios_param = sas_bios_param,
98 .can_queue = 1,
99 .this_id = -1,
100 .sg_tablesize = PM8001_MAX_DMA_SG,
101 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
102 .eh_device_reset_handler = sas_eh_device_reset_handler,
103 .eh_target_reset_handler = sas_eh_target_reset_handler,
104 .slave_alloc = sas_slave_alloc,
105 .target_destroy = sas_target_destroy,
106 .ioctl = sas_ioctl,
107#ifdef CONFIG_COMPAT
108 .compat_ioctl = sas_ioctl,
109#endif
110 .shost_attrs = pm8001_host_attrs,
111 .track_queue_depth = 1,
112};
113
114
115
116
117static struct sas_domain_function_template pm8001_transport_ops = {
118 .lldd_dev_found = pm8001_dev_found,
119 .lldd_dev_gone = pm8001_dev_gone,
120
121 .lldd_execute_task = pm8001_queue_command,
122 .lldd_control_phy = pm8001_phy_control,
123
124 .lldd_abort_task = pm8001_abort_task,
125 .lldd_abort_task_set = pm8001_abort_task_set,
126 .lldd_clear_aca = pm8001_clear_aca,
127 .lldd_clear_task_set = pm8001_clear_task_set,
128 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
129 .lldd_lu_reset = pm8001_lu_reset,
130 .lldd_query_task = pm8001_query_task,
131};
132
133
134
135
136
137
138static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
139{
140 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
141 struct asd_sas_phy *sas_phy = &phy->sas_phy;
142 phy->phy_state = PHY_LINK_DISABLE;
143 phy->pm8001_ha = pm8001_ha;
144 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
145 sas_phy->class = SAS;
146 sas_phy->iproto = SAS_PROTOCOL_ALL;
147 sas_phy->tproto = 0;
148 sas_phy->type = PHY_TYPE_PHYSICAL;
149 sas_phy->role = PHY_ROLE_INITIATOR;
150 sas_phy->oob_mode = OOB_NOT_CONNECTED;
151 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
152 sas_phy->id = phy_id;
153 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
154 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
155 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
156 sas_phy->lldd_phy = phy;
157}
158
159
160
161
162
163static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
164{
165 int i;
166
167 if (!pm8001_ha)
168 return;
169
170 for (i = 0; i < USI_MAX_MEMCNT; i++) {
171 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
172 dma_free_coherent(&pm8001_ha->pdev->dev,
173 (pm8001_ha->memoryMap.region[i].total_len +
174 pm8001_ha->memoryMap.region[i].alignment),
175 pm8001_ha->memoryMap.region[i].virt_ptr,
176 pm8001_ha->memoryMap.region[i].phys_addr);
177 }
178 }
179 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
180 flush_workqueue(pm8001_wq);
181 kfree(pm8001_ha->tags);
182 kfree(pm8001_ha);
183}
184
185#ifdef PM8001_USE_TASKLET
186
187
188
189
190
191
192static void pm8001_tasklet(unsigned long opaque)
193{
194 struct pm8001_hba_info *pm8001_ha;
195 struct isr_param *irq_vector;
196
197 irq_vector = (struct isr_param *)opaque;
198 pm8001_ha = irq_vector->drv_inst;
199 if (unlikely(!pm8001_ha))
200 BUG_ON(1);
201 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
202}
203#endif
204
205
206
207
208
209
210
211
212
213static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
214{
215 struct isr_param *irq_vector;
216 struct pm8001_hba_info *pm8001_ha;
217 irqreturn_t ret = IRQ_HANDLED;
218 irq_vector = (struct isr_param *)opaque;
219 pm8001_ha = irq_vector->drv_inst;
220
221 if (unlikely(!pm8001_ha))
222 return IRQ_NONE;
223 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
224 return IRQ_NONE;
225#ifdef PM8001_USE_TASKLET
226 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
227#else
228 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
229#endif
230 return ret;
231}
232
233
234
235
236
237
238
239static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
240{
241 struct pm8001_hba_info *pm8001_ha;
242 irqreturn_t ret = IRQ_HANDLED;
243 struct sas_ha_struct *sha = dev_id;
244 pm8001_ha = sha->lldd_ha;
245 if (unlikely(!pm8001_ha))
246 return IRQ_NONE;
247 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
248 return IRQ_NONE;
249
250#ifdef PM8001_USE_TASKLET
251 tasklet_schedule(&pm8001_ha->tasklet[0]);
252#else
253 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
254#endif
255 return ret;
256}
257
258static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
259static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
260
261
262
263
264
265
266static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
267 const struct pci_device_id *ent)
268{
269 int i, count = 0, rc = 0;
270 u32 ci_offset, ib_offset, ob_offset, pi_offset;
271 struct inbound_queue_table *ibq;
272 struct outbound_queue_table *obq;
273
274 spin_lock_init(&pm8001_ha->lock);
275 spin_lock_init(&pm8001_ha->bitmap_lock);
276 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
277 pm8001_ha->chip->n_phy);
278
279
280 rc = pm8001_setup_irq(pm8001_ha);
281 if (rc) {
282 pm8001_dbg(pm8001_ha, FAIL,
283 "pm8001_setup_irq failed [ret: %d]\n", rc);
284 goto err_out_shost;
285 }
286
287 rc = pm8001_request_irq(pm8001_ha);
288 if (rc)
289 goto err_out_shost;
290
291 count = pm8001_ha->max_q_num;
292
293 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE;
294 ci_offset = pm8001_ha->ci_offset = ib_offset + count;
295 ob_offset = pm8001_ha->ob_offset = ci_offset + count;
296 pi_offset = pm8001_ha->pi_offset = ob_offset + count;
297 pm8001_ha->max_memcnt = pi_offset + count;
298
299 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
300 pm8001_phy_init(pm8001_ha, i);
301 pm8001_ha->port[i].wide_port_phymap = 0;
302 pm8001_ha->port[i].port_attached = 0;
303 pm8001_ha->port[i].port_state = 0;
304 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
305 }
306
307
308 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
309 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
310 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
311 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
312
313
314 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
315 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
316 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
317 pm8001_ha->memoryMap.region[IOP].alignment = 32;
318
319 for (i = 0; i < count; i++) {
320 ibq = &pm8001_ha->inbnd_q_tbl[i];
321 spin_lock_init(&ibq->iq_lock);
322
323 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
324 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
325 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
326 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
327
328 if ((ent->driver_data) != chip_8001) {
329
330 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
331 PM8001_MPI_QUEUE;
332 pm8001_ha->memoryMap.region[ib_offset+i].element_size
333 = 128;
334 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
335 PM8001_MPI_QUEUE * 128;
336 pm8001_ha->memoryMap.region[ib_offset+i].alignment
337 = 128;
338 } else {
339 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
340 PM8001_MPI_QUEUE;
341 pm8001_ha->memoryMap.region[ib_offset+i].element_size
342 = 64;
343 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
344 PM8001_MPI_QUEUE * 64;
345 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
346 }
347 }
348
349 for (i = 0; i < count; i++) {
350 obq = &pm8001_ha->outbnd_q_tbl[i];
351 spin_lock_init(&obq->oq_lock);
352
353 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
354 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
355 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
356 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
357
358 if (ent->driver_data != chip_8001) {
359
360 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
361 PM8001_MPI_QUEUE;
362 pm8001_ha->memoryMap.region[ob_offset+i].element_size
363 = 128;
364 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
365 PM8001_MPI_QUEUE * 128;
366 pm8001_ha->memoryMap.region[ob_offset+i].alignment
367 = 128;
368 } else {
369
370 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
371 PM8001_MPI_QUEUE;
372 pm8001_ha->memoryMap.region[ob_offset+i].element_size
373 = 64;
374 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
375 PM8001_MPI_QUEUE * 64;
376 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
377 }
378
379 }
380
381 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
382 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
383 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
384
385
386 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
387
388 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
389 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
390 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
391 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
392 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
393 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
394
395 if (pm8001_mem_alloc(pm8001_ha->pdev,
396 ®ion->virt_ptr,
397 ®ion->phys_addr,
398 ®ion->phys_addr_hi,
399 ®ion->phys_addr_lo,
400 region->total_len,
401 region->alignment) != 0) {
402 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
403 goto err_out;
404 }
405 }
406
407
408 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
409 * sizeof(struct pm8001_device), GFP_KERNEL);
410 if (!pm8001_ha->devices) {
411 rc = -ENOMEM;
412 goto err_out_nodev;
413 }
414 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
415 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
416 pm8001_ha->devices[i].id = i;
417 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
418 atomic_set(&pm8001_ha->devices[i].running_req, 0);
419 }
420 pm8001_ha->flags = PM8001F_INIT_TIME;
421
422 pm8001_tag_init(pm8001_ha);
423 return 0;
424
425err_out_shost:
426 scsi_remove_host(pm8001_ha->shost);
427err_out_nodev:
428 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
429 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
430 dma_free_coherent(&pm8001_ha->pdev->dev,
431 (pm8001_ha->memoryMap.region[i].total_len +
432 pm8001_ha->memoryMap.region[i].alignment),
433 pm8001_ha->memoryMap.region[i].virt_ptr,
434 pm8001_ha->memoryMap.region[i].phys_addr);
435 }
436 }
437err_out:
438 return 1;
439}
440
441
442
443
444
445
446static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
447{
448 u32 bar;
449 u32 logicalBar = 0;
450 struct pci_dev *pdev;
451
452 pdev = pm8001_ha->pdev;
453
454 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
455
456
457
458
459
460
461
462
463 if ((bar == 1) || (bar == 3))
464 continue;
465 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
466 pm8001_ha->io_mem[logicalBar].membase =
467 pci_resource_start(pdev, bar);
468 pm8001_ha->io_mem[logicalBar].memsize =
469 pci_resource_len(pdev, bar);
470 pm8001_ha->io_mem[logicalBar].memvirtaddr =
471 ioremap(pm8001_ha->io_mem[logicalBar].membase,
472 pm8001_ha->io_mem[logicalBar].memsize);
473 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
474 pm8001_dbg(pm8001_ha, INIT,
475 "Failed to ioremap bar %d, logicalBar %d",
476 bar, logicalBar);
477 return -ENOMEM;
478 }
479 pm8001_dbg(pm8001_ha, INIT,
480 "base addr %llx virt_addr=%llx len=%d\n",
481 (u64)pm8001_ha->io_mem[logicalBar].membase,
482 (u64)(unsigned long)
483 pm8001_ha->io_mem[logicalBar].memvirtaddr,
484 pm8001_ha->io_mem[logicalBar].memsize);
485 } else {
486 pm8001_ha->io_mem[logicalBar].membase = 0;
487 pm8001_ha->io_mem[logicalBar].memsize = 0;
488 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
489 }
490 logicalBar++;
491 }
492 return 0;
493}
494
495
496
497
498
499
500
501static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
502 const struct pci_device_id *ent,
503 struct Scsi_Host *shost)
504
505{
506 struct pm8001_hba_info *pm8001_ha;
507 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
508 int j;
509
510 pm8001_ha = sha->lldd_ha;
511 if (!pm8001_ha)
512 return NULL;
513
514 pm8001_ha->pdev = pdev;
515 pm8001_ha->dev = &pdev->dev;
516 pm8001_ha->chip_id = ent->driver_data;
517 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
518 pm8001_ha->irq = pdev->irq;
519 pm8001_ha->sas = sha;
520 pm8001_ha->shost = shost;
521 pm8001_ha->id = pm8001_id++;
522 pm8001_ha->logging_level = logging_level;
523 pm8001_ha->non_fatal_count = 0;
524 if (link_rate >= 1 && link_rate <= 15)
525 pm8001_ha->link_rate = (link_rate << 8);
526 else {
527 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
528 LINKRATE_60 | LINKRATE_120;
529 pm8001_dbg(pm8001_ha, FAIL,
530 "Setting link rate to default value\n");
531 }
532 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
533
534 if (pm8001_ha->chip_id != chip_8001)
535 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
536 else
537 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
538
539#ifdef PM8001_USE_TASKLET
540
541 if ((!pdev->msix_cap || !pci_msi_enabled())
542 || (pm8001_ha->chip_id == chip_8001))
543 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
544 (unsigned long)&(pm8001_ha->irq_vector[0]));
545 else
546 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
547 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
548 (unsigned long)&(pm8001_ha->irq_vector[j]));
549#endif
550 if (pm8001_ioremap(pm8001_ha))
551 goto failed_pci_alloc;
552 if (!pm8001_alloc(pm8001_ha, ent))
553 return pm8001_ha;
554failed_pci_alloc:
555 pm8001_free(pm8001_ha);
556 return NULL;
557}
558
559
560
561
562
563static int pci_go_44(struct pci_dev *pdev)
564{
565 int rc;
566
567 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
568 if (rc) {
569 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
570 if (rc)
571 dev_printk(KERN_ERR, &pdev->dev,
572 "32-bit DMA enable failed\n");
573 }
574 return rc;
575}
576
577
578
579
580
581
582static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
583 const struct pm8001_chip_info *chip_info)
584{
585 int phy_nr, port_nr;
586 struct asd_sas_phy **arr_phy;
587 struct asd_sas_port **arr_port;
588 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
589
590 phy_nr = chip_info->n_phy;
591 port_nr = phy_nr;
592 memset(sha, 0x00, sizeof(*sha));
593 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
594 if (!arr_phy)
595 goto exit;
596 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
597 if (!arr_port)
598 goto exit_free2;
599
600 sha->sas_phy = arr_phy;
601 sha->sas_port = arr_port;
602 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
603 if (!sha->lldd_ha)
604 goto exit_free1;
605
606 shost->transportt = pm8001_stt;
607 shost->max_id = PM8001_MAX_DEVICES;
608 shost->max_lun = 8;
609 shost->max_channel = 0;
610 shost->unique_id = pm8001_id;
611 shost->max_cmd_len = 16;
612 shost->can_queue = PM8001_CAN_QUEUE;
613 shost->cmd_per_lun = 32;
614 return 0;
615exit_free1:
616 kfree(arr_port);
617exit_free2:
618 kfree(arr_phy);
619exit:
620 return -1;
621}
622
623
624
625
626
627
628static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
629 const struct pm8001_chip_info *chip_info)
630{
631 int i = 0;
632 struct pm8001_hba_info *pm8001_ha;
633 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
634
635 pm8001_ha = sha->lldd_ha;
636 for (i = 0; i < chip_info->n_phy; i++) {
637 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
638 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
639 sha->sas_phy[i]->sas_addr =
640 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
641 }
642 sha->sas_ha_name = DRV_NAME;
643 sha->dev = pm8001_ha->dev;
644 sha->strict_wide_ports = 1;
645 sha->lldd_module = THIS_MODULE;
646 sha->sas_addr = &pm8001_ha->sas_addr[0];
647 sha->num_phys = chip_info->n_phy;
648 sha->core.shost = shost;
649}
650
651
652
653
654
655
656
657
658static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
659{
660 u8 i, j;
661 u8 sas_add[8];
662#ifdef PM8001_READ_VPD
663
664
665
666
667 DECLARE_COMPLETION_ONSTACK(completion);
668 struct pm8001_ioctl_payload payload;
669 u16 deviceid;
670 int rc;
671
672 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
673 pm8001_ha->nvmd_completion = &completion;
674
675 if (pm8001_ha->chip_id == chip_8001) {
676 if (deviceid == 0x8081 || deviceid == 0x0042) {
677 payload.minor_function = 4;
678 payload.rd_length = 4096;
679 } else {
680 payload.minor_function = 0;
681 payload.rd_length = 128;
682 }
683 } else if ((pm8001_ha->chip_id == chip_8070 ||
684 pm8001_ha->chip_id == chip_8072) &&
685 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
686 payload.minor_function = 4;
687 payload.rd_length = 4096;
688 } else {
689 payload.minor_function = 1;
690 payload.rd_length = 4096;
691 }
692 payload.offset = 0;
693 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
694 if (!payload.func_specific) {
695 pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
696 return;
697 }
698 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
699 if (rc) {
700 kfree(payload.func_specific);
701 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
702 return;
703 }
704 wait_for_completion(&completion);
705
706 for (i = 0, j = 0; i <= 7; i++, j++) {
707 if (pm8001_ha->chip_id == chip_8001) {
708 if (deviceid == 0x8081)
709 pm8001_ha->sas_addr[j] =
710 payload.func_specific[0x704 + i];
711 else if (deviceid == 0x0042)
712 pm8001_ha->sas_addr[j] =
713 payload.func_specific[0x010 + i];
714 } else if ((pm8001_ha->chip_id == chip_8070 ||
715 pm8001_ha->chip_id == chip_8072) &&
716 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
717 pm8001_ha->sas_addr[j] =
718 payload.func_specific[0x010 + i];
719 } else
720 pm8001_ha->sas_addr[j] =
721 payload.func_specific[0x804 + i];
722 }
723 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
724 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
725 if (i && ((i % 4) == 0))
726 sas_add[7] = sas_add[7] + 4;
727 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
728 sas_add, SAS_ADDR_SIZE);
729 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
730 pm8001_ha->phy[i].dev_sas_addr);
731 }
732 kfree(payload.func_specific);
733#else
734 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
735 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
736 pm8001_ha->phy[i].dev_sas_addr =
737 cpu_to_be64((u64)
738 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
739 }
740 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
741 SAS_ADDR_SIZE);
742#endif
743}
744
745
746
747
748
749static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
750{
751
752#ifdef PM8001_READ_VPD
753
754 DECLARE_COMPLETION_ONSTACK(completion);
755 struct pm8001_ioctl_payload payload;
756 int rc;
757
758 pm8001_ha->nvmd_completion = &completion;
759
760 payload.minor_function = 6;
761 payload.offset = 0;
762 payload.rd_length = 4096;
763 payload.func_specific = kzalloc(4096, GFP_KERNEL);
764 if (!payload.func_specific)
765 return -ENOMEM;
766
767 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
768 if (rc) {
769 kfree(payload.func_specific);
770 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
771 return -ENOMEM;
772 }
773 wait_for_completion(&completion);
774 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
775 kfree(payload.func_specific);
776#endif
777 return 0;
778}
779
780struct pm8001_mpi3_phy_pg_trx_config {
781 u32 LaneLosCfg;
782 u32 LanePgaCfg1;
783 u32 LanePisoCfg1;
784 u32 LanePisoCfg2;
785 u32 LanePisoCfg3;
786 u32 LanePisoCfg4;
787 u32 LanePisoCfg5;
788 u32 LanePisoCfg6;
789 u32 LaneBctCtrl;
790};
791
792
793
794
795
796
797static
798void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
799 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
800{
801 phycfg->LaneLosCfg = 0x00000132;
802 phycfg->LanePgaCfg1 = 0x00203949;
803 phycfg->LanePisoCfg1 = 0x000000FF;
804 phycfg->LanePisoCfg2 = 0xFF000001;
805 phycfg->LanePisoCfg3 = 0xE7011300;
806 phycfg->LanePisoCfg4 = 0x631C40C0;
807 phycfg->LanePisoCfg5 = 0xF8102036;
808 phycfg->LanePisoCfg6 = 0xF74A1000;
809 phycfg->LaneBctCtrl = 0x00FB33F8;
810}
811
812
813
814
815
816
817static
818void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
819 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
820{
821 phycfg->LaneLosCfg = 0x00000132;
822 phycfg->LanePgaCfg1 = 0x00203949;
823 phycfg->LanePisoCfg1 = 0x000000FF;
824 phycfg->LanePisoCfg2 = 0xFF000001;
825 phycfg->LanePisoCfg3 = 0xE7011300;
826 phycfg->LanePisoCfg4 = 0x63349140;
827 phycfg->LanePisoCfg5 = 0xF8102036;
828 phycfg->LanePisoCfg6 = 0xF80D9300;
829 phycfg->LaneBctCtrl = 0x00FB33F8;
830}
831
832
833
834
835
836
837static
838void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
839{
840 switch (pm8001_ha->pdev->subsystem_device) {
841 case 0x0070:
842 case 0x0072:
843 *phymask = 0x0000;
844 break;
845
846 case 0x0071:
847 case 0x0073:
848 *phymask = 0xFFFF;
849 break;
850
851 case 0x0080:
852 *phymask = 0x00F0;
853 break;
854
855 case 0x0081:
856 *phymask = 0x0FF0;
857 break;
858
859 case 0x0082:
860 *phymask = 0xFF00;
861 break;
862
863 default:
864 pm8001_dbg(pm8001_ha, INIT,
865 "Unknown subsystem device=0x%.04x\n",
866 pm8001_ha->pdev->subsystem_device);
867 }
868}
869
870
871
872
873
874static
875int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
876{
877 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
878 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
879 int phymask = 0;
880 int i = 0;
881
882 memset(&phycfg_int, 0, sizeof(phycfg_int));
883 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
884
885 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
886 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
887 pm8001_get_phy_mask(pm8001_ha, &phymask);
888
889 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
890 if (phymask & (1 << i)) {
891 pm8001_set_phy_profile_single(pm8001_ha, i,
892 sizeof(phycfg_int) / sizeof(u32),
893 (u32 *)&phycfg_int);
894
895 } else {
896 pm8001_set_phy_profile_single(pm8001_ha, i,
897 sizeof(phycfg_ext) / sizeof(u32),
898 (u32 *)&phycfg_ext);
899 }
900 }
901
902 return 0;
903}
904
905
906
907
908
909static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
910{
911 switch (pm8001_ha->pdev->subsystem_vendor) {
912 case PCI_VENDOR_ID_ATTO:
913 if (pm8001_ha->pdev->device == 0x0042)
914 return 0;
915 else
916 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
917
918 case PCI_VENDOR_ID_ADAPTEC2:
919 case 0:
920 return 0;
921
922 default:
923 return pm8001_get_phy_settings_info(pm8001_ha);
924 }
925}
926
927#ifdef PM8001_USE_MSIX
928
929
930
931
932static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
933{
934 u32 number_of_intr;
935 int rc, cpu_online_count;
936 unsigned int allocated_irq_vectors;
937
938
939 if (pm8001_ha->chip_id == chip_8001) {
940 number_of_intr = 1;
941 } else {
942 number_of_intr = PM8001_MAX_MSIX_VEC;
943 }
944
945 cpu_online_count = num_online_cpus();
946 number_of_intr = min_t(int, cpu_online_count, number_of_intr);
947 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
948 number_of_intr, PCI_IRQ_MSIX);
949 allocated_irq_vectors = rc;
950 if (rc < 0)
951 return rc;
952
953
954 number_of_intr = min_t(int, allocated_irq_vectors, number_of_intr);
955 pm8001_ha->number_of_intr = number_of_intr;
956
957
958 pm8001_ha->max_q_num = number_of_intr;
959
960 pm8001_dbg(pm8001_ha, INIT,
961 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
962 rc, pm8001_ha->number_of_intr);
963 return 0;
964}
965
966static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
967{
968 u32 i = 0, j = 0;
969 int flag = 0, rc = 0;
970 int nr_irqs = pm8001_ha->number_of_intr;
971
972 if (pm8001_ha->chip_id != chip_8001)
973 flag &= ~IRQF_SHARED;
974
975 pm8001_dbg(pm8001_ha, INIT,
976 "pci_enable_msix request number of intr %d\n",
977 pm8001_ha->number_of_intr);
978
979 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
980 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
981
982 for (i = 0; i < nr_irqs; i++) {
983 snprintf(pm8001_ha->intr_drvname[i],
984 sizeof(pm8001_ha->intr_drvname[0]),
985 "%s-%d", pm8001_ha->name, i);
986 pm8001_ha->irq_vector[i].irq_id = i;
987 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
988
989 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
990 pm8001_interrupt_handler_msix, flag,
991 pm8001_ha->intr_drvname[i],
992 &(pm8001_ha->irq_vector[i]));
993 if (rc) {
994 for (j = 0; j < i; j++) {
995 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
996 &(pm8001_ha->irq_vector[i]));
997 }
998 pci_free_irq_vectors(pm8001_ha->pdev);
999 break;
1000 }
1001 }
1002
1003 return rc;
1004}
1005#endif
1006
1007static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
1008{
1009 struct pci_dev *pdev;
1010
1011 pdev = pm8001_ha->pdev;
1012
1013#ifdef PM8001_USE_MSIX
1014 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1015 return pm8001_setup_msix(pm8001_ha);
1016 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1017#endif
1018 return 0;
1019}
1020
1021
1022
1023
1024
1025static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1026{
1027 struct pci_dev *pdev;
1028 int rc;
1029
1030 pdev = pm8001_ha->pdev;
1031
1032#ifdef PM8001_USE_MSIX
1033 if (pdev->msix_cap && pci_msi_enabled())
1034 return pm8001_request_msix(pm8001_ha);
1035 else {
1036 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1037 goto intx;
1038 }
1039#endif
1040
1041intx:
1042
1043 pm8001_ha->irq_vector[0].irq_id = 0;
1044 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1045 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1046 pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1047 return rc;
1048}
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059static int pm8001_pci_probe(struct pci_dev *pdev,
1060 const struct pci_device_id *ent)
1061{
1062 unsigned int rc;
1063 u32 pci_reg;
1064 u8 i = 0;
1065 struct pm8001_hba_info *pm8001_ha;
1066 struct Scsi_Host *shost = NULL;
1067 const struct pm8001_chip_info *chip;
1068 struct sas_ha_struct *sha;
1069
1070 dev_printk(KERN_INFO, &pdev->dev,
1071 "pm80xx: driver version %s\n", DRV_VERSION);
1072 rc = pci_enable_device(pdev);
1073 if (rc)
1074 goto err_out_enable;
1075 pci_set_master(pdev);
1076
1077
1078
1079
1080
1081 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1082 pci_reg |= 0x157;
1083 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1084 rc = pci_request_regions(pdev, DRV_NAME);
1085 if (rc)
1086 goto err_out_disable;
1087 rc = pci_go_44(pdev);
1088 if (rc)
1089 goto err_out_regions;
1090
1091 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1092 if (!shost) {
1093 rc = -ENOMEM;
1094 goto err_out_regions;
1095 }
1096 chip = &pm8001_chips[ent->driver_data];
1097 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1098 if (!sha) {
1099 rc = -ENOMEM;
1100 goto err_out_free_host;
1101 }
1102 SHOST_TO_SAS_HA(shost) = sha;
1103
1104 rc = pm8001_prep_sas_ha_init(shost, chip);
1105 if (rc) {
1106 rc = -ENOMEM;
1107 goto err_out_free;
1108 }
1109 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1110
1111 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1112 if (!pm8001_ha) {
1113 rc = -ENOMEM;
1114 goto err_out_free;
1115 }
1116
1117 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1118 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1119 if (rc) {
1120 pm8001_dbg(pm8001_ha, FAIL,
1121 "chip_init failed [ret: %d]\n", rc);
1122 goto err_out_ha_free;
1123 }
1124
1125 rc = pm8001_init_ccb_tag(pm8001_ha, shost, pdev);
1126 if (rc)
1127 goto err_out_enable;
1128
1129 rc = scsi_add_host(shost, &pdev->dev);
1130 if (rc)
1131 goto err_out_ha_free;
1132
1133 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1134 if (pm8001_ha->chip_id != chip_8001) {
1135 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1136 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1137
1138 pm80xx_set_thermal_config(pm8001_ha);
1139 }
1140
1141 pm8001_init_sas_add(pm8001_ha);
1142
1143 rc = pm8001_configure_phy_settings(pm8001_ha);
1144 if (rc)
1145 goto err_out_shost;
1146
1147 pm8001_post_sas_ha_init(shost, chip);
1148 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1149 if (rc) {
1150 pm8001_dbg(pm8001_ha, FAIL,
1151 "sas_register_ha failed [ret: %d]\n", rc);
1152 goto err_out_shost;
1153 }
1154 list_add_tail(&pm8001_ha->list, &hba_list);
1155 pm8001_ha->flags = PM8001F_RUN_TIME;
1156 scsi_scan_host(pm8001_ha->shost);
1157 return 0;
1158
1159err_out_shost:
1160 scsi_remove_host(pm8001_ha->shost);
1161err_out_ha_free:
1162 pm8001_free(pm8001_ha);
1163err_out_free:
1164 kfree(sha);
1165err_out_free_host:
1166 scsi_host_put(shost);
1167err_out_regions:
1168 pci_release_regions(pdev);
1169err_out_disable:
1170 pci_disable_device(pdev);
1171err_out_enable:
1172 return rc;
1173}
1174
1175
1176
1177
1178
1179
1180
1181static int
1182pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha, struct Scsi_Host *shost,
1183 struct pci_dev *pdev)
1184{
1185 int i = 0;
1186 u32 max_out_io, ccb_count;
1187 u32 can_queue;
1188
1189 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1190 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1191
1192
1193 can_queue = ccb_count - PM8001_RESERVE_SLOT;
1194 shost->can_queue = can_queue;
1195
1196 pm8001_ha->tags = kzalloc(ccb_count, GFP_KERNEL);
1197 if (!pm8001_ha->tags)
1198 goto err_out;
1199
1200
1201 pm8001_ha->ccb_info =
1202 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1203 if (!pm8001_ha->ccb_info) {
1204 pm8001_dbg(pm8001_ha, FAIL,
1205 "Unable to allocate memory for ccb\n");
1206 goto err_out_noccb;
1207 }
1208 for (i = 0; i < ccb_count; i++) {
1209 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(&pdev->dev,
1210 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1211 &pm8001_ha->ccb_info[i].ccb_dma_handle,
1212 GFP_KERNEL);
1213 if (!pm8001_ha->ccb_info[i].buf_prd) {
1214 pm8001_dbg(pm8001_ha, FAIL,
1215 "ccb prd memory allocation error\n");
1216 goto err_out;
1217 }
1218 pm8001_ha->ccb_info[i].task = NULL;
1219 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
1220 pm8001_ha->ccb_info[i].device = NULL;
1221 ++pm8001_ha->tags_num;
1222 }
1223 return 0;
1224
1225err_out_noccb:
1226 kfree(pm8001_ha->devices);
1227err_out:
1228 return -ENOMEM;
1229}
1230
1231static void pm8001_pci_remove(struct pci_dev *pdev)
1232{
1233 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1234 struct pm8001_hba_info *pm8001_ha;
1235 int i, j;
1236 pm8001_ha = sha->lldd_ha;
1237 sas_unregister_ha(sha);
1238 sas_remove_host(pm8001_ha->shost);
1239 list_del(&pm8001_ha->list);
1240 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1241 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1242
1243#ifdef PM8001_USE_MSIX
1244 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1245 synchronize_irq(pci_irq_vector(pdev, i));
1246 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1247 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1248 pci_free_irq_vectors(pdev);
1249#else
1250 free_irq(pm8001_ha->irq, sha);
1251#endif
1252#ifdef PM8001_USE_TASKLET
1253
1254 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1255 (pm8001_ha->chip_id == chip_8001))
1256 tasklet_kill(&pm8001_ha->tasklet[0]);
1257 else
1258 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1259 tasklet_kill(&pm8001_ha->tasklet[j]);
1260#endif
1261 scsi_host_put(pm8001_ha->shost);
1262 pm8001_free(pm8001_ha);
1263 kfree(sha->sas_phy);
1264 kfree(sha->sas_port);
1265 kfree(sha);
1266 pci_release_regions(pdev);
1267 pci_disable_device(pdev);
1268}
1269
1270
1271
1272
1273
1274
1275
1276static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1277{
1278 struct pci_dev *pdev = to_pci_dev(dev);
1279 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1280 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1281 int i, j;
1282 sas_suspend_ha(sha);
1283 flush_workqueue(pm8001_wq);
1284 scsi_block_requests(pm8001_ha->shost);
1285 if (!pdev->pm_cap) {
1286 dev_err(dev, " PCI PM not supported\n");
1287 return -ENODEV;
1288 }
1289 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1290 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1291#ifdef PM8001_USE_MSIX
1292 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1293 synchronize_irq(pci_irq_vector(pdev, i));
1294 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1295 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1296 pci_free_irq_vectors(pdev);
1297#else
1298 free_irq(pm8001_ha->irq, sha);
1299#endif
1300#ifdef PM8001_USE_TASKLET
1301
1302 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1303 (pm8001_ha->chip_id == chip_8001))
1304 tasklet_kill(&pm8001_ha->tasklet[0]);
1305 else
1306 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1307 tasklet_kill(&pm8001_ha->tasklet[j]);
1308#endif
1309 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1310 "suspended state\n", pdev,
1311 pm8001_ha->name);
1312 return 0;
1313}
1314
1315
1316
1317
1318
1319
1320
1321static int __maybe_unused pm8001_pci_resume(struct device *dev)
1322{
1323 struct pci_dev *pdev = to_pci_dev(dev);
1324 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1325 struct pm8001_hba_info *pm8001_ha;
1326 int rc;
1327 u8 i = 0, j;
1328 u32 device_state;
1329 DECLARE_COMPLETION_ONSTACK(completion);
1330 pm8001_ha = sha->lldd_ha;
1331 device_state = pdev->current_state;
1332
1333 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1334 pdev, pm8001_ha->name, device_state);
1335
1336 rc = pci_go_44(pdev);
1337 if (rc)
1338 goto err_out_disable;
1339 sas_prep_resume_ha(sha);
1340
1341 if (pm8001_ha->chip_id == chip_8001) {
1342 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1343 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1344 }
1345 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1346 if (rc)
1347 goto err_out_disable;
1348
1349
1350 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1351
1352 rc = pm8001_request_irq(pm8001_ha);
1353 if (rc)
1354 goto err_out_disable;
1355#ifdef PM8001_USE_TASKLET
1356
1357 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1358 (pm8001_ha->chip_id == chip_8001))
1359 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1360 (unsigned long)&(pm8001_ha->irq_vector[0]));
1361 else
1362 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1363 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1364 (unsigned long)&(pm8001_ha->irq_vector[j]));
1365#endif
1366 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1367 if (pm8001_ha->chip_id != chip_8001) {
1368 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1369 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1370 }
1371
1372
1373
1374
1375
1376
1377 if (pm8001_ha->chip_id == chip_8070 ||
1378 pm8001_ha->chip_id == chip_8072) {
1379 mdelay(500);
1380 }
1381
1382
1383
1384 pm8001_ha->flags = PM8001F_RUN_TIME;
1385 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1386 pm8001_ha->phy[i].enable_completion = &completion;
1387 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1388 wait_for_completion(&completion);
1389 }
1390 sas_resume_ha(sha);
1391 return 0;
1392
1393err_out_disable:
1394 scsi_remove_host(pm8001_ha->shost);
1395
1396 return rc;
1397}
1398
1399
1400
1401
1402static struct pci_device_id pm8001_pci_table[] = {
1403 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1404 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1405 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1406 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1407
1408 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1409 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1410 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1411 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1412 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1413 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1414 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1415 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1416 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1417 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1418 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1419 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1420 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1421 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1422 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1423 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1424 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1425 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1426 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1427 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1428 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1429 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1430 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1431 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1432 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1433 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1434 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1435 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1436 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1437 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1438 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1439 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1440 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1441 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1442 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1443 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1444 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1445 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1446 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1447 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1448 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1449 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1450 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1451 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1452 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1453 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1454 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1455 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1456 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1457 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1458 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1459 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1460 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1461 { PCI_VENDOR_ID_ATTO, 0x8070,
1462 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1463 { PCI_VENDOR_ID_ATTO, 0x8070,
1464 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1465 { PCI_VENDOR_ID_ATTO, 0x8072,
1466 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1467 { PCI_VENDOR_ID_ATTO, 0x8072,
1468 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1469 { PCI_VENDOR_ID_ATTO, 0x8070,
1470 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1471 { PCI_VENDOR_ID_ATTO, 0x8072,
1472 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1473 { PCI_VENDOR_ID_ATTO, 0x8072,
1474 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1475 {}
1476};
1477
1478static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1479 pm8001_pci_suspend,
1480 pm8001_pci_resume);
1481
1482static struct pci_driver pm8001_pci_driver = {
1483 .name = DRV_NAME,
1484 .id_table = pm8001_pci_table,
1485 .probe = pm8001_pci_probe,
1486 .remove = pm8001_pci_remove,
1487 .driver.pm = &pm8001_pci_pm_ops,
1488};
1489
1490
1491
1492
1493static int __init pm8001_init(void)
1494{
1495 int rc = -ENOMEM;
1496
1497 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1498 if (!pm8001_wq)
1499 goto err;
1500
1501 pm8001_id = 0;
1502 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1503 if (!pm8001_stt)
1504 goto err_wq;
1505 rc = pci_register_driver(&pm8001_pci_driver);
1506 if (rc)
1507 goto err_tp;
1508 return 0;
1509
1510err_tp:
1511 sas_release_transport(pm8001_stt);
1512err_wq:
1513 destroy_workqueue(pm8001_wq);
1514err:
1515 return rc;
1516}
1517
1518static void __exit pm8001_exit(void)
1519{
1520 pci_unregister_driver(&pm8001_pci_driver);
1521 sas_release_transport(pm8001_stt);
1522 destroy_workqueue(pm8001_wq);
1523}
1524
1525module_init(pm8001_init);
1526module_exit(pm8001_exit);
1527
1528MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1529MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1530MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1531MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1532MODULE_DESCRIPTION(
1533 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1534 "SAS/SATA controller driver");
1535MODULE_VERSION(DRV_VERSION);
1536MODULE_LICENSE("GPL");
1537MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1538
1539