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23#ifndef LINUX_PCI_H
24#define LINUX_PCI_H
25
26
27#include <linux/mod_devicetable.h>
28
29#include <linux/types.h>
30#include <linux/init.h>
31#include <linux/ioport.h>
32#include <linux/list.h>
33#include <linux/compiler.h>
34#include <linux/errno.h>
35#include <linux/kobject.h>
36#include <linux/atomic.h>
37#include <linux/device.h>
38#include <linux/interrupt.h>
39#include <linux/io.h>
40#include <linux/resource_ext.h>
41#include <uapi/linux/pci.h>
42
43#include <linux/pci_ids.h>
44
45#define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
46 PCI_STATUS_SIG_SYSTEM_ERROR | \
47 PCI_STATUS_REC_MASTER_ABORT | \
48 PCI_STATUS_REC_TARGET_ABORT | \
49 PCI_STATUS_SIG_TARGET_ABORT | \
50 PCI_STATUS_PARITY)
51
52
53#define PCI_NUM_RESET_METHODS 7
54
55#define PCI_RESET_PROBE true
56#define PCI_RESET_DO_RESET false
57
58
59
60
61
62
63
64
65
66
67
68
69
70#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
71
72#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
73
74
75struct pci_slot {
76 struct pci_bus *bus;
77 struct list_head list;
78 struct hotplug_slot *hotplug;
79 unsigned char number;
80 struct kobject kobj;
81};
82
83static inline const char *pci_slot_name(const struct pci_slot *slot)
84{
85 return kobject_name(&slot->kobj);
86}
87
88
89enum pci_mmap_state {
90 pci_mmap_io,
91 pci_mmap_mem
92};
93
94
95enum {
96
97 PCI_STD_RESOURCES,
98 PCI_STD_RESOURCE_END = PCI_STD_RESOURCES + PCI_STD_NUM_BARS - 1,
99
100
101 PCI_ROM_RESOURCE,
102
103
104#ifdef CONFIG_PCI_IOV
105 PCI_IOV_RESOURCES,
106 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
107#endif
108
109
110#define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
111#define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
112#define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
113
114
115#define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
116#define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
117#define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
118#define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
119
120
121#define PCI_BRIDGE_RESOURCE_NUM 4
122
123
124 PCI_BRIDGE_RESOURCES,
125 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
126 PCI_BRIDGE_RESOURCE_NUM - 1,
127
128
129 PCI_NUM_RESOURCES,
130
131
132 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
133};
134
135
136
137
138
139
140
141
142
143
144
145
146enum pci_interrupt_pin {
147 PCI_INTERRUPT_UNKNOWN,
148 PCI_INTERRUPT_INTA,
149 PCI_INTERRUPT_INTB,
150 PCI_INTERRUPT_INTC,
151 PCI_INTERRUPT_INTD,
152};
153
154
155#define PCI_NUM_INTX 4
156
157
158
159
160
161typedef int __bitwise pci_power_t;
162
163#define PCI_D0 ((pci_power_t __force) 0)
164#define PCI_D1 ((pci_power_t __force) 1)
165#define PCI_D2 ((pci_power_t __force) 2)
166#define PCI_D3hot ((pci_power_t __force) 3)
167#define PCI_D3cold ((pci_power_t __force) 4)
168#define PCI_UNKNOWN ((pci_power_t __force) 5)
169#define PCI_POWER_ERROR ((pci_power_t __force) -1)
170
171
172extern const char *pci_power_names[];
173
174static inline const char *pci_power_name(pci_power_t state)
175{
176 return pci_power_names[1 + (__force int) state];
177}
178
179
180
181
182
183
184
185
186typedef unsigned int __bitwise pci_channel_state_t;
187
188enum {
189
190 pci_channel_io_normal = (__force pci_channel_state_t) 1,
191
192
193 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
194
195
196 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
197};
198
199typedef unsigned int __bitwise pcie_reset_state_t;
200
201enum pcie_reset_state {
202
203 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
204
205
206 pcie_warm_reset = (__force pcie_reset_state_t) 2,
207
208
209 pcie_hot_reset = (__force pcie_reset_state_t) 3
210};
211
212typedef unsigned short __bitwise pci_dev_flags_t;
213enum pci_dev_flags {
214
215 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
216
217 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
218
219 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
220
221 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
222
223 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
224
225 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
226
227 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
228
229 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
230
231 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
232
233 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
234
235 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
236};
237
238enum pci_irq_reroute_variant {
239 INTEL_IRQ_REROUTE_VARIANT = 1,
240 MAX_IRQ_REROUTE_VARIANTS = 3
241};
242
243typedef unsigned short __bitwise pci_bus_flags_t;
244enum pci_bus_flags {
245 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
246 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
247 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
248 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
249};
250
251
252enum pcie_link_width {
253 PCIE_LNK_WIDTH_RESRV = 0x00,
254 PCIE_LNK_X1 = 0x01,
255 PCIE_LNK_X2 = 0x02,
256 PCIE_LNK_X4 = 0x04,
257 PCIE_LNK_X8 = 0x08,
258 PCIE_LNK_X12 = 0x0c,
259 PCIE_LNK_X16 = 0x10,
260 PCIE_LNK_X32 = 0x20,
261 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
262};
263
264
265enum pci_bus_speed {
266 PCI_SPEED_33MHz = 0x00,
267 PCI_SPEED_66MHz = 0x01,
268 PCI_SPEED_66MHz_PCIX = 0x02,
269 PCI_SPEED_100MHz_PCIX = 0x03,
270 PCI_SPEED_133MHz_PCIX = 0x04,
271 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
272 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
273 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
274 PCI_SPEED_66MHz_PCIX_266 = 0x09,
275 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
276 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
277 AGP_UNKNOWN = 0x0c,
278 AGP_1X = 0x0d,
279 AGP_2X = 0x0e,
280 AGP_4X = 0x0f,
281 AGP_8X = 0x10,
282 PCI_SPEED_66MHz_PCIX_533 = 0x11,
283 PCI_SPEED_100MHz_PCIX_533 = 0x12,
284 PCI_SPEED_133MHz_PCIX_533 = 0x13,
285 PCIE_SPEED_2_5GT = 0x14,
286 PCIE_SPEED_5_0GT = 0x15,
287 PCIE_SPEED_8_0GT = 0x16,
288 PCIE_SPEED_16_0GT = 0x17,
289 PCIE_SPEED_32_0GT = 0x18,
290 PCIE_SPEED_64_0GT = 0x19,
291 PCI_SPEED_UNKNOWN = 0xff,
292};
293
294enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
295enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
296
297struct pci_vpd {
298 struct mutex lock;
299 unsigned int len;
300 u8 cap;
301};
302
303struct irq_affinity;
304struct pcie_link_state;
305struct pci_sriov;
306struct pci_p2pdma;
307struct rcec_ea;
308
309
310struct pci_dev {
311 struct list_head bus_list;
312 struct pci_bus *bus;
313 struct pci_bus *subordinate;
314
315 void *sysdata;
316 struct proc_dir_entry *procent;
317 struct pci_slot *slot;
318
319 unsigned int devfn;
320 unsigned short vendor;
321 unsigned short device;
322 unsigned short subsystem_vendor;
323 unsigned short subsystem_device;
324 unsigned int class;
325 u8 revision;
326 u8 hdr_type;
327#ifdef CONFIG_PCIEAER
328 u16 aer_cap;
329 struct aer_stats *aer_stats;
330#endif
331#ifdef CONFIG_PCIEPORTBUS
332 struct rcec_ea *rcec_ea;
333 struct pci_dev *rcec;
334#endif
335 u32 devcap;
336 u8 pcie_cap;
337 u8 msi_cap;
338 u8 msix_cap;
339 u8 pcie_mpss:3;
340 u8 rom_base_reg;
341 u8 pin;
342 u16 pcie_flags_reg;
343 unsigned long *dma_alias_mask;
344
345 struct pci_driver *driver;
346 u64 dma_mask;
347
348
349
350
351
352 struct device_dma_parameters dma_parms;
353
354 pci_power_t current_state;
355
356
357 unsigned int imm_ready:1;
358 u8 pm_cap;
359 unsigned int pme_support:5;
360
361 unsigned int pme_poll:1;
362 unsigned int d1_support:1;
363 unsigned int d2_support:1;
364 unsigned int no_d1d2:1;
365 unsigned int no_d3cold:1;
366 unsigned int bridge_d3:1;
367 unsigned int d3cold_allowed:1;
368 unsigned int mmio_always_on:1;
369
370 unsigned int wakeup_prepared:1;
371 unsigned int runtime_d3cold:1;
372
373
374
375 unsigned int skip_bus_pm:1;
376 unsigned int ignore_hotplug:1;
377 unsigned int hotplug_user_indicators:1;
378
379
380 unsigned int clear_retrain_link:1;
381
382 unsigned int d3hot_delay;
383 unsigned int d3cold_delay;
384
385#ifdef CONFIG_PCIEASPM
386 struct pcie_link_state *link_state;
387 unsigned int ltr_path:1;
388
389 u16 l1ss;
390#endif
391 unsigned int pasid_no_tlp:1;
392 unsigned int eetlp_prefix_path:1;
393
394 pci_channel_state_t error_state;
395 struct device dev;
396
397 int cfg_size;
398
399
400
401
402
403 unsigned int irq;
404 struct resource resource[DEVICE_COUNT_RESOURCE];
405
406 bool match_driver;
407
408 unsigned int transparent:1;
409 unsigned int io_window:1;
410 unsigned int pref_window:1;
411 unsigned int pref_64_window:1;
412 unsigned int multifunction:1;
413
414 unsigned int is_busmaster:1;
415 unsigned int no_msi:1;
416 unsigned int no_64bit_msi:1;
417 unsigned int block_cfg_access:1;
418 unsigned int broken_parity_status:1;
419 unsigned int irq_reroute_variant:2;
420 unsigned int msi_enabled:1;
421 unsigned int msix_enabled:1;
422 unsigned int ari_enabled:1;
423 unsigned int ats_enabled:1;
424 unsigned int pasid_enabled:1;
425 unsigned int pri_enabled:1;
426 unsigned int is_managed:1;
427 unsigned int needs_freset:1;
428 unsigned int state_saved:1;
429 unsigned int is_physfn:1;
430 unsigned int is_virtfn:1;
431 unsigned int is_hotplug_bridge:1;
432 unsigned int shpc_managed:1;
433 unsigned int is_thunderbolt:1;
434
435
436
437
438
439
440
441 unsigned int untrusted:1;
442
443
444
445
446
447 unsigned int external_facing:1;
448 unsigned int broken_intx_masking:1;
449 unsigned int io_window_1k:1;
450 unsigned int irq_managed:1;
451 unsigned int non_compliant_bars:1;
452 unsigned int is_probed:1;
453 unsigned int link_active_reporting:1;
454 unsigned int no_vf_scan:1;
455 unsigned int no_command_memory:1;
456 pci_dev_flags_t dev_flags;
457 atomic_t enable_cnt;
458
459 u32 saved_config_space[16];
460 struct hlist_head saved_cap_space;
461 int rom_attr_enabled;
462 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
463 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
464
465#ifdef CONFIG_HOTPLUG_PCI_PCIE
466 unsigned int broken_cmd_compl:1;
467#endif
468#ifdef CONFIG_PCIE_PTM
469 unsigned int ptm_root:1;
470 unsigned int ptm_enabled:1;
471 u8 ptm_granularity;
472#endif
473#ifdef CONFIG_PCI_MSI
474 const struct attribute_group **msi_irq_groups;
475#endif
476 struct pci_vpd vpd;
477#ifdef CONFIG_PCIE_DPC
478 u16 dpc_cap;
479 unsigned int dpc_rp_extensions:1;
480 u8 dpc_rp_log_size;
481#endif
482#ifdef CONFIG_PCI_ATS
483 union {
484 struct pci_sriov *sriov;
485 struct pci_dev *physfn;
486 };
487 u16 ats_cap;
488 u8 ats_stu;
489#endif
490#ifdef CONFIG_PCI_PRI
491 u16 pri_cap;
492 u32 pri_reqs_alloc;
493 unsigned int pasid_required:1;
494#endif
495#ifdef CONFIG_PCI_PASID
496 u16 pasid_cap;
497 u16 pasid_features;
498#endif
499#ifdef CONFIG_PCI_P2PDMA
500 struct pci_p2pdma __rcu *p2pdma;
501#endif
502 u16 acs_cap;
503 phys_addr_t rom;
504 size_t romlen;
505 char *driver_override;
506
507 unsigned long priv_flags;
508
509
510 u8 reset_methods[PCI_NUM_RESET_METHODS];
511};
512
513static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
514{
515#ifdef CONFIG_PCI_IOV
516 if (dev->is_virtfn)
517 dev = dev->physfn;
518#endif
519 return dev;
520}
521
522struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
523
524#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
525#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
526
527static inline int pci_channel_offline(struct pci_dev *pdev)
528{
529 return (pdev->error_state != pci_channel_io_normal);
530}
531
532
533
534
535
536
537
538
539
540#define PCI_DOMAIN_NR_NOT_SET (-1)
541
542struct pci_host_bridge {
543 struct device dev;
544 struct pci_bus *bus;
545 struct pci_ops *ops;
546 struct pci_ops *child_ops;
547 void *sysdata;
548 int busnr;
549 int domain_nr;
550 struct list_head windows;
551 struct list_head dma_ranges;
552 u8 (*swizzle_irq)(struct pci_dev *, u8 *);
553 int (*map_irq)(const struct pci_dev *, u8, u8);
554 void (*release_fn)(struct pci_host_bridge *);
555 void *release_data;
556 unsigned int ignore_reset_delay:1;
557 unsigned int no_ext_tags:1;
558 unsigned int native_aer:1;
559 unsigned int native_pcie_hotplug:1;
560 unsigned int native_shpc_hotplug:1;
561 unsigned int native_pme:1;
562 unsigned int native_ltr:1;
563 unsigned int native_dpc:1;
564 unsigned int preserve_config:1;
565 unsigned int size_windows:1;
566 unsigned int msi_domain:1;
567
568
569 resource_size_t (*align_resource)(struct pci_dev *dev,
570 const struct resource *res,
571 resource_size_t start,
572 resource_size_t size,
573 resource_size_t align);
574 unsigned long private[] ____cacheline_aligned;
575};
576
577#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
578
579static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
580{
581 return (void *)bridge->private;
582}
583
584static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
585{
586 return container_of(priv, struct pci_host_bridge, private);
587}
588
589struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
590struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
591 size_t priv);
592void pci_free_host_bridge(struct pci_host_bridge *bridge);
593struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
594
595void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
596 void (*release_fn)(struct pci_host_bridge *),
597 void *release_data);
598
599int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
600
601
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604
605
606
607
608
609
610
611
612
613
614#define PCI_SUBTRACTIVE_DECODE 0x1
615
616struct pci_bus_resource {
617 struct list_head list;
618 struct resource *res;
619 unsigned int flags;
620};
621
622#define PCI_REGION_FLAG_MASK 0x0fU
623
624struct pci_bus {
625 struct list_head node;
626 struct pci_bus *parent;
627 struct list_head children;
628 struct list_head devices;
629 struct pci_dev *self;
630 struct list_head slots;
631
632 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
633 struct list_head resources;
634 struct resource busn_res;
635
636 struct pci_ops *ops;
637 void *sysdata;
638 struct proc_dir_entry *procdir;
639
640 unsigned char number;
641 unsigned char primary;
642 unsigned char max_bus_speed;
643 unsigned char cur_bus_speed;
644#ifdef CONFIG_PCI_DOMAINS_GENERIC
645 int domain_nr;
646#endif
647
648 char name[48];
649
650 unsigned short bridge_ctl;
651 pci_bus_flags_t bus_flags;
652 struct device *bridge;
653 struct device dev;
654 struct bin_attribute *legacy_io;
655 struct bin_attribute *legacy_mem;
656 unsigned int is_added:1;
657};
658
659#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
660
661static inline u16 pci_dev_id(struct pci_dev *dev)
662{
663 return PCI_DEVID(dev->bus->number, dev->devfn);
664}
665
666
667
668
669
670
671
672
673
674static inline bool pci_is_root_bus(struct pci_bus *pbus)
675{
676 return !(pbus->parent);
677}
678
679
680
681
682
683
684
685
686static inline bool pci_is_bridge(struct pci_dev *dev)
687{
688 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
689 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
690}
691
692#define for_each_pci_bridge(dev, bus) \
693 list_for_each_entry(dev, &bus->devices, bus_list) \
694 if (!pci_is_bridge(dev)) {} else
695
696static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
697{
698 dev = pci_physfn(dev);
699 if (pci_is_root_bus(dev->bus))
700 return NULL;
701
702 return dev->bus->self;
703}
704
705#ifdef CONFIG_PCI_MSI
706static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
707{
708 return pci_dev->msi_enabled || pci_dev->msix_enabled;
709}
710#else
711static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
712#endif
713
714
715#define PCIBIOS_SUCCESSFUL 0x00
716#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
717#define PCIBIOS_BAD_VENDOR_ID 0x83
718#define PCIBIOS_DEVICE_NOT_FOUND 0x86
719#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
720#define PCIBIOS_SET_FAILED 0x88
721#define PCIBIOS_BUFFER_TOO_SMALL 0x89
722
723
724static inline int pcibios_err_to_errno(int err)
725{
726 if (err <= PCIBIOS_SUCCESSFUL)
727 return err;
728
729 switch (err) {
730 case PCIBIOS_FUNC_NOT_SUPPORTED:
731 return -ENOENT;
732 case PCIBIOS_BAD_VENDOR_ID:
733 return -ENOTTY;
734 case PCIBIOS_DEVICE_NOT_FOUND:
735 return -ENODEV;
736 case PCIBIOS_BAD_REGISTER_NUMBER:
737 return -EFAULT;
738 case PCIBIOS_SET_FAILED:
739 return -EIO;
740 case PCIBIOS_BUFFER_TOO_SMALL:
741 return -ENOSPC;
742 }
743
744 return -ERANGE;
745}
746
747
748
749struct pci_ops {
750 int (*add_bus)(struct pci_bus *bus);
751 void (*remove_bus)(struct pci_bus *bus);
752 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
753 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
754 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
755};
756
757
758
759
760
761int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
762 int reg, int len, u32 *val);
763int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
764 int reg, int len, u32 val);
765
766#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
767typedef u64 pci_bus_addr_t;
768#else
769typedef u32 pci_bus_addr_t;
770#endif
771
772struct pci_bus_region {
773 pci_bus_addr_t start;
774 pci_bus_addr_t end;
775};
776
777struct pci_dynids {
778 spinlock_t lock;
779 struct list_head list;
780};
781
782
783
784
785
786
787
788
789
790typedef unsigned int __bitwise pci_ers_result_t;
791
792enum pci_ers_result {
793
794 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
795
796
797 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
798
799
800 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
801
802
803 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
804
805
806 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
807
808
809 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
810};
811
812
813struct pci_error_handlers {
814
815 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
816 pci_channel_state_t error);
817
818
819 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
820
821
822 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
823
824
825 void (*reset_prepare)(struct pci_dev *dev);
826 void (*reset_done)(struct pci_dev *dev);
827
828
829 void (*resume)(struct pci_dev *dev);
830};
831
832
833struct module;
834
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883
884struct pci_driver {
885 struct list_head node;
886 const char *name;
887 const struct pci_device_id *id_table;
888 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
889 void (*remove)(struct pci_dev *dev);
890 int (*suspend)(struct pci_dev *dev, pm_message_t state);
891 int (*resume)(struct pci_dev *dev);
892 void (*shutdown)(struct pci_dev *dev);
893 int (*sriov_configure)(struct pci_dev *dev, int num_vfs);
894 int (*sriov_set_msix_vec_count)(struct pci_dev *vf, int msix_vec_count);
895 u32 (*sriov_get_vf_total_msix)(struct pci_dev *pf);
896 const struct pci_error_handlers *err_handler;
897 const struct attribute_group **groups;
898 const struct attribute_group **dev_groups;
899 struct device_driver driver;
900 struct pci_dynids dynids;
901};
902
903#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
904
905
906
907
908
909
910
911
912
913
914#define PCI_DEVICE(vend,dev) \
915 .vendor = (vend), .device = (dev), \
916 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
917
918
919
920
921
922
923
924
925
926
927
928
929#define PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, driver_override) \
930 .vendor = (vend), .device = (dev), .subvendor = PCI_ANY_ID, \
931 .subdevice = PCI_ANY_ID, .override_only = (driver_override)
932
933
934
935
936
937
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941
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943
944#define PCI_DRIVER_OVERRIDE_DEVICE_VFIO(vend, dev) \
945 PCI_DEVICE_DRIVER_OVERRIDE(vend, dev, PCI_ID_F_VFIO_DRIVER_OVERRIDE)
946
947
948
949
950
951
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953
954
955
956
957#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
958 .vendor = (vend), .device = (dev), \
959 .subvendor = (subvend), .subdevice = (subdev)
960
961
962
963
964
965
966
967
968
969
970#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
971 .class = (dev_class), .class_mask = (dev_class_mask), \
972 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
973 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
974
975
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978
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984
985#define PCI_VDEVICE(vend, dev) \
986 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
987 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
988
989
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991
992
993
994
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996
997
998
999#define PCI_DEVICE_DATA(vend, dev, data) \
1000 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
1001 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
1002 .driver_data = (kernel_ulong_t)(data)
1003
1004enum {
1005 PCI_REASSIGN_ALL_RSRC = 0x00000001,
1006 PCI_REASSIGN_ALL_BUS = 0x00000002,
1007 PCI_PROBE_ONLY = 0x00000004,
1008 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
1009 PCI_ENABLE_PROC_DOMAINS = 0x00000010,
1010 PCI_COMPAT_DOMAIN_0 = 0x00000020,
1011 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
1012};
1013
1014#define PCI_IRQ_LEGACY (1 << 0)
1015#define PCI_IRQ_MSI (1 << 1)
1016#define PCI_IRQ_MSIX (1 << 2)
1017#define PCI_IRQ_AFFINITY (1 << 3)
1018
1019
1020#ifdef CONFIG_PCI
1021
1022extern unsigned int pci_flags;
1023
1024static inline void pci_set_flags(int flags) { pci_flags = flags; }
1025static inline void pci_add_flags(int flags) { pci_flags |= flags; }
1026static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
1027static inline int pci_has_flag(int flag) { return pci_flags & flag; }
1028
1029void pcie_bus_configure_settings(struct pci_bus *bus);
1030
1031enum pcie_bus_config_types {
1032 PCIE_BUS_TUNE_OFF,
1033 PCIE_BUS_DEFAULT,
1034 PCIE_BUS_SAFE,
1035 PCIE_BUS_PERFORMANCE,
1036 PCIE_BUS_PEER2PEER,
1037};
1038
1039extern enum pcie_bus_config_types pcie_bus_config;
1040
1041extern struct bus_type pci_bus_type;
1042
1043
1044
1045extern struct list_head pci_root_buses;
1046
1047int no_pci_devices(void);
1048
1049void pcibios_resource_survey_bus(struct pci_bus *bus);
1050void pcibios_bus_add_device(struct pci_dev *pdev);
1051void pcibios_add_bus(struct pci_bus *bus);
1052void pcibios_remove_bus(struct pci_bus *bus);
1053void pcibios_fixup_bus(struct pci_bus *);
1054int __must_check pcibios_enable_device(struct pci_dev *, int mask);
1055
1056char *pcibios_setup(char *str);
1057
1058
1059resource_size_t pcibios_align_resource(void *, const struct resource *,
1060 resource_size_t,
1061 resource_size_t);
1062
1063
1064void pci_fixup_cardbus(struct pci_bus *);
1065
1066
1067
1068void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
1069 struct resource *res);
1070void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
1071 struct pci_bus_region *region);
1072void pcibios_scan_specific_bus(int busn);
1073struct pci_bus *pci_find_bus(int domain, int busnr);
1074void pci_bus_add_devices(const struct pci_bus *bus);
1075struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
1076struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1077 struct pci_ops *ops, void *sysdata,
1078 struct list_head *resources);
1079int pci_host_probe(struct pci_host_bridge *bridge);
1080int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
1081int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
1082void pci_bus_release_busn_res(struct pci_bus *b);
1083struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1084 struct pci_ops *ops, void *sysdata,
1085 struct list_head *resources);
1086int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
1087struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1088 int busnr);
1089struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
1090 const char *name,
1091 struct hotplug_slot *hotplug);
1092void pci_destroy_slot(struct pci_slot *slot);
1093#ifdef CONFIG_SYSFS
1094void pci_dev_assign_slot(struct pci_dev *dev);
1095#else
1096static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
1097#endif
1098int pci_scan_slot(struct pci_bus *bus, int devfn);
1099struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
1100void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
1101unsigned int pci_scan_child_bus(struct pci_bus *bus);
1102void pci_bus_add_device(struct pci_dev *dev);
1103void pci_read_bridge_bases(struct pci_bus *child);
1104struct resource *pci_find_parent_resource(const struct pci_dev *dev,
1105 struct resource *res);
1106u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
1107int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
1108u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
1109struct pci_dev *pci_dev_get(struct pci_dev *dev);
1110void pci_dev_put(struct pci_dev *dev);
1111void pci_remove_bus(struct pci_bus *b);
1112void pci_stop_and_remove_bus_device(struct pci_dev *dev);
1113void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
1114void pci_stop_root_bus(struct pci_bus *bus);
1115void pci_remove_root_bus(struct pci_bus *bus);
1116void pci_setup_cardbus(struct pci_bus *bus);
1117void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
1118void pci_sort_breadthfirst(void);
1119#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
1120#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
1121
1122
1123
1124u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1125u8 pci_find_capability(struct pci_dev *dev, int cap);
1126u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
1127u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
1128u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap);
1129u16 pci_find_ext_capability(struct pci_dev *dev, int cap);
1130u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 pos, int cap);
1131struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1132u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap);
1133
1134u64 pci_get_dsn(struct pci_dev *dev);
1135
1136struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1137 struct pci_dev *from);
1138struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1139 unsigned int ss_vendor, unsigned int ss_device,
1140 struct pci_dev *from);
1141struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1142struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1143 unsigned int devfn);
1144struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1145int pci_dev_present(const struct pci_device_id *ids);
1146
1147int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1148 int where, u8 *val);
1149int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1150 int where, u16 *val);
1151int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1152 int where, u32 *val);
1153int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1154 int where, u8 val);
1155int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1156 int where, u16 val);
1157int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1158 int where, u32 val);
1159
1160int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1161 int where, int size, u32 *val);
1162int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1163 int where, int size, u32 val);
1164int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1165 int where, int size, u32 *val);
1166int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1167 int where, int size, u32 val);
1168
1169struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1170
1171int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1172int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1173int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1174int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1175int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1176int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1177
1178int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1179int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1180int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1181int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1182int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1183 u16 clear, u16 set);
1184int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1185 u32 clear, u32 set);
1186
1187static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1188 u16 set)
1189{
1190 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1191}
1192
1193static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1194 u32 set)
1195{
1196 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1197}
1198
1199static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1200 u16 clear)
1201{
1202 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1203}
1204
1205static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1206 u32 clear)
1207{
1208 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1209}
1210
1211
1212int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1213int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1214int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1215int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1216int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1217int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1218
1219int __must_check pci_enable_device(struct pci_dev *dev);
1220int __must_check pci_enable_device_io(struct pci_dev *dev);
1221int __must_check pci_enable_device_mem(struct pci_dev *dev);
1222int __must_check pci_reenable_device(struct pci_dev *);
1223int __must_check pcim_enable_device(struct pci_dev *pdev);
1224void pcim_pin_device(struct pci_dev *pdev);
1225
1226static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1227{
1228
1229
1230
1231
1232 return !pdev->broken_intx_masking;
1233}
1234
1235static inline int pci_is_enabled(struct pci_dev *pdev)
1236{
1237 return (atomic_read(&pdev->enable_cnt) > 0);
1238}
1239
1240static inline int pci_is_managed(struct pci_dev *pdev)
1241{
1242 return pdev->is_managed;
1243}
1244
1245void pci_disable_device(struct pci_dev *dev);
1246
1247extern unsigned int pcibios_max_latency;
1248void pci_set_master(struct pci_dev *dev);
1249void pci_clear_master(struct pci_dev *dev);
1250
1251int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1252int pci_set_cacheline_size(struct pci_dev *dev);
1253int __must_check pci_set_mwi(struct pci_dev *dev);
1254int __must_check pcim_set_mwi(struct pci_dev *dev);
1255int pci_try_set_mwi(struct pci_dev *dev);
1256void pci_clear_mwi(struct pci_dev *dev);
1257void pci_disable_parity(struct pci_dev *dev);
1258void pci_intx(struct pci_dev *dev, int enable);
1259bool pci_check_and_mask_intx(struct pci_dev *dev);
1260bool pci_check_and_unmask_intx(struct pci_dev *dev);
1261int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1262int pci_wait_for_pending_transaction(struct pci_dev *dev);
1263int pcix_get_max_mmrbc(struct pci_dev *dev);
1264int pcix_get_mmrbc(struct pci_dev *dev);
1265int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1266int pcie_get_readrq(struct pci_dev *dev);
1267int pcie_set_readrq(struct pci_dev *dev, int rq);
1268int pcie_get_mps(struct pci_dev *dev);
1269int pcie_set_mps(struct pci_dev *dev, int mps);
1270u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1271 enum pci_bus_speed *speed,
1272 enum pcie_link_width *width);
1273void pcie_print_link_status(struct pci_dev *dev);
1274int pcie_reset_flr(struct pci_dev *dev, bool probe);
1275int pcie_flr(struct pci_dev *dev);
1276int __pci_reset_function_locked(struct pci_dev *dev);
1277int pci_reset_function(struct pci_dev *dev);
1278int pci_reset_function_locked(struct pci_dev *dev);
1279int pci_try_reset_function(struct pci_dev *dev);
1280int pci_probe_reset_slot(struct pci_slot *slot);
1281int pci_probe_reset_bus(struct pci_bus *bus);
1282int pci_reset_bus(struct pci_dev *dev);
1283void pci_reset_secondary_bus(struct pci_dev *dev);
1284void pcibios_reset_secondary_bus(struct pci_dev *dev);
1285void pci_update_resource(struct pci_dev *dev, int resno);
1286int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1287int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1288void pci_release_resource(struct pci_dev *dev, int resno);
1289static inline int pci_rebar_bytes_to_size(u64 bytes)
1290{
1291 bytes = roundup_pow_of_two(bytes);
1292
1293
1294 return max(ilog2(bytes), 20) - 20;
1295}
1296
1297u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
1298int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1299int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1300bool pci_device_is_present(struct pci_dev *pdev);
1301void pci_ignore_hotplug(struct pci_dev *dev);
1302struct pci_dev *pci_real_dma_dev(struct pci_dev *dev);
1303int pci_status_get_and_clear_errors(struct pci_dev *pdev);
1304
1305int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1306 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1307 const char *fmt, ...);
1308void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1309
1310
1311int pci_enable_rom(struct pci_dev *pdev);
1312void pci_disable_rom(struct pci_dev *pdev);
1313void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1314void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1315
1316
1317int pci_save_state(struct pci_dev *dev);
1318void pci_restore_state(struct pci_dev *dev);
1319struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1320int pci_load_saved_state(struct pci_dev *dev,
1321 struct pci_saved_state *state);
1322int pci_load_and_free_saved_state(struct pci_dev *dev,
1323 struct pci_saved_state **state);
1324int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state);
1325int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1326pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1327bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1328void pci_pme_active(struct pci_dev *dev, bool enable);
1329int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1330int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1331int pci_prepare_to_sleep(struct pci_dev *dev);
1332int pci_back_from_sleep(struct pci_dev *dev);
1333bool pci_dev_run_wake(struct pci_dev *dev);
1334void pci_d3cold_enable(struct pci_dev *dev);
1335void pci_d3cold_disable(struct pci_dev *dev);
1336bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1337void pci_resume_bus(struct pci_bus *bus);
1338void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1339
1340
1341void set_pcie_port_type(struct pci_dev *pdev);
1342void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1343
1344
1345unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1346unsigned int pci_rescan_bus(struct pci_bus *bus);
1347void pci_lock_rescan_remove(void);
1348void pci_unlock_rescan_remove(void);
1349
1350
1351ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1352ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1353
1354
1355resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1356void pci_bus_assign_resources(const struct pci_bus *bus);
1357void pci_bus_claim_resources(struct pci_bus *bus);
1358void pci_bus_size_bridges(struct pci_bus *bus);
1359int pci_claim_resource(struct pci_dev *, int);
1360int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1361void pci_assign_unassigned_resources(void);
1362void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1363void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1364void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1365int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1366void pdev_enable_device(struct pci_dev *);
1367int pci_enable_resources(struct pci_dev *, int mask);
1368void pci_assign_irq(struct pci_dev *dev);
1369struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1370#define HAVE_PCI_REQ_REGIONS 2
1371int __must_check pci_request_regions(struct pci_dev *, const char *);
1372int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1373void pci_release_regions(struct pci_dev *);
1374int __must_check pci_request_region(struct pci_dev *, int, const char *);
1375void pci_release_region(struct pci_dev *, int);
1376int pci_request_selected_regions(struct pci_dev *, int, const char *);
1377int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1378void pci_release_selected_regions(struct pci_dev *, int);
1379
1380
1381void pci_add_resource(struct list_head *resources, struct resource *res);
1382void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1383 resource_size_t offset);
1384void pci_free_resource_list(struct list_head *resources);
1385void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1386 unsigned int flags);
1387struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1388void pci_bus_remove_resources(struct pci_bus *bus);
1389int devm_request_pci_bus_resources(struct device *dev,
1390 struct list_head *resources);
1391
1392
1393int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1394
1395#define pci_bus_for_each_resource(bus, res, i) \
1396 for (i = 0; \
1397 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1398 i++)
1399
1400int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1401 struct resource *res, resource_size_t size,
1402 resource_size_t align, resource_size_t min,
1403 unsigned long type_mask,
1404 resource_size_t (*alignf)(void *,
1405 const struct resource *,
1406 resource_size_t,
1407 resource_size_t),
1408 void *alignf_data);
1409
1410
1411int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1412 resource_size_t size);
1413unsigned long pci_address_to_pio(phys_addr_t addr);
1414phys_addr_t pci_pio_to_address(unsigned long pio);
1415int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1416int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1417 phys_addr_t phys_addr);
1418void pci_unmap_iospace(struct resource *res);
1419void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1420 resource_size_t offset,
1421 resource_size_t size);
1422void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1423 struct resource *res);
1424
1425static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1426{
1427 struct pci_bus_region region;
1428
1429 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1430 return region.start;
1431}
1432
1433
1434int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1435 const char *mod_name);
1436
1437
1438#define pci_register_driver(driver) \
1439 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1440
1441void pci_unregister_driver(struct pci_driver *dev);
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451#define module_pci_driver(__pci_driver) \
1452 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462#define builtin_pci_driver(__pci_driver) \
1463 builtin_driver(__pci_driver, pci_register_driver)
1464
1465struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1466int pci_add_dynid(struct pci_driver *drv,
1467 unsigned int vendor, unsigned int device,
1468 unsigned int subvendor, unsigned int subdevice,
1469 unsigned int class, unsigned int class_mask,
1470 unsigned long driver_data);
1471const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1472 struct pci_dev *dev);
1473int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1474 int pass);
1475
1476void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1477 void *userdata);
1478int pci_cfg_space_size(struct pci_dev *dev);
1479unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1480void pci_setup_bridge(struct pci_bus *bus);
1481resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1482 unsigned long type);
1483
1484#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1485#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1486
1487int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1488 unsigned int command_bits, u32 flags);
1489
1490
1491
1492
1493
1494
1495
1496#define PCI_IRQ_VIRTUAL (1 << 4)
1497
1498#define PCI_IRQ_ALL_TYPES \
1499 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1500
1501
1502
1503#include <linux/dmapool.h>
1504
1505#define pci_pool dma_pool
1506#define pci_pool_create(name, pdev, size, align, allocation) \
1507 dma_pool_create(name, &pdev->dev, size, align, allocation)
1508#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1509#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1510#define pci_pool_zalloc(pool, flags, handle) \
1511 dma_pool_zalloc(pool, flags, handle)
1512#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1513
1514struct msix_entry {
1515 u32 vector;
1516 u16 entry;
1517};
1518
1519#ifdef CONFIG_PCI_MSI
1520int pci_msi_vec_count(struct pci_dev *dev);
1521void pci_disable_msi(struct pci_dev *dev);
1522int pci_msix_vec_count(struct pci_dev *dev);
1523void pci_disable_msix(struct pci_dev *dev);
1524void pci_restore_msi_state(struct pci_dev *dev);
1525int pci_msi_enabled(void);
1526int pci_enable_msi(struct pci_dev *dev);
1527int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1528 int minvec, int maxvec);
1529static inline int pci_enable_msix_exact(struct pci_dev *dev,
1530 struct msix_entry *entries, int nvec)
1531{
1532 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1533 if (rc < 0)
1534 return rc;
1535 return 0;
1536}
1537int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1538 unsigned int max_vecs, unsigned int flags,
1539 struct irq_affinity *affd);
1540
1541void pci_free_irq_vectors(struct pci_dev *dev);
1542int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1543const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1544
1545#else
1546static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1547static inline void pci_disable_msi(struct pci_dev *dev) { }
1548static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1549static inline void pci_disable_msix(struct pci_dev *dev) { }
1550static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1551static inline int pci_msi_enabled(void) { return 0; }
1552static inline int pci_enable_msi(struct pci_dev *dev)
1553{ return -ENOSYS; }
1554static inline int pci_enable_msix_range(struct pci_dev *dev,
1555 struct msix_entry *entries, int minvec, int maxvec)
1556{ return -ENOSYS; }
1557static inline int pci_enable_msix_exact(struct pci_dev *dev,
1558 struct msix_entry *entries, int nvec)
1559{ return -ENOSYS; }
1560
1561static inline int
1562pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1563 unsigned int max_vecs, unsigned int flags,
1564 struct irq_affinity *aff_desc)
1565{
1566 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1567 return 1;
1568 return -ENOSPC;
1569}
1570
1571static inline void pci_free_irq_vectors(struct pci_dev *dev)
1572{
1573}
1574
1575static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1576{
1577 if (WARN_ON_ONCE(nr > 0))
1578 return -EINVAL;
1579 return dev->irq;
1580}
1581static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1582 int vec)
1583{
1584 return cpu_possible_mask;
1585}
1586#endif
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1605 struct device_node *node,
1606 const u32 *intspec,
1607 unsigned int intsize,
1608 unsigned long *out_hwirq,
1609 unsigned int *out_type)
1610{
1611 const u32 intx = intspec[0];
1612
1613 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1614 return -EINVAL;
1615
1616 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1617 return 0;
1618}
1619
1620#ifdef CONFIG_PCIEPORTBUS
1621extern bool pcie_ports_disabled;
1622extern bool pcie_ports_native;
1623#else
1624#define pcie_ports_disabled true
1625#define pcie_ports_native false
1626#endif
1627
1628#define PCIE_LINK_STATE_L0S BIT(0)
1629#define PCIE_LINK_STATE_L1 BIT(1)
1630#define PCIE_LINK_STATE_CLKPM BIT(2)
1631#define PCIE_LINK_STATE_L1_1 BIT(3)
1632#define PCIE_LINK_STATE_L1_2 BIT(4)
1633#define PCIE_LINK_STATE_L1_1_PCIPM BIT(5)
1634#define PCIE_LINK_STATE_L1_2_PCIPM BIT(6)
1635
1636#ifdef CONFIG_PCIEASPM
1637int pci_disable_link_state(struct pci_dev *pdev, int state);
1638int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
1639void pcie_no_aspm(void);
1640bool pcie_aspm_support_enabled(void);
1641bool pcie_aspm_enabled(struct pci_dev *pdev);
1642#else
1643static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
1644{ return 0; }
1645static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1646{ return 0; }
1647static inline void pcie_no_aspm(void) { }
1648static inline bool pcie_aspm_support_enabled(void) { return false; }
1649static inline bool pcie_aspm_enabled(struct pci_dev *pdev) { return false; }
1650#endif
1651
1652#ifdef CONFIG_PCIEAER
1653bool pci_aer_available(void);
1654#else
1655static inline bool pci_aer_available(void) { return false; }
1656#endif
1657
1658bool pci_ats_disabled(void);
1659
1660#ifdef CONFIG_PCIE_PTM
1661int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1662bool pcie_ptm_enabled(struct pci_dev *dev);
1663#else
1664static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1665{ return -EINVAL; }
1666static inline bool pcie_ptm_enabled(struct pci_dev *dev)
1667{ return false; }
1668#endif
1669
1670void pci_cfg_access_lock(struct pci_dev *dev);
1671bool pci_cfg_access_trylock(struct pci_dev *dev);
1672void pci_cfg_access_unlock(struct pci_dev *dev);
1673
1674int pci_dev_trylock(struct pci_dev *dev);
1675void pci_dev_unlock(struct pci_dev *dev);
1676
1677
1678
1679
1680
1681
1682#ifdef CONFIG_PCI_DOMAINS
1683extern int pci_domains_supported;
1684#else
1685enum { pci_domains_supported = 0 };
1686static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1687static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1688#endif
1689
1690
1691
1692
1693
1694
1695#ifdef CONFIG_PCI_DOMAINS_GENERIC
1696static inline int pci_domain_nr(struct pci_bus *bus)
1697{
1698 return bus->domain_nr;
1699}
1700#ifdef CONFIG_ACPI
1701int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1702#else
1703static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1704{ return 0; }
1705#endif
1706int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1707#endif
1708
1709
1710typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1711 unsigned int command_bits, u32 flags);
1712void pci_register_set_vga_state(arch_set_vga_state_t func);
1713
1714static inline int
1715pci_request_io_regions(struct pci_dev *pdev, const char *name)
1716{
1717 return pci_request_selected_regions(pdev,
1718 pci_select_bars(pdev, IORESOURCE_IO), name);
1719}
1720
1721static inline void
1722pci_release_io_regions(struct pci_dev *pdev)
1723{
1724 return pci_release_selected_regions(pdev,
1725 pci_select_bars(pdev, IORESOURCE_IO));
1726}
1727
1728static inline int
1729pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1730{
1731 return pci_request_selected_regions(pdev,
1732 pci_select_bars(pdev, IORESOURCE_MEM), name);
1733}
1734
1735static inline void
1736pci_release_mem_regions(struct pci_dev *pdev)
1737{
1738 return pci_release_selected_regions(pdev,
1739 pci_select_bars(pdev, IORESOURCE_MEM));
1740}
1741
1742#else
1743
1744static inline void pci_set_flags(int flags) { }
1745static inline void pci_add_flags(int flags) { }
1746static inline void pci_clear_flags(int flags) { }
1747static inline int pci_has_flag(int flag) { return 0; }
1748
1749
1750
1751
1752
1753#define _PCI_NOP(o, s, t) \
1754 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1755 int where, t val) \
1756 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1757
1758#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1759 _PCI_NOP(o, word, u16 x) \
1760 _PCI_NOP(o, dword, u32 x)
1761_PCI_NOP_ALL(read, *)
1762_PCI_NOP_ALL(write,)
1763
1764static inline struct pci_dev *pci_get_device(unsigned int vendor,
1765 unsigned int device,
1766 struct pci_dev *from)
1767{ return NULL; }
1768
1769static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1770 unsigned int device,
1771 unsigned int ss_vendor,
1772 unsigned int ss_device,
1773 struct pci_dev *from)
1774{ return NULL; }
1775
1776static inline struct pci_dev *pci_get_class(unsigned int class,
1777 struct pci_dev *from)
1778{ return NULL; }
1779
1780#define pci_dev_present(ids) (0)
1781#define no_pci_devices() (1)
1782#define pci_dev_put(dev) do { } while (0)
1783
1784static inline void pci_set_master(struct pci_dev *dev) { }
1785static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1786static inline void pci_disable_device(struct pci_dev *dev) { }
1787static inline int pcim_enable_device(struct pci_dev *pdev) { return -EIO; }
1788static inline int pci_assign_resource(struct pci_dev *dev, int i)
1789{ return -EBUSY; }
1790static inline int __must_check __pci_register_driver(struct pci_driver *drv,
1791 struct module *owner,
1792 const char *mod_name)
1793{ return 0; }
1794static inline int pci_register_driver(struct pci_driver *drv)
1795{ return 0; }
1796static inline void pci_unregister_driver(struct pci_driver *drv) { }
1797static inline u8 pci_find_capability(struct pci_dev *dev, int cap)
1798{ return 0; }
1799static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1800 int cap)
1801{ return 0; }
1802static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1803{ return 0; }
1804
1805static inline u64 pci_get_dsn(struct pci_dev *dev)
1806{ return 0; }
1807
1808
1809static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1810static inline void pci_restore_state(struct pci_dev *dev) { }
1811static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1812{ return 0; }
1813static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1814{ return 0; }
1815static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1816 pm_message_t state)
1817{ return PCI_D0; }
1818static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1819 int enable)
1820{ return 0; }
1821
1822static inline struct resource *pci_find_resource(struct pci_dev *dev,
1823 struct resource *res)
1824{ return NULL; }
1825static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1826{ return -EIO; }
1827static inline void pci_release_regions(struct pci_dev *dev) { }
1828
1829static inline int pci_register_io_range(struct fwnode_handle *fwnode,
1830 phys_addr_t addr, resource_size_t size)
1831{ return -EINVAL; }
1832
1833static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1834
1835static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1836{ return NULL; }
1837static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1838 unsigned int devfn)
1839{ return NULL; }
1840static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1841 unsigned int bus, unsigned int devfn)
1842{ return NULL; }
1843
1844static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1845static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1846
1847#define dev_is_pci(d) (false)
1848#define dev_is_pf(d) (false)
1849static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1850{ return false; }
1851static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1852 struct device_node *node,
1853 const u32 *intspec,
1854 unsigned int intsize,
1855 unsigned long *out_hwirq,
1856 unsigned int *out_type)
1857{ return -EINVAL; }
1858
1859static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1860 struct pci_dev *dev)
1861{ return NULL; }
1862static inline bool pci_ats_disabled(void) { return true; }
1863
1864static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1865{
1866 return -EINVAL;
1867}
1868
1869static inline int
1870pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1871 unsigned int max_vecs, unsigned int flags,
1872 struct irq_affinity *aff_desc)
1873{
1874 return -ENOSPC;
1875}
1876#endif
1877
1878static inline int
1879pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1880 unsigned int max_vecs, unsigned int flags)
1881{
1882 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1883 NULL);
1884}
1885
1886
1887
1888#include <asm/pci.h>
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1903 struct vm_area_struct *vma,
1904 enum pci_mmap_state mmap_state, int write_combine);
1905int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1906 struct vm_area_struct *vma,
1907 enum pci_mmap_state mmap_state, int write_combine);
1908
1909#ifndef arch_can_pci_mmap_wc
1910#define arch_can_pci_mmap_wc() 0
1911#endif
1912
1913#ifndef arch_can_pci_mmap_io
1914#define arch_can_pci_mmap_io() 0
1915#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1916#else
1917int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1918#endif
1919
1920#ifndef pci_root_bus_fwnode
1921#define pci_root_bus_fwnode(bus) NULL
1922#endif
1923
1924
1925
1926
1927
1928#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1929#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1930#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1931#define pci_resource_len(dev,bar) \
1932 ((pci_resource_end((dev), (bar)) == 0) ? 0 : \
1933 \
1934 (pci_resource_end((dev), (bar)) - \
1935 pci_resource_start((dev), (bar)) + 1))
1936
1937
1938
1939
1940
1941
1942static inline void *pci_get_drvdata(struct pci_dev *pdev)
1943{
1944 return dev_get_drvdata(&pdev->dev);
1945}
1946
1947static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1948{
1949 dev_set_drvdata(&pdev->dev, data);
1950}
1951
1952static inline const char *pci_name(const struct pci_dev *pdev)
1953{
1954 return dev_name(&pdev->dev);
1955}
1956
1957void pci_resource_to_user(const struct pci_dev *dev, int bar,
1958 const struct resource *rsrc,
1959 resource_size_t *start, resource_size_t *end);
1960
1961
1962
1963
1964
1965
1966
1967
1968struct pci_fixup {
1969 u16 vendor;
1970 u16 device;
1971 u32 class;
1972 unsigned int class_shift;
1973#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1974 int hook_offset;
1975#else
1976 void (*hook)(struct pci_dev *dev);
1977#endif
1978};
1979
1980enum pci_fixup_pass {
1981 pci_fixup_early,
1982 pci_fixup_header,
1983 pci_fixup_final,
1984 pci_fixup_enable,
1985 pci_fixup_resume,
1986 pci_fixup_suspend,
1987 pci_fixup_resume_early,
1988 pci_fixup_suspend_late,
1989};
1990
1991#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1992#define ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1993 class_shift, hook) \
1994 __ADDRESSABLE(hook) \
1995 asm(".section " #sec ", \"a\" \n" \
1996 ".balign 16 \n" \
1997 ".short " #vendor ", " #device " \n" \
1998 ".long " #class ", " #class_shift " \n" \
1999 ".long " #hook " - . \n" \
2000 ".previous \n");
2001
2002
2003
2004
2005
2006
2007#ifdef CONFIG_LTO_CLANG
2008#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2009 class_shift, hook, stub) \
2010 void __cficanonical stub(struct pci_dev *dev); \
2011 void __cficanonical stub(struct pci_dev *dev) \
2012 { \
2013 hook(dev); \
2014 } \
2015 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2016 class_shift, stub)
2017#else
2018#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2019 class_shift, hook, stub) \
2020 ___DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2021 class_shift, hook)
2022#endif
2023
2024#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2025 class_shift, hook) \
2026 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
2027 class_shift, hook, __UNIQUE_ID(hook))
2028#else
2029
2030#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
2031 class_shift, hook) \
2032 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
2033 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
2034 = { vendor, device, class, class_shift, hook };
2035#endif
2036
2037#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
2038 class_shift, hook) \
2039 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2040 hook, vendor, device, class, class_shift, hook)
2041#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
2042 class_shift, hook) \
2043 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2044 hook, vendor, device, class, class_shift, hook)
2045#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
2046 class_shift, hook) \
2047 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2048 hook, vendor, device, class, class_shift, hook)
2049#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
2050 class_shift, hook) \
2051 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2052 hook, vendor, device, class, class_shift, hook)
2053#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
2054 class_shift, hook) \
2055 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2056 resume##hook, vendor, device, class, class_shift, hook)
2057#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
2058 class_shift, hook) \
2059 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2060 resume_early##hook, vendor, device, class, class_shift, hook)
2061#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
2062 class_shift, hook) \
2063 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2064 suspend##hook, vendor, device, class, class_shift, hook)
2065#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
2066 class_shift, hook) \
2067 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2068 suspend_late##hook, vendor, device, class, class_shift, hook)
2069
2070#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
2071 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
2072 hook, vendor, device, PCI_ANY_ID, 0, hook)
2073#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
2074 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
2075 hook, vendor, device, PCI_ANY_ID, 0, hook)
2076#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
2077 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
2078 hook, vendor, device, PCI_ANY_ID, 0, hook)
2079#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
2080 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
2081 hook, vendor, device, PCI_ANY_ID, 0, hook)
2082#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
2083 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
2084 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
2085#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
2086 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
2087 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
2088#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
2089 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
2090 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
2091#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
2092 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
2093 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
2094
2095#ifdef CONFIG_PCI_QUIRKS
2096void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
2097#else
2098static inline void pci_fixup_device(enum pci_fixup_pass pass,
2099 struct pci_dev *dev) { }
2100#endif
2101
2102void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
2103void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
2104void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
2105int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
2106int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
2107 const char *name);
2108void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
2109
2110extern int pci_pci_problems;
2111#define PCIPCI_FAIL 1
2112#define PCIPCI_TRITON 2
2113#define PCIPCI_NATOMA 4
2114#define PCIPCI_VIAETBF 8
2115#define PCIPCI_VSFX 16
2116#define PCIPCI_ALIMAGIK 32
2117#define PCIAGP_FAIL 64
2118
2119extern unsigned long pci_cardbus_io_size;
2120extern unsigned long pci_cardbus_mem_size;
2121extern u8 pci_dfl_cache_line_size;
2122extern u8 pci_cache_line_size;
2123
2124
2125void pcibios_disable_device(struct pci_dev *dev);
2126void pcibios_set_master(struct pci_dev *dev);
2127int pcibios_set_pcie_reset_state(struct pci_dev *dev,
2128 enum pcie_reset_state state);
2129int pcibios_add_device(struct pci_dev *dev);
2130void pcibios_release_device(struct pci_dev *dev);
2131#ifdef CONFIG_PCI
2132void pcibios_penalize_isa_irq(int irq, int active);
2133#else
2134static inline void pcibios_penalize_isa_irq(int irq, int active) {}
2135#endif
2136int pcibios_alloc_irq(struct pci_dev *dev);
2137void pcibios_free_irq(struct pci_dev *dev);
2138resource_size_t pcibios_default_alignment(void);
2139
2140#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2141void __init pci_mmcfg_early_init(void);
2142void __init pci_mmcfg_late_init(void);
2143#else
2144static inline void pci_mmcfg_early_init(void) { }
2145static inline void pci_mmcfg_late_init(void) { }
2146#endif
2147
2148int pci_ext_cfg_avail(void);
2149
2150void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2151void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2152
2153#ifdef CONFIG_PCI_IOV
2154int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2155int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2156
2157int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2158void pci_disable_sriov(struct pci_dev *dev);
2159
2160int pci_iov_sysfs_link(struct pci_dev *dev, struct pci_dev *virtfn, int id);
2161int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2162void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2163int pci_num_vf(struct pci_dev *dev);
2164int pci_vfs_assigned(struct pci_dev *dev);
2165int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2166int pci_sriov_get_totalvfs(struct pci_dev *dev);
2167int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2168resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2169void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2170
2171
2172int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2173int pcibios_sriov_disable(struct pci_dev *pdev);
2174resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2175#else
2176static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2177{
2178 return -ENOSYS;
2179}
2180static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2181{
2182 return -ENOSYS;
2183}
2184static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2185{ return -ENODEV; }
2186
2187static inline int pci_iov_sysfs_link(struct pci_dev *dev,
2188 struct pci_dev *virtfn, int id)
2189{
2190 return -ENODEV;
2191}
2192static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2193{
2194 return -ENOSYS;
2195}
2196static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2197 int id) { }
2198static inline void pci_disable_sriov(struct pci_dev *dev) { }
2199static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2200static inline int pci_vfs_assigned(struct pci_dev *dev)
2201{ return 0; }
2202static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2203{ return 0; }
2204static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2205{ return 0; }
2206#define pci_sriov_configure_simple NULL
2207static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2208{ return 0; }
2209static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2210#endif
2211
2212#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2213void pci_hp_create_module_link(struct pci_slot *pci_slot);
2214void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2215#endif
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228static inline int pci_pcie_cap(struct pci_dev *dev)
2229{
2230 return dev->pcie_cap;
2231}
2232
2233
2234
2235
2236
2237
2238
2239static inline bool pci_is_pcie(struct pci_dev *dev)
2240{
2241 return pci_pcie_cap(dev);
2242}
2243
2244
2245
2246
2247
2248static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2249{
2250 return dev->pcie_flags_reg;
2251}
2252
2253
2254
2255
2256
2257static inline int pci_pcie_type(const struct pci_dev *dev)
2258{
2259 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2260}
2261
2262
2263
2264
2265
2266
2267
2268
2269static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2270{
2271 while (dev) {
2272 if (pci_is_pcie(dev) &&
2273 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2274 return dev;
2275 dev = pci_upstream_bridge(dev);
2276 }
2277
2278 return NULL;
2279}
2280
2281void pci_request_acs(void);
2282bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2283bool pci_acs_path_enabled(struct pci_dev *start,
2284 struct pci_dev *end, u16 acs_flags);
2285int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2286
2287#define PCI_VPD_LRDT 0x80
2288#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2289
2290
2291#define PCI_VPD_LTIN_ID_STRING 0x02
2292#define PCI_VPD_LTIN_RO_DATA 0x10
2293#define PCI_VPD_LTIN_RW_DATA 0x11
2294
2295#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2296#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2297#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2298
2299#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2300#define PCI_VPD_RO_KEYWORD_SERIALNO "SN"
2301#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2302#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2303#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2304
2305
2306
2307
2308
2309
2310
2311
2312void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size);
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size);
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
2335 const char *kw, unsigned int *size);
2336
2337
2338
2339
2340
2341
2342
2343
2344int pci_vpd_check_csum(const void *buf, unsigned int len);
2345
2346
2347#ifdef CONFIG_OF
2348struct device_node;
2349struct irq_domain;
2350struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2351bool pci_host_of_has_msi_map(struct device *dev);
2352
2353
2354struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2355
2356#else
2357static inline struct irq_domain *
2358pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2359static inline bool pci_host_of_has_msi_map(struct device *dev) { return false; }
2360#endif
2361
2362static inline struct device_node *
2363pci_device_to_OF_node(const struct pci_dev *pdev)
2364{
2365 return pdev ? pdev->dev.of_node : NULL;
2366}
2367
2368static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2369{
2370 return bus ? bus->dev.of_node : NULL;
2371}
2372
2373#ifdef CONFIG_ACPI
2374struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2375
2376void
2377pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2378bool pci_pr3_present(struct pci_dev *pdev);
2379#else
2380static inline struct irq_domain *
2381pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2382static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; }
2383#endif
2384
2385#ifdef CONFIG_EEH
2386static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2387{
2388 return pdev->dev.archdata.edev;
2389}
2390#endif
2391
2392void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns);
2393bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2394int pci_for_each_dma_alias(struct pci_dev *pdev,
2395 int (*fn)(struct pci_dev *pdev,
2396 u16 alias, void *data), void *data);
2397
2398
2399static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2400{
2401 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2402}
2403static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2404{
2405 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2406}
2407static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2408{
2409 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2410}
2411
2412
2413
2414
2415
2416
2417
2418static inline bool pci_ari_enabled(struct pci_bus *bus)
2419{
2420 return bus->self && bus->self->ari_enabled;
2421}
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2432{
2433 struct pci_dev *parent = pdev;
2434
2435 if (pdev->is_thunderbolt)
2436 return true;
2437
2438 while ((parent = pci_upstream_bridge(parent)))
2439 if (parent->is_thunderbolt)
2440 return true;
2441
2442 return false;
2443}
2444
2445#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2446void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2447#endif
2448
2449
2450#include <linux/pci-dma-compat.h>
2451
2452#define pci_printk(level, pdev, fmt, arg...) \
2453 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2454
2455#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2456#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2457#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2458#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2459#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2460#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2461#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2462#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2463
2464#define pci_notice_ratelimited(pdev, fmt, arg...) \
2465 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2466
2467#define pci_info_ratelimited(pdev, fmt, arg...) \
2468 dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
2469
2470#define pci_WARN(pdev, condition, fmt, arg...) \
2471 WARN(condition, "%s %s: " fmt, \
2472 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2473
2474#define pci_WARN_ONCE(pdev, condition, fmt, arg...) \
2475 WARN_ONCE(condition, "%s %s: " fmt, \
2476 dev_driver_string(&(pdev)->dev), pci_name(pdev), ##arg)
2477
2478#endif
2479