1
2
3
4
5
6config ARC
7 def_bool y
8 select ARC_TIMERS
9 select ARCH_HAS_CACHE_LINE_SIZE
10 select ARCH_HAS_DEBUG_VM_PGTABLE
11 select ARCH_HAS_DMA_PREP_COHERENT
12 select ARCH_HAS_PTE_SPECIAL
13 select ARCH_HAS_SETUP_DMA_OPS
14 select ARCH_HAS_SYNC_DMA_FOR_CPU
15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
17 select ARCH_32BIT_OFF_T
18 select BUILDTIME_TABLE_SORT
19 select CLONE_BACKWARDS
20 select COMMON_CLK
21 select DMA_DIRECT_REMAP
22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
23 select GENERIC_FIND_FIRST_BIT
24
25 select GENERIC_IRQ_SHOW
26 select GENERIC_PCI_IOMAP
27 select GENERIC_PENDING_IRQ if SMP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select HAVE_ARCH_KGDB
31 select HAVE_ARCH_TRACEHOOK
32 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
33 select HAVE_DEBUG_STACKOVERFLOW
34 select HAVE_DEBUG_KMEMLEAK
35 select HAVE_FUTEX_CMPXCHG if FUTEX
36 select HAVE_IOREMAP_PROT
37 select HAVE_KERNEL_GZIP
38 select HAVE_KERNEL_LZMA
39 select HAVE_KPROBES
40 select HAVE_KRETPROBES
41 select HAVE_MOD_ARCH_SPECIFIC
42 select HAVE_PERF_EVENTS
43 select IRQ_DOMAIN
44 select MODULES_USE_ELF_RELA
45 select OF
46 select OF_EARLY_FLATTREE
47 select PCI_SYSCALL if PCI
48 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
49 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
50 select SET_FS
51 select TRACE_IRQFLAGS_SUPPORT
52
53config LOCKDEP_SUPPORT
54 def_bool y
55
56config SCHED_OMIT_FRAME_POINTER
57 def_bool y
58
59config GENERIC_CSUM
60 def_bool y
61
62config ARCH_FLATMEM_ENABLE
63 def_bool y
64
65config MMU
66 def_bool y
67
68config NO_IOPORT_MAP
69 def_bool y
70
71config GENERIC_CALIBRATE_DELAY
72 def_bool y
73
74config GENERIC_HWEIGHT
75 def_bool y
76
77config STACKTRACE_SUPPORT
78 def_bool y
79 select STACKTRACE
80
81menu "ARC Architecture Configuration"
82
83menu "ARC Platform/SoC/Board"
84
85source "arch/arc/plat-tb10x/Kconfig"
86source "arch/arc/plat-axs10x/Kconfig"
87source "arch/arc/plat-hsdk/Kconfig"
88
89endmenu
90
91choice
92 prompt "ARC Instruction Set"
93 default ISA_ARCV2
94
95config ISA_ARCOMPACT
96 bool "ARCompact ISA"
97 select CPU_NO_EFFICIENT_FFS
98 help
99 The original ARC ISA of ARC600/700 cores
100
101config ISA_ARCV2
102 bool "ARC ISA v2"
103 select ARC_TIMERS_64BIT
104 help
105 ISA for the Next Generation ARC-HS cores
106
107endchoice
108
109menu "ARC CPU Configuration"
110
111choice
112 prompt "ARC Core"
113 default ARC_CPU_770 if ISA_ARCOMPACT
114 default ARC_CPU_HS if ISA_ARCV2
115
116config ARC_CPU_770
117 bool "ARC770"
118 depends on ISA_ARCOMPACT
119 select ARC_HAS_SWAPE
120 help
121 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
122 This core has a bunch of cool new features:
123 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
124 Shared Address Spaces (for sharing TLB entries in MMU)
125 -Caches: New Prog Model, Region Flush
126 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
127
128config ARC_CPU_HS
129 bool "ARC-HS"
130 depends on ISA_ARCV2
131 help
132 Support for ARC HS38x Cores based on ARCv2 ISA
133 The notable features are:
134 - SMP configurations of up to 4 cores with coherency
135 - Optional L2 Cache and IO-Coherency
136 - Revised Interrupt Architecture (multiple priorites, reg banks,
137 auto stack switch, auto regfile save/restore)
138 - MMUv4 (PIPT dcache, Huge Pages)
139 - Instructions for
140 * 64bit load/store: LDD, STD
141 * Hardware assisted divide/remainder: DIV, REM
142 * Function prologue/epilogue: ENTER_S, LEAVE_S
143 * IRQ enable/disable: CLRI, SETI
144 * pop count: FFS, FLS
145 * SETcc, BMSKN, XBFU...
146
147endchoice
148
149config ARC_TUNE_MCPU
150 string "Override default -mcpu compiler flag"
151 default ""
152 help
153 Override default -mcpu=xxx compiler flag (which is set depending on
154 the ISA version) with the specified value.
155 NOTE: If specified flag isn't supported by current compiler the
156 ISA default value will be used as a fallback.
157
158config CPU_BIG_ENDIAN
159 bool "Enable Big Endian Mode"
160 help
161 Build kernel for Big Endian Mode of ARC CPU
162
163config SMP
164 bool "Symmetric Multi-Processing"
165 select ARC_MCIP if ISA_ARCV2
166 help
167 This enables support for systems with more than one CPU.
168
169if SMP
170
171config NR_CPUS
172 int "Maximum number of CPUs (2-4096)"
173 range 2 4096
174 default "4"
175
176config ARC_SMP_HALT_ON_RESET
177 bool "Enable Halt-on-reset boot mode"
178 help
179 In SMP configuration cores can be configured as Halt-on-reset
180 or they could all start at same time. For Halt-on-reset, non
181 masters are parked until Master kicks them so they can start off
182 at designated entry point. For other case, all jump to common
183 entry point and spin wait for Master's signal.
184
185endif
186
187config ARC_MCIP
188 bool "ARConnect Multicore IP (MCIP) Support "
189 depends on ISA_ARCV2
190 default y if SMP
191 help
192 This IP block enables SMP in ARC-HS38 cores.
193 It provides for cross-core interrupts, multi-core debug
194 hardware semaphores, shared memory,....
195
196menuconfig ARC_CACHE
197 bool "Enable Cache Support"
198 default y
199
200if ARC_CACHE
201
202config ARC_CACHE_LINE_SHIFT
203 int "Cache Line Length (as power of 2)"
204 range 5 7
205 default "6"
206 help
207 Starting with ARC700 4.9, Cache line length is configurable,
208 This option specifies "N", with Line-len = 2 power N
209 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
210 Linux only supports same line lengths for I and D caches.
211
212config ARC_HAS_ICACHE
213 bool "Use Instruction Cache"
214 default y
215
216config ARC_HAS_DCACHE
217 bool "Use Data Cache"
218 default y
219
220config ARC_CACHE_PAGES
221 bool "Per Page Cache Control"
222 default y
223 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
224 help
225 This can be used to over-ride the global I/D Cache Enable on a
226 per-page basis (but only for pages accessed via MMU such as
227 Kernel Virtual address or User Virtual Address)
228 TLB entries have a per-page Cache Enable Bit.
229 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
230 Global DISABLE + Per Page ENABLE won't work
231
232config ARC_CACHE_VIPT_ALIASING
233 bool "Support VIPT Aliasing D$"
234 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
235
236endif
237
238config ARC_HAS_ICCM
239 bool "Use ICCM"
240 help
241 Single Cycle RAMS to store Fast Path Code
242
243config ARC_ICCM_SZ
244 int "ICCM Size in KB"
245 default "64"
246 depends on ARC_HAS_ICCM
247
248config ARC_HAS_DCCM
249 bool "Use DCCM"
250 help
251 Single Cycle RAMS to store Fast Path Data
252
253config ARC_DCCM_SZ
254 int "DCCM Size in KB"
255 default "64"
256 depends on ARC_HAS_DCCM
257
258config ARC_DCCM_BASE
259 hex "DCCM map address"
260 default "0xA0000000"
261 depends on ARC_HAS_DCCM
262
263choice
264 prompt "MMU Version"
265 default ARC_MMU_V3 if ISA_ARCOMPACT
266 default ARC_MMU_V4 if ISA_ARCV2
267
268config ARC_MMU_V3
269 bool "MMU v3"
270 depends on ISA_ARCOMPACT
271 help
272 Introduced with ARC700 4.10: New Features
273 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
274 Shared Address Spaces (SASID)
275
276config ARC_MMU_V4
277 bool "MMU v4"
278 depends on ISA_ARCV2
279
280endchoice
281
282
283choice
284 prompt "MMU Page Size"
285 default ARC_PAGE_SIZE_8K
286
287config ARC_PAGE_SIZE_8K
288 bool "8KB"
289 help
290 Choose between 8k vs 16k
291
292config ARC_PAGE_SIZE_16K
293 bool "16KB"
294
295config ARC_PAGE_SIZE_4K
296 bool "4KB"
297 depends on ARC_MMU_V3 || ARC_MMU_V4
298
299endchoice
300
301choice
302 prompt "MMU Super Page Size"
303 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
304 default ARC_HUGEPAGE_2M
305
306config ARC_HUGEPAGE_2M
307 bool "2MB"
308
309config ARC_HUGEPAGE_16M
310 bool "16MB"
311
312endchoice
313
314config PGTABLE_LEVELS
315 int "Number of Page table levels"
316 default 2
317
318config ARC_COMPACT_IRQ_LEVELS
319 depends on ISA_ARCOMPACT
320 bool "Setup Timer IRQ as high Priority"
321
322 depends on !SMP
323
324config ARC_FPU_SAVE_RESTORE
325 bool "Enable FPU state persistence across context switch"
326 help
327 ARCompact FPU has internal registers to assist with Double precision
328 Floating Point operations. There are control and stauts registers
329 for floating point exceptions and rounding modes. These are
330 preserved across task context switch when enabled.
331
332config ARC_CANT_LLSC
333 def_bool n
334
335config ARC_HAS_LLSC
336 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
337 default y
338 depends on !ARC_CANT_LLSC
339
340config ARC_HAS_SWAPE
341 bool "Insn: SWAPE (endian-swap)"
342 default y
343
344if ISA_ARCV2
345
346config ARC_USE_UNALIGNED_MEM_ACCESS
347 bool "Enable unaligned access in HW"
348 default y
349 select HAVE_EFFICIENT_UNALIGNED_ACCESS
350 help
351 The ARC HS architecture supports unaligned memory access
352 which is disabled by default. Enable unaligned access in
353 hardware and use software to use it
354
355config ARC_HAS_LL64
356 bool "Insn: 64bit LDD/STD"
357 help
358 Enable gcc to generate 64-bit load/store instructions
359 ISA mandates even/odd registers to allow encoding of two
360 dest operands with 2 possible source operands.
361 default y
362
363config ARC_HAS_DIV_REM
364 bool "Insn: div, divu, rem, remu"
365 default y
366
367config ARC_HAS_ACCL_REGS
368 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
369 default y
370 help
371 Depending on the configuration, CPU can contain accumulator reg-pair
372 (also referred to as r58:r59). These can also be used by gcc as GPR so
373 kernel needs to save/restore per process
374
375config ARC_DSP_HANDLED
376 def_bool n
377
378config ARC_DSP_SAVE_RESTORE_REGS
379 def_bool n
380
381choice
382 prompt "DSP support"
383 default ARC_DSP_NONE
384 help
385 Depending on the configuration, CPU can contain DSP registers
386 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
387 Below are options describing how to handle these registers in
388 interrupt entry / exit and in context switch.
389
390config ARC_DSP_NONE
391 bool "No DSP extension presence in HW"
392 help
393 No DSP extension presence in HW
394
395config ARC_DSP_KERNEL
396 bool "DSP extension in HW, no support for userspace"
397 select ARC_HAS_ACCL_REGS
398 select ARC_DSP_HANDLED
399 help
400 DSP extension presence in HW, no support for DSP-enabled userspace
401 applications. We don't save / restore DSP registers and only do
402 some minimal preparations so userspace won't be able to break kernel
403
404config ARC_DSP_USERSPACE
405 bool "Support DSP for userspace apps"
406 select ARC_HAS_ACCL_REGS
407 select ARC_DSP_HANDLED
408 select ARC_DSP_SAVE_RESTORE_REGS
409 help
410 DSP extension presence in HW, support save / restore DSP registers to
411 run DSP-enabled userspace applications
412
413config ARC_DSP_AGU_USERSPACE
414 bool "Support DSP with AGU for userspace apps"
415 select ARC_HAS_ACCL_REGS
416 select ARC_DSP_HANDLED
417 select ARC_DSP_SAVE_RESTORE_REGS
418 help
419 DSP and AGU extensions presence in HW, support save / restore DSP
420 and AGU registers to run DSP-enabled userspace applications
421endchoice
422
423config ARC_IRQ_NO_AUTOSAVE
424 bool "Disable hardware autosave regfile on interrupts"
425 default n
426 help
427 On HS cores, taken interrupt auto saves the regfile on stack.
428 This is programmable and can be optionally disabled in which case
429 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
430
431config ARC_LPB_DISABLE
432 bool "Disable loop buffer (LPB)"
433 help
434 On HS cores, loop buffer (LPB) is programmable in runtime and can
435 be optionally disabled.
436
437endif
438
439endmenu
440
441config LINUX_LINK_BASE
442 hex "Kernel link address"
443 default "0x80000000"
444 help
445 ARC700 divides the 32 bit phy address space into two equal halves
446 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
447 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
448 Typically Linux kernel is linked at the start of untransalted addr,
449 hence the default value of 0x8zs.
450 However some customers have peripherals mapped at this addr, so
451 Linux needs to be scooted a bit.
452 If you don't know what the above means, leave this setting alone.
453 This needs to match memory start address specified in Device Tree
454
455config LINUX_RAM_BASE
456 hex "RAM base address"
457 default LINUX_LINK_BASE
458 help
459 By default Linux is linked at base of RAM. However in some special
460 cases (such as HSDK), Linux can't be linked at start of DDR, hence
461 this option.
462
463config HIGHMEM
464 bool "High Memory Support"
465 select HAVE_ARCH_PFN_VALID
466 select KMAP_LOCAL
467 help
468 With ARC 2G:2G address split, only upper 2G is directly addressable by
469 kernel. Enable this to potentially allow access to rest of 2G and PAE
470 in future
471
472config ARC_HAS_PAE40
473 bool "Support for the 40-bit Physical Address Extension"
474 depends on ISA_ARCV2
475 select HIGHMEM
476 select PHYS_ADDR_T_64BIT
477 help
478 Enable access to physical memory beyond 4G, only supported on
479 ARC cores with 40 bit Physical Addressing support
480
481config ARC_KVADDR_SIZE
482 int "Kernel Virtual Address Space size (MB)"
483 range 0 512
484 default "256"
485 help
486 The kernel address space is carved out of 256MB of translated address
487 space for catering to vmalloc, modules, pkmap, fixmap. This however may
488 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
489 this to be stretched to 512 MB (by extending into the reserved
490 kernel-user gutter)
491
492config ARC_CURR_IN_REG
493 bool "Dedicate Register r25 for current_task pointer"
494 default y
495 help
496 This reserved Register R25 to point to Current Task in
497 kernel mode. This saves memory access for each such access
498
499
500config ARC_EMUL_UNALIGNED
501 bool "Emulate unaligned memory access (userspace only)"
502 select SYSCTL_ARCH_UNALIGN_NO_WARN
503 select SYSCTL_ARCH_UNALIGN_ALLOW
504 depends on ISA_ARCOMPACT
505 help
506 This enables misaligned 16 & 32 bit memory access from user space.
507 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
508 potential bugs in code
509
510config HZ
511 int "Timer Frequency"
512 default 100
513
514config ARC_METAWARE_HLINK
515 bool "Support for Metaware debugger assisted Host access"
516 help
517 This options allows a Linux userland apps to directly access
518 host file system (open/creat/read/write etc) with help from
519 Metaware Debugger. This can come in handy for Linux-host communication
520 when there is no real usable peripheral such as EMAC.
521
522menuconfig ARC_DBG
523 bool "ARC debugging"
524 default y
525
526if ARC_DBG
527
528config ARC_DW2_UNWIND
529 bool "Enable DWARF specific kernel stack unwind"
530 default y
531 select KALLSYMS
532 help
533 Compiles the kernel with DWARF unwind information and can be used
534 to get stack backtraces.
535
536 If you say Y here the resulting kernel image will be slightly larger
537 but not slower, and it will give very useful debugging information.
538 If you don't debug the kernel, you can say N, but we may not be able
539 to solve problems without frame unwind information
540
541config ARC_DBG_JUMP_LABEL
542 bool "Paranoid checks in Static Keys (jump labels) code"
543 depends on JUMP_LABEL
544 default y if STATIC_KEYS_SELFTEST
545 help
546 Enable paranoid checks and self-test of both ARC-specific and generic
547 part of static keys (jump labels) related code.
548endif
549
550config ARC_BUILTIN_DTB_NAME
551 string "Built in DTB"
552 help
553 Set the name of the DTB to embed in the vmlinux binary
554 Leaving it blank selects the minimal "skeleton" dtb
555
556endmenu
557
558config FORCE_MAX_ZONEORDER
559 int "Maximum zone order"
560 default "12" if ARC_HUGEPAGE_16M
561 default "11"
562
563source "kernel/power/Kconfig"
564