1/* 2 * AURORA shared L2 cache controller support 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Yehuda Yitschak <yehuday@marvell.com> 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 8 * 9 * This file is licensed under the terms of the GNU General Public 10 * License version 2. This program is licensed "as is" without any 11 * warranty of any kind, whether express or implied. 12 */ 13 14#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H 15#define __ASM_ARM_HARDWARE_AURORA_L2_H 16 17#define AURORA_SYNC_REG 0x700 18#define AURORA_RANGE_BASE_ADDR_REG 0x720 19#define AURORA_FLUSH_PHY_ADDR_REG 0x7f0 20#define AURORA_INVAL_RANGE_REG 0x774 21#define AURORA_CLEAN_RANGE_REG 0x7b4 22#define AURORA_FLUSH_RANGE_REG 0x7f4 23 24#define AURORA_ACR_REPLACEMENT_OFFSET 27 25#define AURORA_ACR_REPLACEMENT_MASK \ 26 (0x3 << AURORA_ACR_REPLACEMENT_OFFSET) 27#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR \ 28 (0 << AURORA_ACR_REPLACEMENT_OFFSET) 29#define AURORA_ACR_REPLACEMENT_TYPE_LFSR \ 30 (1 << AURORA_ACR_REPLACEMENT_OFFSET) 31#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \ 32 (3 << AURORA_ACR_REPLACEMENT_OFFSET) 33 34#define AURORA_ACR_PARITY_EN (1 << 21) 35#define AURORA_ACR_ECC_EN (1 << 20) 36 37#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0 38#define AURORA_ACR_FORCE_WRITE_POLICY_MASK \ 39 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 40#define AURORA_ACR_FORCE_WRITE_POLICY_DIS \ 41 (0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 42#define AURORA_ACR_FORCE_WRITE_BACK_POLICY \ 43 (1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 44#define AURORA_ACR_FORCE_WRITE_THRO_POLICY \ 45 (2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET) 46 47#define AURORA_ERR_CNT_REG 0x600 48#define AURORA_ERR_ATTR_CAP_REG 0x608 49#define AURORA_ERR_ADDR_CAP_REG 0x60c 50#define AURORA_ERR_WAY_CAP_REG 0x610 51#define AURORA_ERR_INJECT_CTL_REG 0x614 52#define AURORA_ERR_INJECT_MASK_REG 0x618 53 54#define AURORA_ERR_CNT_CLR_OFFSET 31 55#define AURORA_ERR_CNT_CLR \ 56 (0x1 << AURORA_ERR_CNT_CLR_OFFSET) 57#define AURORA_ERR_CNT_UE_OFFSET 16 58#define AURORA_ERR_CNT_UE_MASK \ 59 (0x7fff << AURORA_ERR_CNT_UE_OFFSET) 60#define AURORA_ERR_CNT_CE_OFFSET 0 61#define AURORA_ERR_CNT_CE_MASK \ 62 (0xffff << AURORA_ERR_CNT_CE_OFFSET) 63 64#define AURORA_ERR_ATTR_SRC_OFF 16 65#define AURORA_ERR_ATTR_SRC_MSK \ 66 (0x7 << AURORA_ERR_ATTR_SRC_OFF) 67#define AURORA_ERR_ATTR_TXN_OFF 12 68#define AURORA_ERR_ATTR_TXN_MSK \ 69 (0xf << AURORA_ERR_ATTR_TXN_OFF) 70#define AURORA_ERR_ATTR_ERR_OFF 8 71#define AURORA_ERR_ATTR_ERR_MSK \ 72 (0x3 << AURORA_ERR_ATTR_ERR_OFF) 73#define AURORA_ERR_ATTR_CAP_VALID_OFF 0 74#define AURORA_ERR_ATTR_CAP_VALID \ 75 (0x1 << AURORA_ERR_ATTR_CAP_VALID_OFF) 76 77#define AURORA_ERR_ADDR_CAP_ADDR_MASK 0xffffffe0 78 79#define AURORA_ERR_WAY_IDX_OFF 8 80#define AURORA_ERR_WAY_IDX_MSK \ 81 (0xfff << AURORA_ERR_WAY_IDX_OFF) 82#define AURORA_ERR_WAY_CAP_WAY_OFFSET 1 83#define AURORA_ERR_WAY_CAP_WAY_MASK \ 84 (0xf << AURORA_ERR_WAY_CAP_WAY_OFFSET) 85 86#define AURORA_ERR_INJECT_CTL_ADDR_MASK 0xfffffff0 87#define AURORA_ERR_ATTR_TXN_OFF 12 88#define AURORA_ERR_INJECT_CTL_EN_MASK 0x3 89#define AURORA_ERR_INJECT_CTL_EN_PARITY 0x2 90#define AURORA_ERR_INJECT_CTL_EN_ECC 0x1 91 92#define AURORA_MAX_RANGE_SIZE 1024 93 94#define AURORA_WAY_SIZE_SHIFT 2 95 96#define AURORA_CTRL_FW 0x100 97 98/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make 99 * the distinction between a number coming from hardware and a number 100 * coming from the device tree */ 101#define AURORA_CACHE_ID 0x100 102 103#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */ 104