LXR linux/arch/arm64/kernel/cpu

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Contains CPU specific errata definitions
   4 *
   5 * Copyright (C) 2014 ARM Ltd.
   6 */
   7
   8#include <linux/arm-smccc.h>
   9#include <linux/types.h>
  10#include <linux/cpu.h>
  11#include <asm/cpu.h>
  12#include <asm/cputype.h>
  13#include <asm/cpufeature.h>
  14#include <asm/kvm_asm.h>
  15#include <asm/smp_plat.h>
  16
  17static bool __maybe_unused
  18is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
  19{
  20        const struct arm64_midr_revidr *fix;
  21        u32 midr = read_cpuid_id(), revidr;
  22
  23        WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  24        if (!is_midr_in_range(midr, &entry->midr_range))
  25                return false;
  26
  27        midr &= MIDR_REVISION_MASK | MIDR_VARIANT_MASK;
  28        revidr = read_cpuid(REVIDR_EL1);
  29        for (fix = entry->fixed_revs; fix && fix->revidr_mask; fix++)
  30                if (midr == fix->midr_rv && (revidr & fix->revidr_mask))
  31                        return false;
  32
  33        return true;
  34}
  35
  36static bool __maybe_unused
  37is_affected_midr_range_list(const struct arm64_cpu_capabilities *entry,
  38                            int scope)
  39{
  40        WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  41        return is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list);
  42}
  43
  44static bool __maybe_unused
  45is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
  46{
  47        u32 model;
  48
  49        WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  50
  51        model = read_cpuid_id();
  52        model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
  53                 MIDR_ARCHITECTURE_MASK;
  54
  55        return model == entry->midr_range.model;
  56}
  57
  58static bool
  59has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry,
  60                          int scope)
  61{
  62        u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
  63        u64 sys = arm64_ftr_reg_ctrel0.sys_val & mask;
  64        u64 ctr_raw, ctr_real;
  65
  66        WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  67
  68        /*
  69         * We want to make sure that all the CPUs in the system expose
  70         * a consistent CTR_EL0 to make sure that applications behaves
  71         * correctly with migration.
  72         *
  73         * If a CPU has CTR_EL0.IDC but does not advertise it via CTR_EL0 :
  74         *
  75         * 1) It is safe if the system doesn't support IDC, as CPU anyway
  76         *    reports IDC = 0, consistent with the rest.
  77         *
  78         * 2) If the system has IDC, it is still safe as we trap CTR_EL0
  79         *    access on this CPU via the ARM64_HAS_CACHE_IDC capability.
  80         *
  81         * So, we need to make sure either the raw CTR_EL0 or the effective
  82         * CTR_EL0 matches the system's copy to allow a secondary CPU to boot.
  83         */
  84        ctr_raw = read_cpuid_cachetype() & mask;
  85        ctr_real = read_cpuid_effective_cachetype() & mask;
  86
  87        return (ctr_real != sys) && (ctr_raw != sys);
  88}
  89
  90static void
  91cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap)
  92{
  93        u64 mask = arm64_ftr_reg_ctrel0.strict_mask;
  94        bool enable_uct_trap = false;
  95
  96        /* Trap CTR_EL0 access on this CPU, only if it has a mismatch */
  97        if ((read_cpuid_cachetype() & mask) !=
  98            (arm64_ftr_reg_ctrel0.sys_val & mask))
  99                enable_uct_trap = true;
 100
 101        /* ... or if the system is affected by an erratum */
 102        if (cap->capability == ARM64_WORKAROUND_1542419)
 103                enable_uct_trap = true;
 104
 105        if (enable_uct_trap)
 106                sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 107}
 108
 109#ifdef CONFIG_ARM64_ERRATUM_1463225
 110static bool
 111has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
 112                               int scope)
 113{
 114        return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
 115}
 116#endif
 117
 118static void __maybe_unused
 119cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused)
 120{
 121        sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCI, 0);
 122}
 123
 124#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)       \
 125        .matches = is_affected_midr_range,                      \
 126        .midr_range = MIDR_RANGE(model, v_min, r_min, v_max, r_max)
 127
 128#define CAP_MIDR_ALL_VERSIONS(model)                                    \
 129        .matches = is_affected_midr_range,                              \
 130        .midr_range = MIDR_ALL_VERSIONS(model)
 131
 132#define MIDR_FIXED(rev, revidr_mask) \
 133        .fixed_revs = (struct arm64_midr_revidr[]){{ (rev), (revidr_mask) }, {}}
 134
 135#define ERRATA_MIDR_RANGE(model, v_min, r_min, v_max, r_max)            \
 136        .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                         \
 137        CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max)
 138
 139#define CAP_MIDR_RANGE_LIST(list)                               \
 140        .matches = is_affected_midr_range_list,                 \
 141        .midr_range_list = list
 142
 143/* Errata affecting a range of revisions of  given model variant */
 144#define ERRATA_MIDR_REV_RANGE(m, var, r_min, r_max)      \
 145        ERRATA_MIDR_RANGE(m, var, r_min, var, r_max)
 146
 147/* Errata affecting a single variant/revision of a model */
 148#define ERRATA_MIDR_REV(model, var, rev)        \
 149        ERRATA_MIDR_RANGE(model, var, rev, var, rev)
 150
 151/* Errata affecting all variants/revisions of a given a model */
 152#define ERRATA_MIDR_ALL_VERSIONS(model)                         \
 153        .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                 \
 154        CAP_MIDR_ALL_VERSIONS(model)
 155
 156/* Errata affecting a list of midr ranges, with same work around */
 157#define ERRATA_MIDR_RANGE_LIST(midr_list)                       \
 158        .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,                 \
 159        CAP_MIDR_RANGE_LIST(midr_list)
 160
 161static const __maybe_unused struct midr_range tx2_family_cpus[] = {
 162        MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 163        MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 164        {},
 165};
 166
 167static bool __maybe_unused
 168needs_tx2_tvm_workaround(const struct arm64_cpu_capabilities *entry,
 169                         int scope)
 170{
 171        int i;
 172
 173        if (!is_affected_midr_range_list(entry, scope) ||
 174            !is_hyp_mode_available())
 175                return false;
 176
 177        for_each_possible_cpu(i) {
 178                if (MPIDR_AFFINITY_LEVEL(cpu_logical_map(i), 0) != 0)
 179                        return true;
 180        }
 181
 182        return false;
 183}
 184
 185static bool __maybe_unused
 186has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry,
 187                                int scope)
 188{
 189        u32 midr = read_cpuid_id();
 190        bool has_dic = read_cpuid_cachetype() & BIT(CTR_DIC_SHIFT);
 191        const struct midr_range range = MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1);
 192
 193        WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
 194        return is_midr_in_range(midr, &range) && has_dic;
 195}
 196
 197#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
 198static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
 199#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
 200        {
 201                ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0)
 202        },
 203        {
 204                .midr_range.model = MIDR_QCOM_KRYO,
 205                .matches = is_kryo_midr,
 206        },
 207#endif
 208#ifdef CONFIG_ARM64_ERRATUM_1286807
 209        {
 210                ERRATA_MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 0),
 211        },
 212#endif
 213        {},
 214};
 215#endif
 216
 217#ifdef CONFIG_CAVIUM_ERRATUM_27456
 218const struct midr_range cavium_erratum_27456_cpus[] = {
 219        /* Cavium ThunderX, T88 pass 1.x - 2.1 */
 220        MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 1),
 221        /* Cavium ThunderX, T81 pass 1.0 */
 222        MIDR_REV(MIDR_THUNDERX_81XX, 0, 0),
 223        {},
 224};
 225#endif
 226
 227#ifdef CONFIG_CAVIUM_ERRATUM_30115
 228static const struct midr_range cavium_erratum_30115_cpus[] = {
 229        /* Cavium ThunderX, T88 pass 1.x - 2.2 */
 230        MIDR_RANGE(MIDR_THUNDERX, 0, 0, 1, 2),
 231        /* Cavium ThunderX, T81 pass 1.0 - 1.2 */
 232        MIDR_REV_RANGE(MIDR_THUNDERX_81XX, 0, 0, 2),
 233        /* Cavium ThunderX, T83 pass 1.0 */
 234        MIDR_REV(MIDR_THUNDERX_83XX, 0, 0),
 235        {},
 236};
 237#endif
 238
 239#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
 240static const struct arm64_cpu_capabilities qcom_erratum_1003_list[] = {
 241        {
 242                ERRATA_MIDR_REV(MIDR_QCOM_FALKOR_V1, 0, 0),
 243        },
 244        {
 245                .midr_range.model = MIDR_QCOM_KRYO,
 246                .matches = is_kryo_midr,
 247        },
 248        {},
 249};
 250#endif
 251
 252#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
 253static const struct midr_range workaround_clean_cache[] = {
 254#if     defined(CONFIG_ARM64_ERRATUM_826319) || \
 255        defined(CONFIG_ARM64_ERRATUM_827319) || \
 256        defined(CONFIG_ARM64_ERRATUM_824069)
 257        /* Cortex-A53 r0p[012]: ARM errata 826319, 827319, 824069 */
 258        MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 2),
 259#endif
 260#ifdef  CONFIG_ARM64_ERRATUM_819472
 261        /* Cortex-A53 r0p[01] : ARM errata 819472 */
 262        MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 1),
 263#endif
 264        {},
 265};
 266#endif
 267
 268#ifdef CONFIG_ARM64_ERRATUM_1418040
 269/*
 270 * - 1188873 affects r0p0 to r2p0
 271 * - 1418040 affects r0p0 to r3p1
 272 */
 273static const struct midr_range erratum_1418040_list[] = {
 274        /* Cortex-A76 r0p0 to r3p1 */
 275        MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
 276        /* Neoverse-N1 r0p0 to r3p1 */
 277        MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
 278        /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
 279        MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
 280        {},
 281};
 282#endif
 283
 284#ifdef CONFIG_ARM64_ERRATUM_845719
 285static const struct midr_range erratum_845719_list[] = {
 286        /* Cortex-A53 r0p[01234] */
 287        MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
 288        /* Brahma-B53 r0p[0] */
 289        MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
 290        /* Kryo2XX Silver rAp4 */
 291        MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),
 292        {},
 293};
 294#endif
 295
 296#ifdef CONFIG_ARM64_ERRATUM_843419
 297static const struct arm64_cpu_capabilities erratum_843419_list[] = {
 298        {
 299                /* Cortex-A53 r0p[01234] */
 300                .matches = is_affected_midr_range,
 301                ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),
 302                MIDR_FIXED(0x4, BIT(8)),
 303        },
 304        {
 305                /* Brahma-B53 r0p[0] */
 306                .matches = is_affected_midr_range,
 307                ERRATA_MIDR_REV(MIDR_BRAHMA_B53, 0, 0),
 308        },
 309        {},
 310};
 311#endif
 312
 313#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
 314static const struct midr_range erratum_speculative_at_list[] = {
 315#ifdef CONFIG_ARM64_ERRATUM_1165522
 316        /* Cortex A76 r0p0 to r2p0 */
 317        MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),
 318#endif
 319#ifdef CONFIG_ARM64_ERRATUM_1319367
 320        MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 321        MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 322#endif
 323#ifdef CONFIG_ARM64_ERRATUM_1530923
 324        /* Cortex A55 r0p0 to r2p0 */
 325        MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
 326        /* Kryo4xx Silver (rdpe => r1p0) */
 327        MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
 328#endif
 329        {},
 330};
 331#endif
 332
 333#ifdef CONFIG_ARM64_ERRATUM_1463225
 334static const struct midr_range erratum_1463225[] = {
 335        /* Cortex-A76 r0p0 - r3p1 */
 336        MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
 337        /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
 338        MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
 339        {},
 340};
 341#endif
 342
 343#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
 344static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {
 345#ifdef CONFIG_ARM64_ERRATUM_2139208
 346        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
 347#endif
 348#ifdef CONFIG_ARM64_ERRATUM_2119858
 349        MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
 350#endif
 351        {},
 352};
 353#endif  /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */
 354
 355#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
 356static const struct midr_range tsb_flush_fail_cpus[] = {
 357#ifdef CONFIG_ARM64_ERRATUM_2067961
 358        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
 359#endif
 360#ifdef CONFIG_ARM64_ERRATUM_2054223
 361        MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
 362#endif
 363        {},
 364};
 365#endif  /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */
 366
 367#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
 368static struct midr_range trbe_write_out_of_range_cpus[] = {
 369#ifdef CONFIG_ARM64_ERRATUM_2253138
 370        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
 371#endif
 372#ifdef CONFIG_ARM64_ERRATUM_2224489
 373        MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
 374#endif
 375        {},
 376};
 377#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */
 378
 379const struct arm64_cpu_capabilities arm64_errata[] = {
 380#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
 381        {
 382                .desc = "ARM errata 826319, 827319, 824069, or 819472",
 383                .capability = ARM64_WORKAROUND_CLEAN_CACHE,
 384                ERRATA_MIDR_RANGE_LIST(workaround_clean_cache),
 385                .cpu_enable = cpu_enable_cache_maint_trap,
 386        },
 387#endif
 388#ifdef CONFIG_ARM64_ERRATUM_832075
 389        {
 390        /* Cortex-A57 r0p0 - r1p2 */
 391                .desc = "ARM erratum 832075",
 392                .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
 393                ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
 394                                  0, 0,
 395                                  1, 2),
 396        },
 397#endif
 398#ifdef CONFIG_ARM64_ERRATUM_834220
 399        {
 400        /* Cortex-A57 r0p0 - r1p2 */
 401                .desc = "ARM erratum 834220",
 402                .capability = ARM64_WORKAROUND_834220,
 403                ERRATA_MIDR_RANGE(MIDR_CORTEX_A57,
 404                                  0, 0,
 405                                  1, 2),
 406        },
 407#endif
 408#ifdef CONFIG_ARM64_ERRATUM_843419
 409        {
 410                .desc = "ARM erratum 843419",
 411                .capability = ARM64_WORKAROUND_843419,
 412                .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 413                .matches = cpucap_multi_entry_cap_matches,
 414                .match_list = erratum_843419_list,
 415        },
 416#endif
 417#ifdef CONFIG_ARM64_ERRATUM_845719
 418        {
 419                .desc = "ARM erratum 845719",
 420                .capability = ARM64_WORKAROUND_845719,
 421                ERRATA_MIDR_RANGE_LIST(erratum_845719_list),
 422        },
 423#endif
 424#ifdef CONFIG_CAVIUM_ERRATUM_23154
 425        {
 426        /* Cavium ThunderX, pass 1.x */
 427                .desc = "Cavium erratum 23154",
 428                .capability = ARM64_WORKAROUND_CAVIUM_23154,
 429                ERRATA_MIDR_REV_RANGE(MIDR_THUNDERX, 0, 0, 1),
 430        },
 431#endif
 432#ifdef CONFIG_CAVIUM_ERRATUM_27456
 433        {
 434                .desc = "Cavium erratum 27456",
 435                .capability = ARM64_WORKAROUND_CAVIUM_27456,
 436                ERRATA_MIDR_RANGE_LIST(cavium_erratum_27456_cpus),
 437        },
 438#endif
 439#ifdef CONFIG_CAVIUM_ERRATUM_30115
 440        {
 441                .desc = "Cavium erratum 30115",
 442                .capability = ARM64_WORKAROUND_CAVIUM_30115,
 443                ERRATA_MIDR_RANGE_LIST(cavium_erratum_30115_cpus),
 444        },
 445#endif
 446        {
 447                .desc = "Mismatched cache type (CTR_EL0)",
 448                .capability = ARM64_MISMATCHED_CACHE_TYPE,
 449                .matches = has_mismatched_cache_type,
 450                .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 451                .cpu_enable = cpu_enable_trap_ctr_access,
 452        },
 453#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
 454        {
 455                .desc = "Qualcomm Technologies Falkor/Kryo erratum 1003",
 456                .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
 457                .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 458                .matches = cpucap_multi_entry_cap_matches,
 459                .match_list = qcom_erratum_1003_list,
 460        },
 461#endif
 462#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
 463        {
 464                .desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
 465                .capability = ARM64_WORKAROUND_REPEAT_TLBI,
 466                .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 467                .matches = cpucap_multi_entry_cap_matches,
 468                .match_list = arm64_repeat_tlbi_list,
 469        },
 470#endif
 471#ifdef CONFIG_ARM64_ERRATUM_858921
 472        {
 473        /* Cortex-A73 all versions */
 474                .desc = "ARM erratum 858921",
 475                .capability = ARM64_WORKAROUND_858921,
 476                ERRATA_MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 477        },
 478#endif
 479        {
 480                .desc = "Spectre-v2",
 481                .capability = ARM64_SPECTRE_V2,
 482                .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 483                .matches = has_spectre_v2,
 484                .cpu_enable = spectre_v2_enable_mitigation,
 485        },
 486#ifdef CONFIG_RANDOMIZE_BASE
 487        {
 488        /* Must come after the Spectre-v2 entry */
 489                .desc = "Spectre-v3a",
 490                .capability = ARM64_SPECTRE_V3A,
 491                .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 492                .matches = has_spectre_v3a,
 493                .cpu_enable = spectre_v3a_enable_mitigation,
 494        },
 495#endif
 496        {
 497                .desc = "Spectre-v4",
 498                .capability = ARM64_SPECTRE_V4,
 499                .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 500                .matches = has_spectre_v4,
 501                .cpu_enable = spectre_v4_enable_mitigation,
 502        },
 503#ifdef CONFIG_ARM64_ERRATUM_1418040
 504        {
 505                .desc = "ARM erratum 1418040",
 506                .capability = ARM64_WORKAROUND_1418040,
 507                ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),
 508                /*
 509                 * We need to allow affected CPUs to come in late, but
 510                 * also need the non-affected CPUs to be able to come
 511                 * in at any point in time. Wonderful.
 512                 */
 513                .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
 514        },
 515#endif
 516#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT
 517        {
 518                .desc = "ARM errata 1165522, 1319367, or 1530923",
 519                .capability = ARM64_WORKAROUND_SPECULATIVE_AT,
 520                ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),
 521        },
 522#endif
 523#ifdef CONFIG_ARM64_ERRATUM_1463225
 524        {
 525                .desc = "ARM erratum 1463225",
 526                .capability = ARM64_WORKAROUND_1463225,
 527                .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 528                .matches = has_cortex_a76_erratum_1463225,
 529                .midr_range_list = erratum_1463225,
 530        },
 531#endif
 532#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
 533        {
 534                .desc = "Cavium ThunderX2 erratum 219 (KVM guest sysreg trapping)",
 535                .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_TVM,
 536                ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
 537                .matches = needs_tx2_tvm_workaround,
 538        },
 539        {
 540                .desc = "Cavium ThunderX2 erratum 219 (PRFM removal)",
 541                .capability = ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM,
 542                ERRATA_MIDR_RANGE_LIST(tx2_family_cpus),
 543        },
 544#endif
 545#ifdef CONFIG_ARM64_ERRATUM_1542419
 546        {
 547                /* we depend on the firmware portion for correctness */
 548                .desc = "ARM erratum 1542419 (kernel portion)",
 549                .capability = ARM64_WORKAROUND_1542419,
 550                .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
 551                .matches = has_neoverse_n1_erratum_1542419,
 552                .cpu_enable = cpu_enable_trap_ctr_access,
 553        },
 554#endif
 555#ifdef CONFIG_ARM64_ERRATUM_1508412
 556        {
 557                /* we depend on the firmware portion for correctness */
 558                .desc = "ARM erratum 1508412 (kernel portion)",
 559                .capability = ARM64_WORKAROUND_1508412,
 560                ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
 561                                  0, 0,
 562                                  1, 0),
 563        },
 564#endif
 565#ifdef CONFIG_NVIDIA_CARMEL_CNP_ERRATUM
 566        {
 567                /* NVIDIA Carmel */
 568                .desc = "NVIDIA Carmel CNP erratum",
 569                .capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,
 570                ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
 571        },
 572#endif
 573#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
 574        {
 575                /*
 576                 * The erratum work around is handled within the TRBE
 577                 * driver and can be applied per-cpu. So, we can allow
 578                 * a late CPU to come online with this erratum.
 579                 */
 580                .desc = "ARM erratum 2119858 or 2139208",
 581                .capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,
 582                .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
 583                CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),
 584        },
 585#endif
 586#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE
 587        {
 588                .desc = "ARM erratum 2067961 or 2054223",
 589                .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE,
 590                ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus),
 591        },
 592#endif
 593#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
 594        {
 595                .desc = "ARM erratum 2253138 or 2224489",
 596                .capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE,
 597                .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
 598                CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),
 599        },
 600#endif
 601        {
 602        }
 603};
 604