LXR linux/arch/mips/include/asm/octeon/cvmx-boot-vector.h

   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2003-2017 Cavium, Inc.
   7 */
   8
   9#ifndef __CVMX_BOOT_VECTOR_H__
  10#define __CVMX_BOOT_VECTOR_H__
  11
  12#include <asm/octeon/octeon.h>
  13
  14/*
  15 * The boot vector table is made up of an array of 1024 elements of
  16 * struct cvmx_boot_vector_element.  There is one entry for each
  17 * possible MIPS CPUNum, indexed by the CPUNum.
  18 *
  19 * Once cvmx_boot_vector_get() returns a non-NULL value (indicating
  20 * success), NMI to a core will cause execution to transfer to the
  21 * target_ptr location for that core's entry in the vector table.
  22 *
  23 * The struct cvmx_boot_vector_element fields app0, app1, and app2 can
  24 * be used by the application that has set the target_ptr in any
  25 * application specific manner, they are not touched by the vectoring
  26 * code.
  27 *
  28 * The boot vector code clobbers the CP0_DESAVE register, and on
  29 * OCTEON II and later CPUs also clobbers CP0_KScratch2.  All GP
  30 * registers are preserved, except on pre-OCTEON II CPUs, where k1 is
  31 * clobbered.
  32 *
  33 */
  34
  35
  36/*
  37 * Applications install the boot bus code in cvmx-boot-vector.c, which
  38 * uses this magic:
  39 */
  40#define OCTEON_BOOT_MOVEABLE_MAGIC1 0xdb00110ad358eacdull
  41
  42struct cvmx_boot_vector_element {
  43        /* kseg0 or xkphys address of target code. */
  44        uint64_t target_ptr;
  45        /* Three application specific arguments. */
  46        uint64_t app0;
  47        uint64_t app1;
  48        uint64_t app2;
  49};
  50
  51struct cvmx_boot_vector_element *cvmx_boot_vector_get(void);
  52
  53#endif /* __CVMX_BOOT_VECTOR_H__ */
  54