LXR linux/arch/powerpc/include/asm/ppc

   1/*
   2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
   3 */
   4#ifndef _ASM_POWERPC_PPC_ASM_H
   5#define _ASM_POWERPC_PPC_ASM_H
   6
   7#include <linux/stringify.h>
   8#include <asm/asm-compat.h>
   9#include <asm/processor.h>
  10#include <asm/ppc-opcode.h>
  11#include <asm/firmware.h>
  12#include <asm/feature-fixups.h>
  13#include <asm/extable.h>
  14
  15#ifdef __ASSEMBLY__
  16
  17#define SZL                     (BITS_PER_LONG/8)
  18
  19/*
  20 * Macros for storing registers into and loading registers from
  21 * exception frames.
  22 */
  23#ifdef __powerpc64__
  24#define SAVE_GPR(n, base)       std     n,GPR0+8*(n)(base)
  25#define REST_GPR(n, base)       ld      n,GPR0+8*(n)(base)
  26#define SAVE_NVGPRS(base)       SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
  27#define REST_NVGPRS(base)       REST_8GPRS(14, base); REST_10GPRS(22, base)
  28#else
  29#define SAVE_GPR(n, base)       stw     n,GPR0+4*(n)(base)
  30#define REST_GPR(n, base)       lwz     n,GPR0+4*(n)(base)
  31#define SAVE_NVGPRS(base)       SAVE_GPR(13, base); SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
  32#define REST_NVGPRS(base)       REST_GPR(13, base); REST_8GPRS(14, base); REST_10GPRS(22, base)
  33#endif
  34
  35#define SAVE_2GPRS(n, base)     SAVE_GPR(n, base); SAVE_GPR(n+1, base)
  36#define SAVE_4GPRS(n, base)     SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
  37#define SAVE_8GPRS(n, base)     SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
  38#define SAVE_10GPRS(n, base)    SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
  39#define REST_2GPRS(n, base)     REST_GPR(n, base); REST_GPR(n+1, base)
  40#define REST_4GPRS(n, base)     REST_2GPRS(n, base); REST_2GPRS(n+2, base)
  41#define REST_8GPRS(n, base)     REST_4GPRS(n, base); REST_4GPRS(n+4, base)
  42#define REST_10GPRS(n, base)    REST_8GPRS(n, base); REST_2GPRS(n+8, base)
  43
  44#define SAVE_FPR(n, base)       stfd    n,8*TS_FPRWIDTH*(n)(base)
  45#define SAVE_2FPRS(n, base)     SAVE_FPR(n, base); SAVE_FPR(n+1, base)
  46#define SAVE_4FPRS(n, base)     SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
  47#define SAVE_8FPRS(n, base)     SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
  48#define SAVE_16FPRS(n, base)    SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
  49#define SAVE_32FPRS(n, base)    SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
  50#define REST_FPR(n, base)       lfd     n,8*TS_FPRWIDTH*(n)(base)
  51#define REST_2FPRS(n, base)     REST_FPR(n, base); REST_FPR(n+1, base)
  52#define REST_4FPRS(n, base)     REST_2FPRS(n, base); REST_2FPRS(n+2, base)
  53#define REST_8FPRS(n, base)     REST_4FPRS(n, base); REST_4FPRS(n+4, base)
  54#define REST_16FPRS(n, base)    REST_8FPRS(n, base); REST_8FPRS(n+8, base)
  55#define REST_32FPRS(n, base)    REST_16FPRS(n, base); REST_16FPRS(n+16, base)
  56
  57#define SAVE_VR(n,b,base)       li b,16*(n);  stvx n,base,b
  58#define SAVE_2VRS(n,b,base)     SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
  59#define SAVE_4VRS(n,b,base)     SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
  60#define SAVE_8VRS(n,b,base)     SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
  61#define SAVE_16VRS(n,b,base)    SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
  62#define SAVE_32VRS(n,b,base)    SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
  63#define REST_VR(n,b,base)       li b,16*(n); lvx n,base,b
  64#define REST_2VRS(n,b,base)     REST_VR(n,b,base); REST_VR(n+1,b,base)
  65#define REST_4VRS(n,b,base)     REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
  66#define REST_8VRS(n,b,base)     REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
  67#define REST_16VRS(n,b,base)    REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
  68#define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
  69
  70#ifdef __BIG_ENDIAN__
  71#define STXVD2X_ROT(n,b,base)           STXVD2X(n,b,base)
  72#define LXVD2X_ROT(n,b,base)            LXVD2X(n,b,base)
  73#else
  74#define STXVD2X_ROT(n,b,base)           XXSWAPD(n,n);           \
  75                                        STXVD2X(n,b,base);      \
  76                                        XXSWAPD(n,n)
  77
  78#define LXVD2X_ROT(n,b,base)            LXVD2X(n,b,base);       \
  79                                        XXSWAPD(n,n)
  80#endif
  81/* Save the lower 32 VSRs in the thread VSR region */
  82#define SAVE_VSR(n,b,base)      li b,16*(n);  STXVD2X_ROT(n,R##base,R##b)
  83#define SAVE_2VSRS(n,b,base)    SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
  84#define SAVE_4VSRS(n,b,base)    SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
  85#define SAVE_8VSRS(n,b,base)    SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
  86#define SAVE_16VSRS(n,b,base)   SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
  87#define SAVE_32VSRS(n,b,base)   SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
  88#define REST_VSR(n,b,base)      li b,16*(n); LXVD2X_ROT(n,R##base,R##b)
  89#define REST_2VSRS(n,b,base)    REST_VSR(n,b,base); REST_VSR(n+1,b,base)
  90#define REST_4VSRS(n,b,base)    REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
  91#define REST_8VSRS(n,b,base)    REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
  92#define REST_16VSRS(n,b,base)   REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
  93#define REST_32VSRS(n,b,base)   REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
  94
  95/*
  96 * b = base register for addressing, o = base offset from register of 1st EVR
  97 * n = first EVR, s = scratch
  98 */
  99#define SAVE_EVR(n,s,b,o)       evmergehi s,s,n; stw s,o+4*(n)(b)
 100#define SAVE_2EVRS(n,s,b,o)     SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o)
 101#define SAVE_4EVRS(n,s,b,o)     SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o)
 102#define SAVE_8EVRS(n,s,b,o)     SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o)
 103#define SAVE_16EVRS(n,s,b,o)    SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o)
 104#define SAVE_32EVRS(n,s,b,o)    SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o)
 105#define REST_EVR(n,s,b,o)       lwz s,o+4*(n)(b); evmergelo n,s,n
 106#define REST_2EVRS(n,s,b,o)     REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o)
 107#define REST_4EVRS(n,s,b,o)     REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o)
 108#define REST_8EVRS(n,s,b,o)     REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o)
 109#define REST_16EVRS(n,s,b,o)    REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o)
 110#define REST_32EVRS(n,s,b,o)    REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o)
 111
 112/* Macros to adjust thread priority for hardware multithreading */
 113#define HMT_VERY_LOW    or      31,31,31        # very low priority
 114#define HMT_LOW         or      1,1,1
 115#define HMT_MEDIUM_LOW  or      6,6,6           # medium low priority
 116#define HMT_MEDIUM      or      2,2,2
 117#define HMT_MEDIUM_HIGH or      5,5,5           # medium high priority
 118#define HMT_HIGH        or      3,3,3
 119#define HMT_EXTRA_HIGH  or      7,7,7           # power7 only
 120
 121#ifdef CONFIG_PPC64
 122#define ULONG_SIZE      8
 123#else
 124#define ULONG_SIZE      4
 125#endif
 126#define __VCPU_GPR(n)   (VCPU_GPRS + (n * ULONG_SIZE))
 127#define VCPU_GPR(n)     __VCPU_GPR(__REG_##n)
 128
 129#ifdef __KERNEL__
 130
 131/*
 132 * We use __powerpc64__ here because we want the compat VDSO to use the 32-bit
 133 * version below in the else case of the ifdef.
 134 */
 135#ifdef __powerpc64__
 136
 137#define STACKFRAMESIZE 256
 138#define __STK_REG(i)   (112 + ((i)-14)*8)
 139#define STK_REG(i)     __STK_REG(__REG_##i)
 140
 141#ifdef PPC64_ELF_ABI_v2
 142#define STK_GOT         24
 143#define __STK_PARAM(i)  (32 + ((i)-3)*8)
 144#else
 145#define STK_GOT         40
 146#define __STK_PARAM(i)  (48 + ((i)-3)*8)
 147#endif
 148#define STK_PARAM(i)    __STK_PARAM(__REG_##i)
 149
 150#ifdef PPC64_ELF_ABI_v2
 151
 152#define _GLOBAL(name) \
 153        .align 2 ; \
 154        .type name,@function; \
 155        .globl name; \
 156name:
 157
 158#define _GLOBAL_TOC(name) \
 159        .align 2 ; \
 160        .type name,@function; \
 161        .globl name; \
 162name: \
 1630:      addis r2,r12,(.TOC.-0b)@ha; \
 164        addi r2,r2,(.TOC.-0b)@l; \
 165        .localentry name,.-name
 166
 167#define DOTSYM(a)       a
 168
 169#else
 170
 171#define XGLUE(a,b) a##b
 172#define GLUE(a,b) XGLUE(a,b)
 173
 174#define _GLOBAL(name) \
 175        .align 2 ; \
 176        .globl name; \
 177        .globl GLUE(.,name); \
 178        .pushsection ".opd","aw"; \
 179name: \
 180        .quad GLUE(.,name); \
 181        .quad .TOC.@tocbase; \
 182        .quad 0; \
 183        .popsection; \
 184        .type GLUE(.,name),@function; \
 185GLUE(.,name):
 186
 187#define _GLOBAL_TOC(name) _GLOBAL(name)
 188
 189#define DOTSYM(a)       GLUE(.,a)
 190
 191#endif
 192
 193#else /* 32-bit */
 194
 195#define _ENTRY(n)       \
 196        .globl n;       \
 197n:
 198
 199#define _GLOBAL(n)      \
 200        .stabs __stringify(n:F-1),N_FUN,0,0,n;\
 201        .globl n;       \
 202n:
 203
 204#define _GLOBAL_TOC(name) _GLOBAL(name)
 205
 206#define DOTSYM(a)       a
 207
 208#endif
 209
 210/*
 211 * __kprobes (the C annotation) puts the symbol into the .kprobes.text
 212 * section, which gets emitted at the end of regular text.
 213 *
 214 * _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to
 215 * a blacklist. The former is for core kprobe functions/data, the
 216 * latter is for those that incdentially must be excluded from probing
 217 * and allows them to be linked at more optimal location within text.
 218 */
 219#ifdef CONFIG_KPROBES
 220#define _ASM_NOKPROBE_SYMBOL(entry)                     \
 221        .pushsection "_kprobe_blacklist","aw";          \
 222        PPC_LONG (entry) ;                              \
 223        .popsection
 224#else
 225#define _ASM_NOKPROBE_SYMBOL(entry)
 226#endif
 227
 228#define FUNC_START(name)        _GLOBAL(name)
 229#define FUNC_END(name)
 230
 231/* 
 232 * LOAD_REG_IMMEDIATE(rn, expr)
 233 *   Loads the value of the constant expression 'expr' into register 'rn'
 234 *   using immediate instructions only.  Use this when it's important not
 235 *   to reference other data (i.e. on ppc64 when the TOC pointer is not
 236 *   valid) and when 'expr' is a constant or absolute address.
 237 *
 238 * LOAD_REG_ADDR(rn, name)
 239 *   Loads the address of label 'name' into register 'rn'.  Use this when
 240 *   you don't particularly need immediate instructions only, but you need
 241 *   the whole address in one register (e.g. it's a structure address and
 242 *   you want to access various offsets within it).  On ppc32 this is
 243 *   identical to LOAD_REG_IMMEDIATE.
 244 *
 245 * LOAD_REG_ADDR_PIC(rn, name)
 246 *   Loads the address of label 'name' into register 'run'. Use this when
 247 *   the kernel doesn't run at the linked or relocated address. Please
 248 *   note that this macro will clobber the lr register.
 249 *
 250 * LOAD_REG_ADDRBASE(rn, name)
 251 * ADDROFF(name)
 252 *   LOAD_REG_ADDRBASE loads part of the address of label 'name' into
 253 *   register 'rn'.  ADDROFF(name) returns the remainder of the address as
 254 *   a constant expression.  ADDROFF(name) is a signed expression < 16 bits
 255 *   in size, so is suitable for use directly as an offset in load and store
 256 *   instructions.  Use this when loading/storing a single word or less as:
 257 *      LOAD_REG_ADDRBASE(rX, name)
 258 *      ld      rY,ADDROFF(name)(rX)
 259 */
 260
 261/* Be careful, this will clobber the lr register. */
 262#define LOAD_REG_ADDR_PIC(reg, name)            \
 263        bcl     20,31,$+4;                      \
 2640:      mflr    reg;                            \
 265        addis   reg,reg,(name - 0b)@ha;         \
 266        addi    reg,reg,(name - 0b)@l;
 267
 268#if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH)
 269#define __AS_ATHIGH high
 270#else
 271#define __AS_ATHIGH h
 272#endif
 273
 274.macro __LOAD_REG_IMMEDIATE_32 r, x
 275        .if (\x) >= 0x8000 || (\x) < -0x8000
 276                lis \r, (\x)@__AS_ATHIGH
 277                .if (\x) & 0xffff != 0
 278                        ori \r, \r, (\x)@l
 279                .endif
 280        .else
 281                li \r, (\x)@l
 282        .endif
 283.endm
 284
 285.macro __LOAD_REG_IMMEDIATE r, x
 286        .if (\x) >= 0x80000000 || (\x) < -0x80000000
 287                __LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32
 288                sldi    \r, \r, 32
 289                .if (\x) & 0xffff0000 != 0
 290                        oris \r, \r, (\x)@__AS_ATHIGH
 291                .endif
 292                .if (\x) & 0xffff != 0
 293                        ori \r, \r, (\x)@l
 294                .endif
 295        .else
 296                __LOAD_REG_IMMEDIATE_32 \r, \x
 297        .endif
 298.endm
 299
 300#ifdef __powerpc64__
 301
 302#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr
 303
 304#define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr)  \
 305        lis     tmp, (expr)@highest;            \
 306        lis     reg, (expr)@__AS_ATHIGH;        \
 307        ori     tmp, tmp, (expr)@higher;        \
 308        ori     reg, reg, (expr)@l;             \
 309        rldimi  reg, tmp, 32, 0
 310
 311#define LOAD_REG_ADDR(reg,name)                 \
 312        ld      reg,name@got(r2)
 313
 314#define LOAD_REG_ADDRBASE(reg,name)     LOAD_REG_ADDR(reg,name)
 315#define ADDROFF(name)                   0
 316
 317/* offsets for stack frame layout */
 318#define LRSAVE  16
 319
 320#else /* 32-bit */
 321
 322#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr
 323
 324#define LOAD_REG_IMMEDIATE_SYM(reg,expr)                \
 325        lis     reg,(expr)@ha;          \
 326        addi    reg,reg,(expr)@l;
 327
 328#define LOAD_REG_ADDR(reg,name)         LOAD_REG_IMMEDIATE_SYM(reg, name)
 329
 330#define LOAD_REG_ADDRBASE(reg, name)    lis     reg,name@ha
 331#define ADDROFF(name)                   name@l
 332
 333/* offsets for stack frame layout */
 334#define LRSAVE  4
 335
 336#endif
 337
 338/* various errata or part fixups */
 339#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E)
 340#define MFTB(dest)                      \
 34190:     mfspr dest, SPRN_TBRL;          \
 342BEGIN_FTR_SECTION_NESTED(96);           \
 343        cmpwi dest,0;                   \
 344        beq-  90b;                      \
 345END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
 346#else
 347#define MFTB(dest)                      MFTBL(dest)
 348#endif
 349
 350#ifdef CONFIG_PPC_8xx
 351#define MFTBL(dest)                     mftb dest
 352#define MFTBU(dest)                     mftbu dest
 353#else
 354#define MFTBL(dest)                     mfspr dest, SPRN_TBRL
 355#define MFTBU(dest)                     mfspr dest, SPRN_TBRU
 356#endif
 357
 358#ifndef CONFIG_SMP
 359#define TLBSYNC
 360#else
 361#define TLBSYNC         tlbsync; sync
 362#endif
 363
 364#ifdef CONFIG_PPC64
 365#define MTOCRF(FXM, RS)                 \
 366        BEGIN_FTR_SECTION_NESTED(848);  \
 367        mtcrf   (FXM), RS;              \
 368        FTR_SECTION_ELSE_NESTED(848);   \
 369        mtocrf (FXM), RS;               \
 370        ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
 371#endif
 372
 373/*
 374 * This instruction is not implemented on the PPC 603 or 601; however, on
 375 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
 376 * All of these instructions exist in the 8xx, they have magical powers,
 377 * and they must be used.
 378 */
 379
 380#if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx)
 381#define tlbia                                   \
 382        li      r4,1024;                        \
 383        mtctr   r4;                             \
 384        lis     r4,KERNELBASE@h;                \
 385        .machine push;                          \
 386        .machine "power4";                      \
 3870:      tlbie   r4;                             \
 388        .machine pop;                           \
 389        addi    r4,r4,0x1000;                   \
 390        bdnz    0b
 391#endif
 392
 393
 394#ifdef CONFIG_IBM440EP_ERR42
 395#define PPC440EP_ERR42 isync
 396#else
 397#define PPC440EP_ERR42
 398#endif
 399
 400/* The following stops all load and store data streams associated with stream
 401 * ID (ie. streams created explicitly).  The embedded and server mnemonics for
 402 * dcbt are different so this must only be used for server.
 403 */
 404#define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch)        \
 405       lis     scratch,0x60000000@h;                    \
 406       dcbt    0,scratch,0b01010
 407
 408/*
 409 * toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them
 410 * keep the address intact to be compatible with code shared with
 411 * 32-bit classic.
 412 *
 413 * On the other hand, I find it useful to have them behave as expected
 414 * by their name (ie always do the addition) on 64-bit BookE
 415 */
 416#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64)
 417#define toreal(rd)
 418#define fromreal(rd)
 419
 420/*
 421 * We use addis to ensure compatibility with the "classic" ppc versions of
 422 * these macros, which use rs = 0 to get the tophys offset in rd, rather than
 423 * converting the address in r0, and so this version has to do that too
 424 * (i.e. set register rd to 0 when rs == 0).
 425 */
 426#define tophys(rd,rs)                           \
 427        addis   rd,rs,0
 428
 429#define tovirt(rd,rs)                           \
 430        addis   rd,rs,0
 431
 432#elif defined(CONFIG_PPC64)
 433#define toreal(rd)              /* we can access c000... in real mode */
 434#define fromreal(rd)
 435
 436#define tophys(rd,rs)                           \
 437        clrldi  rd,rs,2
 438
 439#define tovirt(rd,rs)                           \
 440        rotldi  rd,rs,16;                       \
 441        ori     rd,rd,((KERNELBASE>>48)&0xFFFF);\
 442        rotldi  rd,rd,48
 443#else
 444#define toreal(rd)      tophys(rd,rd)
 445#define fromreal(rd)    tovirt(rd,rd)
 446
 447#define tophys(rd, rs)  addis   rd, rs, -PAGE_OFFSET@h
 448#define tovirt(rd, rs)  addis   rd, rs, PAGE_OFFSET@h
 449#endif
 450
 451#ifdef CONFIG_PPC_BOOK3S_64
 452#define MTMSRD(r)       mtmsrd  r
 453#define MTMSR_EERI(reg) mtmsrd  reg,1
 454#else
 455#define MTMSRD(r)       mtmsr   r
 456#define MTMSR_EERI(reg) mtmsr   reg
 457#endif
 458
 459#endif /* __KERNEL__ */
 460
 461/* The boring bits... */
 462
 463/* Condition Register Bit Fields */
 464
 465#define cr0     0
 466#define cr1     1
 467#define cr2     2
 468#define cr3     3
 469#define cr4     4
 470#define cr5     5
 471#define cr6     6
 472#define cr7     7
 473
 474
 475/*
 476 * General Purpose Registers (GPRs)
 477 *
 478 * The lower case r0-r31 should be used in preference to the upper
 479 * case R0-R31 as they provide more error checking in the assembler.
 480 * Use R0-31 only when really nessesary.
 481 */
 482
 483#define r0      %r0
 484#define r1      %r1
 485#define r2      %r2
 486#define r3      %r3
 487#define r4      %r4
 488#define r5      %r5
 489#define r6      %r6
 490#define r7      %r7
 491#define r8      %r8
 492#define r9      %r9
 493#define r10     %r10
 494#define r11     %r11
 495#define r12     %r12
 496#define r13     %r13
 497#define r14     %r14
 498#define r15     %r15
 499#define r16     %r16
 500#define r17     %r17
 501#define r18     %r18
 502#define r19     %r19
 503#define r20     %r20
 504#define r21     %r21
 505#define r22     %r22
 506#define r23     %r23
 507#define r24     %r24
 508#define r25     %r25
 509#define r26     %r26
 510#define r27     %r27
 511#define r28     %r28
 512#define r29     %r29
 513#define r30     %r30
 514#define r31     %r31
 515
 516
 517/* Floating Point Registers (FPRs) */
 518
 519#define fr0     0
 520#define fr1     1
 521#define fr2     2
 522#define fr3     3
 523#define fr4     4
 524#define fr5     5
 525#define fr6     6
 526#define fr7     7
 527#define fr8     8
 528#define fr9     9
 529#define fr10    10
 530#define fr11    11
 531#define fr12    12
 532#define fr13    13
 533#define fr14    14
 534#define fr15    15
 535#define fr16    16
 536#define fr17    17
 537#define fr18    18
 538#define fr19    19
 539#define fr20    20
 540#define fr21    21
 541#define fr22    22
 542#define fr23    23
 543#define fr24    24
 544#define fr25    25
 545#define fr26    26
 546#define fr27    27
 547#define fr28    28
 548#define fr29    29
 549#define fr30    30
 550#define fr31    31
 551
 552/* AltiVec Registers (VPRs) */
 553
 554#define v0      0
 555#define v1      1
 556#define v2      2
 557#define v3      3
 558#define v4      4
 559#define v5      5
 560#define v6      6
 561#define v7      7
 562#define v8      8
 563#define v9      9
 564#define v10     10
 565#define v11     11
 566#define v12     12
 567#define v13     13
 568#define v14     14
 569#define v15     15
 570#define v16     16
 571#define v17     17
 572#define v18     18
 573#define v19     19
 574#define v20     20
 575#define v21     21
 576#define v22     22
 577#define v23     23
 578#define v24     24
 579#define v25     25
 580#define v26     26
 581#define v27     27
 582#define v28     28
 583#define v29     29
 584#define v30     30
 585#define v31     31
 586
 587/* VSX Registers (VSRs) */
 588
 589#define vs0     0
 590#define vs1     1
 591#define vs2     2
 592#define vs3     3
 593#define vs4     4
 594#define vs5     5
 595#define vs6     6
 596#define vs7     7
 597#define vs8     8
 598#define vs9     9
 599#define vs10    10
 600#define vs11    11
 601#define vs12    12
 602#define vs13    13
 603#define vs14    14
 604#define vs15    15
 605#define vs16    16
 606#define vs17    17
 607#define vs18    18
 608#define vs19    19
 609#define vs20    20
 610#define vs21    21
 611#define vs22    22
 612#define vs23    23
 613#define vs24    24
 614#define vs25    25
 615#define vs26    26
 616#define vs27    27
 617#define vs28    28
 618#define vs29    29
 619#define vs30    30
 620#define vs31    31
 621#define vs32    32
 622#define vs33    33
 623#define vs34    34
 624#define vs35    35
 625#define vs36    36
 626#define vs37    37
 627#define vs38    38
 628#define vs39    39
 629#define vs40    40
 630#define vs41    41
 631#define vs42    42
 632#define vs43    43
 633#define vs44    44
 634#define vs45    45
 635#define vs46    46
 636#define vs47    47
 637#define vs48    48
 638#define vs49    49
 639#define vs50    50
 640#define vs51    51
 641#define vs52    52
 642#define vs53    53
 643#define vs54    54
 644#define vs55    55
 645#define vs56    56
 646#define vs57    57
 647#define vs58    58
 648#define vs59    59
 649#define vs60    60
 650#define vs61    61
 651#define vs62    62
 652#define vs63    63
 653
 654/* SPE Registers (EVPRs) */
 655
 656#define evr0    0
 657#define evr1    1
 658#define evr2    2
 659#define evr3    3
 660#define evr4    4
 661#define evr5    5
 662#define evr6    6
 663#define evr7    7
 664#define evr8    8
 665#define evr9    9
 666#define evr10   10
 667#define evr11   11
 668#define evr12   12
 669#define evr13   13
 670#define evr14   14
 671#define evr15   15
 672#define evr16   16
 673#define evr17   17
 674#define evr18   18
 675#define evr19   19
 676#define evr20   20
 677#define evr21   21
 678#define evr22   22
 679#define evr23   23
 680#define evr24   24
 681#define evr25   25
 682#define evr26   26
 683#define evr27   27
 684#define evr28   28
 685#define evr29   29
 686#define evr30   30
 687#define evr31   31
 688
 689/* some stab codes */
 690#define N_FUN   36
 691#define N_RSYM  64
 692#define N_SLINE 68
 693#define N_SO    100
 694
 695#define RFSCV   .long 0x4c0000a4
 696
 697/*
 698 * Create an endian fixup trampoline
 699 *
 700 * This starts with a "tdi 0,0,0x48" instruction which is
 701 * essentially a "trap never", and thus akin to a nop.
 702 *
 703 * The opcode for this instruction read with the wrong endian
 704 * however results in a b . + 8
 705 *
 706 * So essentially we use that trick to execute the following
 707 * trampoline in "reverse endian" if we are running with the
 708 * MSR_LE bit set the "wrong" way for whatever endianness the
 709 * kernel is built for.
 710 */
 711
 712#ifdef CONFIG_PPC_BOOK3E
 713#define FIXUP_ENDIAN
 714#else
 715/*
 716 * This version may be used in HV or non-HV context.
 717 * MSR[EE] must be disabled.
 718 */
 719#define FIXUP_ENDIAN                                               \
 720        tdi   0,0,0x48;   /* Reverse endian of b . + 8          */ \
 721        b     191f;       /* Skip trampoline if endian is good  */ \
 722        .long 0xa600607d; /* mfmsr r11                          */ \
 723        .long 0x01006b69; /* xori r11,r11,1                     */ \
 724        .long 0x00004039; /* li r10,0                           */ \
 725        .long 0x6401417d; /* mtmsrd r10,1                       */ \
 726        .long 0x05009f42; /* bcl 20,31,$+4                      */ \
 727        .long 0xa602487d; /* mflr r10                           */ \
 728        .long 0x14004a39; /* addi r10,r10,20                    */ \
 729        .long 0xa6035a7d; /* mtsrr0 r10                         */ \
 730        .long 0xa6037b7d; /* mtsrr1 r11                         */ \
 731        .long 0x2400004c; /* rfid                               */ \
 732191:
 733
 734/*
 735 * This version that may only be used with MSR[HV]=1
 736 * - Does not clear MSR[RI], so more robust.
 737 * - Slightly smaller and faster.
 738 */
 739#define FIXUP_ENDIAN_HV                                            \
 740        tdi   0,0,0x48;   /* Reverse endian of b . + 8          */ \
 741        b     191f;       /* Skip trampoline if endian is good  */ \
 742        .long 0xa600607d; /* mfmsr r11                          */ \
 743        .long 0x01006b69; /* xori r11,r11,1                     */ \
 744        .long 0x05009f42; /* bcl 20,31,$+4                      */ \
 745        .long 0xa602487d; /* mflr r10                           */ \
 746        .long 0x14004a39; /* addi r10,r10,20                    */ \
 747        .long 0xa64b5a7d; /* mthsrr0 r10                        */ \
 748        .long 0xa64b7b7d; /* mthsrr1 r11                        */ \
 749        .long 0x2402004c; /* hrfid                              */ \
 750191:
 751
 752#endif /* !CONFIG_PPC_BOOK3E */
 753
 754#endif /*  __ASSEMBLY__ */
 755
 756#define SOFT_MASK_TABLE(_start, _end)           \
 757        stringify_in_c(.section __soft_mask_table,"a";)\
 758        stringify_in_c(.balign 8;)              \
 759        stringify_in_c(.llong (_start);)        \
 760        stringify_in_c(.llong (_end);)          \
 761        stringify_in_c(.previous)
 762
 763#define RESTART_TABLE(_start, _end, _target)    \
 764        stringify_in_c(.section __restart_table,"a";)\
 765        stringify_in_c(.balign 8;)              \
 766        stringify_in_c(.llong (_start);)        \
 767        stringify_in_c(.llong (_end);)          \
 768        stringify_in_c(.llong (_target);)       \
 769        stringify_in_c(.previous)
 770
 771#ifdef CONFIG_PPC_FSL_BOOK3E
 772#define BTB_FLUSH(reg)                  \
 773        lis reg,BUCSR_INIT@h;           \
 774        ori reg,reg,BUCSR_INIT@l;       \
 775        mtspr SPRN_BUCSR,reg;           \
 776        isync;
 777#else
 778#define BTB_FLUSH(reg)
 779#endif /* CONFIG_PPC_FSL_BOOK3E */
 780
 781#endif /* _ASM_POWERPC_PPC_ASM_H */
 782