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5#include <asm/inst.h>
6
7struct pt_regs;
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18
19#define IS_MTMSRD(instr) ((ppc_inst_val(instr) & 0xfc0007be) == 0x7c000124)
20#define IS_RFID(instr) ((ppc_inst_val(instr) & 0xfc0007be) == 0x4c000024)
21
22enum instruction_type {
23 COMPUTE,
24 LOAD,
25 LOAD_MULTI,
26 LOAD_FP,
27 LOAD_VMX,
28 LOAD_VSX,
29 STORE,
30 STORE_MULTI,
31 STORE_FP,
32 STORE_VMX,
33 STORE_VSX,
34 LARX,
35 STCX,
36 BRANCH,
37 MFSPR,
38 MTSPR,
39 CACHEOP,
40 BARRIER,
41 SYSCALL,
42 SYSCALL_VECTORED_0,
43 MFMSR,
44 MTMSR,
45 RFI,
46 INTERRUPT,
47 UNKNOWN
48};
49
50#define INSTR_TYPE_MASK 0x1f
51
52#define OP_IS_LOAD(type) ((LOAD <= (type) && (type) <= LOAD_VSX) || (type) == LARX)
53#define OP_IS_STORE(type) ((STORE <= (type) && (type) <= STORE_VSX) || (type) == STCX)
54#define OP_IS_LOAD_STORE(type) (LOAD <= (type) && (type) <= STCX)
55
56
57#define SETREG 0x20
58#define SETCC 0x40
59#define SETXER 0x80
60
61
62#define SETLK 0x20
63#define BRTAKEN 0x40
64#define DECCTR 0x80
65
66
67#define SIGNEXT 0x20
68#define UPDATE 0x40
69#define BYTEREV 0x80
70#define FPCONV 0x100
71
72
73#define BARRIER_MASK 0xe0
74#define BARRIER_SYNC 0x00
75#define BARRIER_ISYNC 0x20
76#define BARRIER_EIEIO 0x40
77#define BARRIER_LWSYNC 0x60
78#define BARRIER_PTESYNC 0x80
79
80
81#define CACHEOP_MASK 0x700
82#define DCBST 0
83#define DCBF 0x100
84#define DCBTST 0x200
85#define DCBT 0x300
86#define ICBI 0x400
87#define DCBZ 0x500
88
89
90#define VSX_FPCONV 1
91#define VSX_SPLAT 2
92#define VSX_LDLEFT 4
93#define VSX_CHECK_VEC 8
94
95
96#define PREFIXED 0x800
97
98
99#define SIZE(n) ((n) << 12)
100#define GETSIZE(w) ((w) >> 12)
101
102#define GETTYPE(t) ((t) & INSTR_TYPE_MASK)
103#define GETLENGTH(t) (((t) & PREFIXED) ? 8 : 4)
104
105#define MKOP(t, f, s) ((t) | (f) | SIZE(s))
106
107
108#define GET_PREFIX_RA(i) (((i) >> 16) & 0x1f)
109#define GET_PREFIX_R(i) ((i) & (1ul << 20))
110
111extern s32 patch__exec_instr;
112
113struct instruction_op {
114 int type;
115 int reg;
116 unsigned long val;
117
118 unsigned long ea;
119 int update_reg;
120
121 int spr;
122 u32 ccval;
123 u32 xerval;
124 u8 element_size;
125 u8 vsx_flags;
126};
127
128union vsx_reg {
129 u8 b[16];
130 u16 h[8];
131 u32 w[4];
132 unsigned long d[2];
133 float fp[4];
134 double dp[2];
135 __vector128 v;
136};
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147extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
148 struct ppc_inst instr);
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154void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op);
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165extern int emulate_step(struct pt_regs *regs, struct ppc_inst instr);
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174extern int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op);
175
176extern void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
177 const void *mem, bool cross_endian);
178extern void emulate_vsx_store(struct instruction_op *op,
179 const union vsx_reg *reg, void *mem,
180 bool cross_endian);
181extern int emulate_dcbz(unsigned long ea, struct pt_regs *regs);
182