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12#include <linux/compat.h>
13#include <linux/signal.h>
14#include <linux/sched.h>
15#include <linux/kernel.h>
16#include <linux/errno.h>
17#include <linux/string.h>
18#include <linux/types.h>
19#include <linux/mman.h>
20#include <linux/mm.h>
21#include <linux/suspend.h>
22#include <linux/hrtimer.h>
23#ifdef CONFIG_PPC64
24#include <linux/time.h>
25#include <linux/hardirq.h>
26#endif
27#include <linux/kbuild.h>
28
29#include <asm/io.h>
30#include <asm/page.h>
31#include <asm/processor.h>
32#include <asm/cputable.h>
33#include <asm/thread_info.h>
34#include <asm/rtas.h>
35#include <asm/vdso_datapage.h>
36#include <asm/dbell.h>
37#ifdef CONFIG_PPC64
38#include <asm/paca.h>
39#include <asm/lppaca.h>
40#include <asm/cache.h>
41#include <asm/mmu.h>
42#include <asm/hvcall.h>
43#include <asm/xics.h>
44#endif
45#ifdef CONFIG_PPC_POWERNV
46#include <asm/opal.h>
47#endif
48#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
49#include <linux/kvm_host.h>
50#endif
51#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
52#include <asm/kvm_book3s.h>
53#include <asm/kvm_ppc.h>
54#endif
55
56#ifdef CONFIG_PPC32
57#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
58#include "head_booke.h"
59#endif
60#endif
61
62#if defined(CONFIG_PPC_FSL_BOOK3E)
63#include "../mm/mmu_decl.h"
64#endif
65
66#ifdef CONFIG_PPC_8xx
67#include <asm/fixmap.h>
68#endif
69
70#ifdef CONFIG_XMON
71#include "../xmon/xmon_bpts.h"
72#endif
73
74#define STACK_PT_REGS_OFFSET(sym, val) \
75 DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val))
76
77int main(void)
78{
79 OFFSET(THREAD, task_struct, thread);
80 OFFSET(MM, task_struct, mm);
81#ifdef CONFIG_STACKPROTECTOR
82 OFFSET(TASK_CANARY, task_struct, stack_canary);
83#ifdef CONFIG_PPC64
84 OFFSET(PACA_CANARY, paca_struct, canary);
85#endif
86#endif
87#ifdef CONFIG_PPC32
88#ifdef CONFIG_PPC_RTAS
89 OFFSET(RTAS_SP, thread_struct, rtas_sp);
90#endif
91#endif
92 OFFSET(TASK_STACK, task_struct, stack);
93#ifdef CONFIG_SMP
94 OFFSET(TASK_CPU, task_struct, thread_info.cpu);
95#endif
96
97#ifdef CONFIG_LIVEPATCH
98 OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
99#endif
100
101 OFFSET(KSP, thread_struct, ksp);
102 OFFSET(PT_REGS, thread_struct, regs);
103#ifdef CONFIG_BOOKE
104 OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
105#endif
106#ifdef CONFIG_PPC_FPU
107 OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
108 OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr);
109 OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
110#endif
111 OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
112 OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
113#ifdef CONFIG_ALTIVEC
114 OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr);
115 OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
116 OFFSET(THREAD_USED_VR, thread_struct, used_vr);
117 OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
118 OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
119#endif
120#ifdef CONFIG_VSX
121 OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
122#endif
123#ifdef CONFIG_PPC64
124 OFFSET(KSP_VSID, thread_struct, ksp_vsid);
125#else
126 OFFSET(PGDIR, thread_struct, pgdir);
127 OFFSET(SRR0, thread_struct, srr0);
128 OFFSET(SRR1, thread_struct, srr1);
129 OFFSET(DAR, thread_struct, dar);
130 OFFSET(DSISR, thread_struct, dsisr);
131#ifdef CONFIG_PPC_BOOK3S_32
132 OFFSET(THR0, thread_struct, r0);
133 OFFSET(THR3, thread_struct, r3);
134 OFFSET(THR4, thread_struct, r4);
135 OFFSET(THR5, thread_struct, r5);
136 OFFSET(THR6, thread_struct, r6);
137 OFFSET(THR8, thread_struct, r8);
138 OFFSET(THR9, thread_struct, r9);
139 OFFSET(THR11, thread_struct, r11);
140 OFFSET(THLR, thread_struct, lr);
141 OFFSET(THCTR, thread_struct, ctr);
142#endif
143#ifdef CONFIG_SPE
144 OFFSET(THREAD_EVR0, thread_struct, evr[0]);
145 OFFSET(THREAD_ACC, thread_struct, acc);
146 OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
147#endif
148#endif
149#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
150 OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
151#endif
152#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
153 OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
154#endif
155
156#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
157 OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
158 OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
159 OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
160 OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
161 OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
162 OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
163 OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
164 OFFSET(THREAD_TM_AMR, thread_struct, tm_amr);
165 OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
166 OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr);
167 OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
168 OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr);
169
170 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
171 sizeof(struct pt_regs) + 16);
172#endif
173
174 OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
175
176#ifdef CONFIG_PPC64
177 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
178 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
179
180 OFFSET(PACAPACAINDEX, paca_struct, paca_index);
181 OFFSET(PACAPROCSTART, paca_struct, cpu_start);
182 OFFSET(PACAKSAVE, paca_struct, kstack);
183 OFFSET(PACACURRENT, paca_struct, __current);
184 DEFINE(PACA_THREAD_INFO, offsetof(struct paca_struct, __current) +
185 offsetof(struct task_struct, thread_info));
186 OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
187 OFFSET(PACAR1, paca_struct, saved_r1);
188 OFFSET(PACATOC, paca_struct, kernel_toc);
189 OFFSET(PACAKBASE, paca_struct, kernelbase);
190 OFFSET(PACAKMSR, paca_struct, kernel_msr);
191#ifdef CONFIG_PPC_BOOK3S_64
192 OFFSET(PACAHSRR_VALID, paca_struct, hsrr_valid);
193 OFFSET(PACASRR_VALID, paca_struct, srr_valid);
194#endif
195 OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask);
196 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
197 OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled);
198
199#ifdef CONFIG_PPC_BOOK3E
200 OFFSET(PACAPGD, paca_struct, pgd);
201 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
202 OFFSET(PACA_EXGEN, paca_struct, exgen);
203 OFFSET(PACA_EXTLB, paca_struct, extlb);
204 OFFSET(PACA_EXMC, paca_struct, exmc);
205 OFFSET(PACA_EXCRIT, paca_struct, excrit);
206 OFFSET(PACA_EXDBG, paca_struct, exdbg);
207 OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
208 OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
209 OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
210 OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
211
212 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
213 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
214 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
215#endif
216
217#ifdef CONFIG_PPC_BOOK3S_64
218 OFFSET(PACA_EXGEN, paca_struct, exgen);
219 OFFSET(PACA_EXMC, paca_struct, exmc);
220 OFFSET(PACA_EXNMI, paca_struct, exnmi);
221 OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
222 OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
223 OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
224 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
225 OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
226#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
227 OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use);
228#endif
229 OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
230#endif
231 OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
232#ifdef CONFIG_PPC_BOOK3S_64
233 OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
234 OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp);
235 OFFSET(PACA_IN_MCE, paca_struct, in_mce);
236 OFFSET(PACA_IN_NMI, paca_struct, in_nmi);
237 OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area);
238 OFFSET(PACA_EXRFI, paca_struct, exrfi);
239 OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size);
240
241#endif
242 OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
243 OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
244 OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
245#ifdef CONFIG_PPC64
246 OFFSET(PACA_EXIT_SAVE_R1, paca_struct, exit_save_r1);
247#endif
248#ifdef CONFIG_PPC_BOOK3E
249 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
250#endif
251 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
252#else
253#endif
254
255
256 OFFSET(RTASBASE, rtas_t, base);
257 OFFSET(RTASENTRY, rtas_t, entry);
258
259
260 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
261 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_WITH_PT_REGS);
262 STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
263 STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
264 STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
265 STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
266 STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
267 STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
268 STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
269 STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
270 STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
271 STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
272 STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
273 STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
274 STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
275 STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
276
277
278
279
280 STACK_PT_REGS_OFFSET(_NIP, nip);
281 STACK_PT_REGS_OFFSET(_MSR, msr);
282 STACK_PT_REGS_OFFSET(_CTR, ctr);
283 STACK_PT_REGS_OFFSET(_LINK, link);
284 STACK_PT_REGS_OFFSET(_CCR, ccr);
285 STACK_PT_REGS_OFFSET(_XER, xer);
286 STACK_PT_REGS_OFFSET(_DAR, dar);
287 STACK_PT_REGS_OFFSET(_DEAR, dear);
288 STACK_PT_REGS_OFFSET(_DSISR, dsisr);
289 STACK_PT_REGS_OFFSET(_ESR, esr);
290 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
291 STACK_PT_REGS_OFFSET(RESULT, result);
292 STACK_PT_REGS_OFFSET(_TRAP, trap);
293#ifdef CONFIG_PPC64
294 STACK_PT_REGS_OFFSET(SOFTE, softe);
295 STACK_PT_REGS_OFFSET(_PPR, ppr);
296#endif
297
298#ifdef CONFIG_PPC_PKEY
299 STACK_PT_REGS_OFFSET(STACK_REGS_AMR, amr);
300 STACK_PT_REGS_OFFSET(STACK_REGS_IAMR, iamr);
301#endif
302
303#if defined(CONFIG_PPC32) && defined(CONFIG_BOOKE)
304 STACK_PT_REGS_OFFSET(MAS0, mas0);
305
306 STACK_PT_REGS_OFFSET(MMUCR, mas0);
307 STACK_PT_REGS_OFFSET(MAS1, mas1);
308 STACK_PT_REGS_OFFSET(MAS2, mas2);
309 STACK_PT_REGS_OFFSET(MAS3, mas3);
310 STACK_PT_REGS_OFFSET(MAS6, mas6);
311 STACK_PT_REGS_OFFSET(MAS7, mas7);
312 STACK_PT_REGS_OFFSET(_SRR0, srr0);
313 STACK_PT_REGS_OFFSET(_SRR1, srr1);
314 STACK_PT_REGS_OFFSET(_CSRR0, csrr0);
315 STACK_PT_REGS_OFFSET(_CSRR1, csrr1);
316 STACK_PT_REGS_OFFSET(_DSRR0, dsrr0);
317 STACK_PT_REGS_OFFSET(_DSRR1, dsrr1);
318#endif
319
320
321 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
322 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
323 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
324
325 OFFSET(pbe_address, pbe, address);
326 OFFSET(pbe_orig_address, pbe, orig_address);
327 OFFSET(pbe_next, pbe, next);
328
329#ifndef CONFIG_PPC64
330 DEFINE(TASK_SIZE, TASK_SIZE);
331 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
332#endif
333
334
335 OFFSET(VDSO_DATA_OFFSET, vdso_arch_data, data);
336 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_arch_data, tb_ticks_per_sec);
337#ifdef CONFIG_PPC64
338 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_arch_data, icache_block_size);
339 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_arch_data, dcache_block_size);
340 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_arch_data, icache_log_block_size);
341 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_arch_data, dcache_log_block_size);
342 OFFSET(CFG_SYSCALL_MAP64, vdso_arch_data, syscall_map);
343 OFFSET(CFG_SYSCALL_MAP32, vdso_arch_data, compat_syscall_map);
344#else
345 OFFSET(CFG_SYSCALL_MAP32, vdso_arch_data, syscall_map);
346#endif
347
348#ifdef CONFIG_BUG
349 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
350#endif
351
352#ifdef CONFIG_KVM
353 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
354 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
355 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
356 OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr);
357 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
358 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
359#ifdef CONFIG_ALTIVEC
360 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
361#endif
362 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
363 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
364 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
365#ifdef CONFIG_PPC_BOOK3S
366 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
367#endif
368 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
369 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
370#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
371 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
372 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
373 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
374 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
375 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
376 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
377 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
378#endif
379#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
380 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
381 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
382 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
383 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
384 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
385 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
386 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
387 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
388 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
389 OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
390 OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
391#endif
392 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
393 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
394 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
395 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
396 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
397 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
398 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
399 OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
400 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
401 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
402#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
403 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
404#endif
405
406 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
407 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
408 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
409 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
410 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
411 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
412
413 OFFSET(VCPU_KVM, kvm_vcpu, kvm);
414 OFFSET(KVM_LPID, kvm, arch.lpid);
415
416
417#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
418 OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets);
419 OFFSET(KVM_SDR1, kvm, arch.sdr1);
420 OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
421 OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
422 OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
423 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
424 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
425 OFFSET(KVM_RADIX, kvm, arch.radix);
426 OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest);
427 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
428 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
429 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
430 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
431 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
432 OFFSET(VCPU_NESTED, kvm_vcpu, arch.nested);
433 OFFSET(VCPU_CPU, kvm_vcpu, cpu);
434 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
435#endif
436#ifdef CONFIG_PPC_BOOK3S
437 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
438 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
439 OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
440 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
441 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
442 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
443 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
444 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
445 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
446 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
447 OFFSET(VCPU_DAWR0, kvm_vcpu, arch.dawr0);
448 OFFSET(VCPU_DAWRX0, kvm_vcpu, arch.dawrx0);
449 OFFSET(VCPU_DAWR1, kvm_vcpu, arch.dawr1);
450 OFFSET(VCPU_DAWRX1, kvm_vcpu, arch.dawrx1);
451 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
452 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
453 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
454 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
455 OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
456 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
457 OFFSET(VCPU_IRQ_PENDING, kvm_vcpu, arch.irq_pending);
458 OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request);
459 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
460 OFFSET(VCPU_MMCRA, kvm_vcpu, arch.mmcra);
461 OFFSET(VCPU_MMCRS, kvm_vcpu, arch.mmcrs);
462 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
463 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
464 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
465 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
466 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
467 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
468 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
469 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
470 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
471 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
472 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
473 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
474 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
475 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
476 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
477 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
478 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
479 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
480 OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
481 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
482 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
483 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
484 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
485 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
486 OFFSET(VCPU_TID, kvm_vcpu, arch.tid);
487 OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr);
488 OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr);
489 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
490 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
491 OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
492 OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
493 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
494 OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied);
495 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
496 OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
497 OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
498 OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
499 OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
500 OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
501 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
502#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
503 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
504 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
505 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
506 OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr);
507 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
508 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
509 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
510 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
511 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
512 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
513 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
514 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
515 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
516 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
517 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
518 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
519#endif
520
521#ifdef CONFIG_PPC_BOOK3S_64
522#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
523 OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
524# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
525#else
526# define SVCPU_FIELD(x, f)
527#endif
528# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
529#else
530# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
531# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
532#endif
533
534 SVCPU_FIELD(SVCPU_CR, cr);
535 SVCPU_FIELD(SVCPU_XER, xer);
536 SVCPU_FIELD(SVCPU_CTR, ctr);
537 SVCPU_FIELD(SVCPU_LR, lr);
538 SVCPU_FIELD(SVCPU_PC, pc);
539 SVCPU_FIELD(SVCPU_R0, gpr[0]);
540 SVCPU_FIELD(SVCPU_R1, gpr[1]);
541 SVCPU_FIELD(SVCPU_R2, gpr[2]);
542 SVCPU_FIELD(SVCPU_R3, gpr[3]);
543 SVCPU_FIELD(SVCPU_R4, gpr[4]);
544 SVCPU_FIELD(SVCPU_R5, gpr[5]);
545 SVCPU_FIELD(SVCPU_R6, gpr[6]);
546 SVCPU_FIELD(SVCPU_R7, gpr[7]);
547 SVCPU_FIELD(SVCPU_R8, gpr[8]);
548 SVCPU_FIELD(SVCPU_R9, gpr[9]);
549 SVCPU_FIELD(SVCPU_R10, gpr[10]);
550 SVCPU_FIELD(SVCPU_R11, gpr[11]);
551 SVCPU_FIELD(SVCPU_R12, gpr[12]);
552 SVCPU_FIELD(SVCPU_R13, gpr[13]);
553 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
554 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
555 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
556 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
557#ifdef CONFIG_PPC_BOOK3S_32
558 SVCPU_FIELD(SVCPU_SR, sr);
559#endif
560#ifdef CONFIG_PPC64
561 SVCPU_FIELD(SVCPU_SLB, slb);
562 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
563 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
564#endif
565
566 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
567 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
568 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
569 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
570 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
571 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
572 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
573 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
574 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
575 HSTATE_FIELD(HSTATE_NAPPING, napping);
576
577#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
578 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
579 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
580 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
581 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
582 HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys);
583 HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt);
584 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
585 HSTATE_FIELD(HSTATE_PTID, ptid);
586 HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend);
587 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
588 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
589 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
590 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
591 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
592 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
593 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
594 HSTATE_FIELD(HSTATE_MMCR3, host_mmcr[7]);
595 HSTATE_FIELD(HSTATE_SIER2, host_mmcr[8]);
596 HSTATE_FIELD(HSTATE_SIER3, host_mmcr[9]);
597 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
598 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
599 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
600 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
601 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
602 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
603 HSTATE_FIELD(HSTATE_PURR, host_purr);
604 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
605 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
606 HSTATE_FIELD(HSTATE_DABR, dabr);
607 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
608 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
609 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
610 OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
611 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
612 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
613 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
614 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
615#endif
616
617#ifdef CONFIG_PPC_BOOK3S_64
618 HSTATE_FIELD(HSTATE_CFAR, cfar);
619 HSTATE_FIELD(HSTATE_PPR, ppr);
620 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
621#endif
622
623#else
624 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
625 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
626 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
627 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
628 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
629 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
630 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
631 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
632 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
633 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
634#endif
635#endif
636
637#ifdef CONFIG_KVM_GUEST
638 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
639 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
640 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
641 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
642 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
643 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
644 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
645#endif
646
647#ifdef CONFIG_44x
648 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
649 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
650#endif
651#ifdef CONFIG_PPC_FSL_BOOK3E
652 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
653 OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
654 OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
655 OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
656 OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
657 OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
658#endif
659
660#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
661 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
662 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
663 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
664 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
665#endif
666
667#ifdef CONFIG_KVM_BOOKE_HV
668 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
669 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
670#endif
671
672#ifdef CONFIG_KVM_XICS
673 DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu,
674 arch.xive_saved_state));
675 DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu,
676 arch.xive_cam_word));
677 DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed));
678 DEFINE(VCPU_XIVE_ESC_ON, offsetof(struct kvm_vcpu, arch.xive_esc_on));
679 DEFINE(VCPU_XIVE_ESC_RADDR, offsetof(struct kvm_vcpu, arch.xive_esc_raddr));
680 DEFINE(VCPU_XIVE_ESC_VADDR, offsetof(struct kvm_vcpu, arch.xive_esc_vaddr));
681#endif
682
683#ifdef CONFIG_KVM_EXIT_TIMING
684 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
685 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
686 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
687 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
688#endif
689
690 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
691
692#ifdef CONFIG_PPC_8xx
693 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
694#endif
695
696#ifdef CONFIG_XMON
697 DEFINE(BPT_SIZE, BPT_SIZE);
698#endif
699
700 return 0;
701}
702
