1
2
3
4
5
6
7#include <linux/bitops.h>
8#include <linux/compat.h>
9#include <linux/cpu.h>
10#include <linux/mman.h>
11#include <linux/nospec.h>
12#include <linux/pkeys.h>
13#include <linux/seq_file.h>
14#include <linux/proc_fs.h>
15#include <linux/vmalloc.h>
16
17#include <asm/fpu/api.h>
18#include <asm/fpu/regset.h>
19#include <asm/fpu/signal.h>
20#include <asm/fpu/xcr.h>
21
22#include <asm/tlbflush.h>
23#include <asm/prctl.h>
24#include <asm/elf.h>
25
26#include "context.h"
27#include "internal.h"
28#include "legacy.h"
29#include "xstate.h"
30
31#define for_each_extended_xfeature(bit, mask) \
32 (bit) = FIRST_EXTENDED_XFEATURE; \
33 for_each_set_bit_from(bit, (unsigned long *)&(mask), 8 * sizeof(mask))
34
35
36
37
38
39
40static const char *xfeature_names[] =
41{
42 "x87 floating point registers" ,
43 "SSE registers" ,
44 "AVX registers" ,
45 "MPX bounds registers" ,
46 "MPX CSR" ,
47 "AVX-512 opmask" ,
48 "AVX-512 Hi256" ,
49 "AVX-512 ZMM_Hi256" ,
50 "Processor Trace (unused)" ,
51 "Protection Keys User registers",
52 "PASID state",
53 "unknown xstate feature" ,
54 "unknown xstate feature" ,
55 "unknown xstate feature" ,
56 "unknown xstate feature" ,
57 "unknown xstate feature" ,
58 "unknown xstate feature" ,
59 "AMX Tile config" ,
60 "AMX Tile data" ,
61 "unknown xstate feature" ,
62};
63
64static unsigned short xsave_cpuid_features[] __initdata = {
65 [XFEATURE_FP] = X86_FEATURE_FPU,
66 [XFEATURE_SSE] = X86_FEATURE_XMM,
67 [XFEATURE_YMM] = X86_FEATURE_AVX,
68 [XFEATURE_BNDREGS] = X86_FEATURE_MPX,
69 [XFEATURE_BNDCSR] = X86_FEATURE_MPX,
70 [XFEATURE_OPMASK] = X86_FEATURE_AVX512F,
71 [XFEATURE_ZMM_Hi256] = X86_FEATURE_AVX512F,
72 [XFEATURE_Hi16_ZMM] = X86_FEATURE_AVX512F,
73 [XFEATURE_PT_UNIMPLEMENTED_SO_FAR] = X86_FEATURE_INTEL_PT,
74 [XFEATURE_PKRU] = X86_FEATURE_PKU,
75 [XFEATURE_PASID] = X86_FEATURE_ENQCMD,
76 [XFEATURE_XTILE_CFG] = X86_FEATURE_AMX_TILE,
77 [XFEATURE_XTILE_DATA] = X86_FEATURE_AMX_TILE,
78};
79
80static unsigned int xstate_offsets[XFEATURE_MAX] __ro_after_init =
81 { [ 0 ... XFEATURE_MAX - 1] = -1};
82static unsigned int xstate_sizes[XFEATURE_MAX] __ro_after_init =
83 { [ 0 ... XFEATURE_MAX - 1] = -1};
84static unsigned int xstate_comp_offsets[XFEATURE_MAX] __ro_after_init =
85 { [ 0 ... XFEATURE_MAX - 1] = -1};
86static unsigned int xstate_supervisor_only_offsets[XFEATURE_MAX] __ro_after_init =
87 { [ 0 ... XFEATURE_MAX - 1] = -1};
88
89
90
91
92
93
94int cpu_has_xfeatures(u64 xfeatures_needed, const char **feature_name)
95{
96 u64 xfeatures_missing = xfeatures_needed & ~fpu_kernel_cfg.max_features;
97
98 if (unlikely(feature_name)) {
99 long xfeature_idx, max_idx;
100 u64 xfeatures_print;
101
102
103
104
105
106
107
108 if (xfeatures_missing)
109 xfeatures_print = xfeatures_missing;
110 else
111 xfeatures_print = xfeatures_needed;
112
113 xfeature_idx = fls64(xfeatures_print)-1;
114 max_idx = ARRAY_SIZE(xfeature_names)-1;
115 xfeature_idx = min(xfeature_idx, max_idx);
116
117 *feature_name = xfeature_names[xfeature_idx];
118 }
119
120 if (xfeatures_missing)
121 return 0;
122
123 return 1;
124}
125EXPORT_SYMBOL_GPL(cpu_has_xfeatures);
126
127static bool xfeature_is_supervisor(int xfeature_nr)
128{
129
130
131
132
133
134 u32 eax, ebx, ecx, edx;
135
136 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
137 return ecx & 1;
138}
139
140
141
142
143
144void fpu__init_cpu_xstate(void)
145{
146 if (!boot_cpu_has(X86_FEATURE_XSAVE) || !fpu_kernel_cfg.max_features)
147 return;
148
149 cr4_set_bits(X86_CR4_OSXSAVE);
150
151
152
153
154
155
156
157 if (cpu_feature_enabled(X86_FEATURE_XFD))
158 wrmsrl(MSR_IA32_XFD, init_fpstate.xfd);
159
160
161
162
163
164
165 xsetbv(XCR_XFEATURE_ENABLED_MASK, fpu_user_cfg.max_features);
166
167
168
169
170 if (boot_cpu_has(X86_FEATURE_XSAVES)) {
171 wrmsrl(MSR_IA32_XSS, xfeatures_mask_supervisor() |
172 xfeatures_mask_independent());
173 }
174}
175
176static bool xfeature_enabled(enum xfeature xfeature)
177{
178 return fpu_kernel_cfg.max_features & BIT_ULL(xfeature);
179}
180
181
182
183
184
185static void __init setup_xstate_features(void)
186{
187 u32 eax, ebx, ecx, edx, i;
188
189 unsigned int last_good_offset = offsetof(struct xregs_state,
190 extended_state_area);
191
192
193
194
195
196 xstate_offsets[XFEATURE_FP] = 0;
197 xstate_sizes[XFEATURE_FP] = offsetof(struct fxregs_state,
198 xmm_space);
199
200 xstate_offsets[XFEATURE_SSE] = xstate_sizes[XFEATURE_FP];
201 xstate_sizes[XFEATURE_SSE] = sizeof_field(struct fxregs_state,
202 xmm_space);
203
204 for_each_extended_xfeature(i, fpu_kernel_cfg.max_features) {
205 cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);
206
207 xstate_sizes[i] = eax;
208
209
210
211
212
213 if (xfeature_is_supervisor(i))
214 continue;
215
216 xstate_offsets[i] = ebx;
217
218
219
220
221
222
223 WARN_ONCE(last_good_offset > xstate_offsets[i],
224 "x86/fpu: misordered xstate at %d\n", last_good_offset);
225
226 last_good_offset = xstate_offsets[i];
227 }
228}
229
230static void __init print_xstate_feature(u64 xstate_mask)
231{
232 const char *feature_name;
233
234 if (cpu_has_xfeatures(xstate_mask, &feature_name))
235 pr_info("x86/fpu: Supporting XSAVE feature 0x%03Lx: '%s'\n", xstate_mask, feature_name);
236}
237
238
239
240
241static void __init print_xstate_features(void)
242{
243 print_xstate_feature(XFEATURE_MASK_FP);
244 print_xstate_feature(XFEATURE_MASK_SSE);
245 print_xstate_feature(XFEATURE_MASK_YMM);
246 print_xstate_feature(XFEATURE_MASK_BNDREGS);
247 print_xstate_feature(XFEATURE_MASK_BNDCSR);
248 print_xstate_feature(XFEATURE_MASK_OPMASK);
249 print_xstate_feature(XFEATURE_MASK_ZMM_Hi256);
250 print_xstate_feature(XFEATURE_MASK_Hi16_ZMM);
251 print_xstate_feature(XFEATURE_MASK_PKRU);
252 print_xstate_feature(XFEATURE_MASK_PASID);
253 print_xstate_feature(XFEATURE_MASK_XTILE_CFG);
254 print_xstate_feature(XFEATURE_MASK_XTILE_DATA);
255}
256
257
258
259
260
261#define CHECK_XFEATURE(nr) do { \
262 WARN_ON(nr < FIRST_EXTENDED_XFEATURE); \
263 WARN_ON(nr >= XFEATURE_MAX); \
264} while (0)
265
266
267
268
269
270static int xfeature_is_aligned(int xfeature_nr)
271{
272 u32 eax, ebx, ecx, edx;
273
274 CHECK_XFEATURE(xfeature_nr);
275
276 if (!xfeature_enabled(xfeature_nr)) {
277 WARN_ONCE(1, "Checking alignment of disabled xfeature %d\n",
278 xfeature_nr);
279 return 0;
280 }
281
282 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
283
284
285
286
287
288 return !!(ecx & 2);
289}
290
291
292
293
294
295
296static void __init setup_xstate_comp_offsets(void)
297{
298 unsigned int next_offset;
299 int i;
300
301
302
303
304
305
306 xstate_comp_offsets[XFEATURE_FP] = 0;
307 xstate_comp_offsets[XFEATURE_SSE] = offsetof(struct fxregs_state,
308 xmm_space);
309
310 if (!cpu_feature_enabled(X86_FEATURE_XSAVES)) {
311 for_each_extended_xfeature(i, fpu_kernel_cfg.max_features)
312 xstate_comp_offsets[i] = xstate_offsets[i];
313 return;
314 }
315
316 next_offset = FXSAVE_SIZE + XSAVE_HDR_SIZE;
317
318 for_each_extended_xfeature(i, fpu_kernel_cfg.max_features) {
319 if (xfeature_is_aligned(i))
320 next_offset = ALIGN(next_offset, 64);
321
322 xstate_comp_offsets[i] = next_offset;
323 next_offset += xstate_sizes[i];
324 }
325}
326
327
328
329
330
331
332
333
334
335static void __init setup_supervisor_only_offsets(void)
336{
337 unsigned int next_offset;
338 int i;
339
340 next_offset = FXSAVE_SIZE + XSAVE_HDR_SIZE;
341
342 for_each_extended_xfeature(i, fpu_kernel_cfg.max_features) {
343 if (!xfeature_is_supervisor(i))
344 continue;
345
346 if (xfeature_is_aligned(i))
347 next_offset = ALIGN(next_offset, 64);
348
349 xstate_supervisor_only_offsets[i] = next_offset;
350 next_offset += xstate_sizes[i];
351 }
352}
353
354
355
356
357static void __init print_xstate_offset_size(void)
358{
359 int i;
360
361 for_each_extended_xfeature(i, fpu_kernel_cfg.max_features) {
362 pr_info("x86/fpu: xstate_offset[%d]: %4d, xstate_sizes[%d]: %4d\n",
363 i, xstate_comp_offsets[i], i, xstate_sizes[i]);
364 }
365}
366
367
368
369
370
371static __init void os_xrstor_booting(struct xregs_state *xstate)
372{
373 u64 mask = fpu_kernel_cfg.max_features & XFEATURE_MASK_FPSTATE;
374 u32 lmask = mask;
375 u32 hmask = mask >> 32;
376 int err;
377
378 if (cpu_feature_enabled(X86_FEATURE_XSAVES))
379 XSTATE_OP(XRSTORS, xstate, lmask, hmask, err);
380 else
381 XSTATE_OP(XRSTOR, xstate, lmask, hmask, err);
382
383
384
385
386
387 WARN_ON_FPU(err);
388}
389
390
391
392
393
394
395
396
397#define XFEATURES_INIT_FPSTATE_HANDLED \
398 (XFEATURE_MASK_FP | \
399 XFEATURE_MASK_SSE | \
400 XFEATURE_MASK_YMM | \
401 XFEATURE_MASK_OPMASK | \
402 XFEATURE_MASK_ZMM_Hi256 | \
403 XFEATURE_MASK_Hi16_ZMM | \
404 XFEATURE_MASK_PKRU | \
405 XFEATURE_MASK_BNDREGS | \
406 XFEATURE_MASK_BNDCSR | \
407 XFEATURE_MASK_PASID | \
408 XFEATURE_MASK_XTILE)
409
410
411
412
413static void __init setup_init_fpu_buf(void)
414{
415 BUILD_BUG_ON((XFEATURE_MASK_USER_SUPPORTED |
416 XFEATURE_MASK_SUPERVISOR_SUPPORTED) !=
417 XFEATURES_INIT_FPSTATE_HANDLED);
418
419 if (!boot_cpu_has(X86_FEATURE_XSAVE))
420 return;
421
422 setup_xstate_features();
423 print_xstate_features();
424
425 xstate_init_xcomp_bv(&init_fpstate.regs.xsave, fpu_kernel_cfg.max_features);
426
427
428
429
430 os_xrstor_booting(&init_fpstate.regs.xsave);
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448 fxsave(&init_fpstate.regs.fxsave);
449}
450
451static int xfeature_uncompacted_offset(int xfeature_nr)
452{
453 u32 eax, ebx, ecx, edx;
454
455
456
457
458
459
460 if (XFEATURE_MASK_SUPERVISOR_ALL & BIT_ULL(xfeature_nr)) {
461 WARN_ONCE(1, "No fixed offset for xstate %d\n", xfeature_nr);
462 return -1;
463 }
464
465 CHECK_XFEATURE(xfeature_nr);
466 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
467 return ebx;
468}
469
470int xfeature_size(int xfeature_nr)
471{
472 u32 eax, ebx, ecx, edx;
473
474 CHECK_XFEATURE(xfeature_nr);
475 cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx);
476 return eax;
477}
478
479
480static int validate_user_xstate_header(const struct xstate_header *hdr,
481 struct fpstate *fpstate)
482{
483
484 if (hdr->xfeatures & ~fpstate->user_xfeatures)
485 return -EINVAL;
486
487
488 if (hdr->xcomp_bv)
489 return -EINVAL;
490
491
492
493
494
495 BUILD_BUG_ON(sizeof(hdr->reserved) != 48);
496
497
498 if (memchr_inv(hdr->reserved, 0, sizeof(hdr->reserved)))
499 return -EINVAL;
500
501 return 0;
502}
503
504static void __init __xstate_dump_leaves(void)
505{
506 int i;
507 u32 eax, ebx, ecx, edx;
508 static int should_dump = 1;
509
510 if (!should_dump)
511 return;
512 should_dump = 0;
513
514
515
516
517 for (i = 0; i < XFEATURE_MAX + 10; i++) {
518 cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx);
519 pr_warn("CPUID[%02x, %02x]: eax=%08x ebx=%08x ecx=%08x edx=%08x\n",
520 XSTATE_CPUID, i, eax, ebx, ecx, edx);
521 }
522}
523
524#define XSTATE_WARN_ON(x) do { \
525 if (WARN_ONCE(x, "XSAVE consistency problem, dumping leaves")) { \
526 __xstate_dump_leaves(); \
527 } \
528} while (0)
529
530#define XCHECK_SZ(sz, nr, nr_macro, __struct) do { \
531 if ((nr == nr_macro) && \
532 WARN_ONCE(sz != sizeof(__struct), \
533 "%s: struct is %zu bytes, cpu state %d bytes\n", \
534 __stringify(nr_macro), sizeof(__struct), sz)) { \
535 __xstate_dump_leaves(); \
536 } \
537} while (0)
538
539
540
541
542
543
544
545
546
547
548
549
550static int __init check_xtile_data_against_struct(int size)
551{
552 u32 max_palid, palid, state_size;
553 u32 eax, ebx, ecx, edx;
554 u16 max_tile;
555
556
557
558
559
560 cpuid_count(TILE_CPUID, 0, &max_palid, &ebx, &ecx, &edx);
561
562
563
564
565
566 for (palid = 1, max_tile = 0; palid <= max_palid; palid++) {
567 u16 tile_size, max;
568
569
570
571
572
573
574 cpuid_count(TILE_CPUID, palid, &eax, &ebx, &edx, &edx);
575 tile_size = eax >> 16;
576 max = ebx >> 16;
577
578 if (tile_size != sizeof(struct xtile_data)) {
579 pr_err("%s: struct is %zu bytes, cpu xtile %d bytes\n",
580 __stringify(XFEATURE_XTILE_DATA),
581 sizeof(struct xtile_data), tile_size);
582 __xstate_dump_leaves();
583 return -EINVAL;
584 }
585
586 if (max > max_tile)
587 max_tile = max;
588 }
589
590 state_size = sizeof(struct xtile_data) * max_tile;
591 if (size != state_size) {
592 pr_err("%s: calculated size is %u bytes, cpu state %d bytes\n",
593 __stringify(XFEATURE_XTILE_DATA), state_size, size);
594 __xstate_dump_leaves();
595 return -EINVAL;
596 }
597 return 0;
598}
599
600
601
602
603
604
605static bool __init check_xstate_against_struct(int nr)
606{
607
608
609
610 int sz = xfeature_size(nr);
611
612
613
614
615 XCHECK_SZ(sz, nr, XFEATURE_YMM, struct ymmh_struct);
616 XCHECK_SZ(sz, nr, XFEATURE_BNDREGS, struct mpx_bndreg_state);
617 XCHECK_SZ(sz, nr, XFEATURE_BNDCSR, struct mpx_bndcsr_state);
618 XCHECK_SZ(sz, nr, XFEATURE_OPMASK, struct avx_512_opmask_state);
619 XCHECK_SZ(sz, nr, XFEATURE_ZMM_Hi256, struct avx_512_zmm_uppers_state);
620 XCHECK_SZ(sz, nr, XFEATURE_Hi16_ZMM, struct avx_512_hi16_state);
621 XCHECK_SZ(sz, nr, XFEATURE_PKRU, struct pkru_state);
622 XCHECK_SZ(sz, nr, XFEATURE_PASID, struct ia32_pasid_state);
623 XCHECK_SZ(sz, nr, XFEATURE_XTILE_CFG, struct xtile_cfg);
624
625
626 if (nr == XFEATURE_XTILE_DATA)
627 check_xtile_data_against_struct(sz);
628
629
630
631
632
633
634 if ((nr < XFEATURE_YMM) ||
635 (nr >= XFEATURE_MAX) ||
636 (nr == XFEATURE_PT_UNIMPLEMENTED_SO_FAR) ||
637 ((nr >= XFEATURE_RSRVD_COMP_11) && (nr <= XFEATURE_RSRVD_COMP_16))) {
638 WARN_ONCE(1, "no structure for xstate: %d\n", nr);
639 XSTATE_WARN_ON(1);
640 return false;
641 }
642 return true;
643}
644
645static unsigned int xstate_calculate_size(u64 xfeatures, bool compacted)
646{
647 unsigned int size = FXSAVE_SIZE + XSAVE_HDR_SIZE;
648 int i;
649
650 for_each_extended_xfeature(i, xfeatures) {
651
652 if (xfeature_is_aligned(i))
653 size = ALIGN(size, 64);
654
655
656
657
658
659
660
661 if (!compacted)
662 size = xfeature_uncompacted_offset(i);
663
664
665
666
667 size += xfeature_size(i);
668 }
669 return size;
670}
671
672
673
674
675
676
677
678
679
680
681static bool __init paranoid_xstate_size_valid(unsigned int kernel_size)
682{
683 bool compacted = cpu_feature_enabled(X86_FEATURE_XSAVES);
684 unsigned int size = FXSAVE_SIZE + XSAVE_HDR_SIZE;
685 int i;
686
687 for_each_extended_xfeature(i, fpu_kernel_cfg.max_features) {
688 if (!check_xstate_against_struct(i))
689 return false;
690
691
692
693
694 if (!compacted && xfeature_is_supervisor(i)) {
695 XSTATE_WARN_ON(1);
696 return false;
697 }
698 }
699 size = xstate_calculate_size(fpu_kernel_cfg.max_features, compacted);
700 XSTATE_WARN_ON(size != kernel_size);
701 return size == kernel_size;
702}
703
704
705
706
707
708
709
710
711
712static unsigned int __init get_xsaves_size(void)
713{
714 unsigned int eax, ebx, ecx, edx;
715
716
717
718
719
720
721
722
723 cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx);
724 return ebx;
725}
726
727
728
729
730
731static unsigned int __init get_xsaves_size_no_independent(void)
732{
733 u64 mask = xfeatures_mask_independent();
734 unsigned int size;
735
736 if (!mask)
737 return get_xsaves_size();
738
739
740 wrmsrl(MSR_IA32_XSS, xfeatures_mask_supervisor());
741
742
743
744
745
746 size = get_xsaves_size();
747
748
749 wrmsrl(MSR_IA32_XSS, xfeatures_mask_supervisor() | mask);
750
751 return size;
752}
753
754static unsigned int __init get_xsave_size_user(void)
755{
756 unsigned int eax, ebx, ecx, edx;
757
758
759
760
761
762
763
764 cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
765 return ebx;
766}
767
768
769
770
771
772static bool __init is_supported_xstate_size(unsigned int test_xstate_size)
773{
774 if (test_xstate_size <= sizeof(init_fpstate.regs))
775 return true;
776
777 pr_warn("x86/fpu: xstate buffer too small (%zu < %d), disabling xsave\n",
778 sizeof(init_fpstate.regs), test_xstate_size);
779 return false;
780}
781
782static int __init init_xstate_size(void)
783{
784
785 unsigned int user_size, kernel_size, kernel_default_size;
786 bool compacted = cpu_feature_enabled(X86_FEATURE_XSAVES);
787
788
789 user_size = get_xsave_size_user();
790
791
792
793
794
795
796
797
798 if (compacted)
799 kernel_size = get_xsaves_size_no_independent();
800 else
801 kernel_size = user_size;
802
803 kernel_default_size =
804 xstate_calculate_size(fpu_kernel_cfg.default_features, compacted);
805
806
807 if (!is_supported_xstate_size(kernel_default_size))
808 return -EINVAL;
809
810 if (!paranoid_xstate_size_valid(kernel_size))
811 return -EINVAL;
812
813 fpu_kernel_cfg.max_size = kernel_size;
814 fpu_user_cfg.max_size = user_size;
815
816 fpu_kernel_cfg.default_size = kernel_default_size;
817 fpu_user_cfg.default_size =
818 xstate_calculate_size(fpu_user_cfg.default_features, false);
819
820 return 0;
821}
822
823
824
825
826
827static void __init fpu__init_disable_system_xstate(unsigned int legacy_size)
828{
829 fpu_kernel_cfg.max_features = 0;
830 cr4_clear_bits(X86_CR4_OSXSAVE);
831 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
832
833
834 fpu_kernel_cfg.max_size = legacy_size;
835 fpu_kernel_cfg.default_size = legacy_size;
836 fpu_user_cfg.max_size = legacy_size;
837 fpu_user_cfg.default_size = legacy_size;
838
839
840
841
842
843 init_fpstate.xfd = 0;
844
845 fpstate_reset(¤t->thread.fpu);
846}
847
848
849
850
851
852void __init fpu__init_system_xstate(unsigned int legacy_size)
853{
854 unsigned int eax, ebx, ecx, edx;
855 u64 xfeatures;
856 int err;
857 int i;
858
859 if (!boot_cpu_has(X86_FEATURE_FPU)) {
860 pr_info("x86/fpu: No FPU detected\n");
861 return;
862 }
863
864 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
865 pr_info("x86/fpu: x87 FPU will use %s\n",
866 boot_cpu_has(X86_FEATURE_FXSR) ? "FXSAVE" : "FSAVE");
867 return;
868 }
869
870 if (boot_cpu_data.cpuid_level < XSTATE_CPUID) {
871 WARN_ON_FPU(1);
872 return;
873 }
874
875
876
877
878 cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx);
879 fpu_kernel_cfg.max_features = eax + ((u64)edx << 32);
880
881
882
883
884 cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx);
885 fpu_kernel_cfg.max_features |= ecx + ((u64)edx << 32);
886
887 if ((fpu_kernel_cfg.max_features & XFEATURE_MASK_FPSSE) != XFEATURE_MASK_FPSSE) {
888
889
890
891
892
893 pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n",
894 fpu_kernel_cfg.max_features);
895 goto out_disable;
896 }
897
898
899
900
901 for (i = 0; i < ARRAY_SIZE(xsave_cpuid_features); i++) {
902 unsigned short cid = xsave_cpuid_features[i];
903
904
905 if ((i != XFEATURE_FP && !cid) || !boot_cpu_has(cid))
906 fpu_kernel_cfg.max_features &= ~BIT_ULL(i);
907 }
908
909 if (!cpu_feature_enabled(X86_FEATURE_XFD))
910 fpu_kernel_cfg.max_features &= ~XFEATURE_MASK_USER_DYNAMIC;
911
912 fpu_kernel_cfg.max_features &= XFEATURE_MASK_USER_SUPPORTED |
913 XFEATURE_MASK_SUPERVISOR_SUPPORTED;
914
915 fpu_user_cfg.max_features = fpu_kernel_cfg.max_features;
916 fpu_user_cfg.max_features &= XFEATURE_MASK_USER_SUPPORTED;
917
918
919 fpu_kernel_cfg.default_features = fpu_kernel_cfg.max_features;
920 fpu_kernel_cfg.default_features &= ~XFEATURE_MASK_USER_DYNAMIC;
921
922 fpu_user_cfg.default_features = fpu_user_cfg.max_features;
923 fpu_user_cfg.default_features &= ~XFEATURE_MASK_USER_DYNAMIC;
924
925
926 xfeatures = fpu_kernel_cfg.max_features;
927
928
929
930
931
932
933
934 init_fpstate.xfd = fpu_user_cfg.max_features & XFEATURE_MASK_USER_DYNAMIC;
935
936
937 fpu__init_cpu_xstate();
938 err = init_xstate_size();
939 if (err)
940 goto out_disable;
941
942
943 fpstate_reset(¤t->thread.fpu);
944
945
946
947
948
949 update_regset_xstate_info(fpu_user_cfg.max_size,
950 fpu_user_cfg.max_features);
951
952 setup_init_fpu_buf();
953 setup_xstate_comp_offsets();
954 setup_supervisor_only_offsets();
955
956
957
958
959
960 if (xfeatures != fpu_kernel_cfg.max_features) {
961 pr_err("x86/fpu: xfeatures modified from 0x%016llx to 0x%016llx during init, disabling XSAVE\n",
962 xfeatures, fpu_kernel_cfg.max_features);
963 goto out_disable;
964 }
965
966 print_xstate_offset_size();
967 pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n",
968 fpu_kernel_cfg.max_features,
969 fpu_kernel_cfg.max_size,
970 boot_cpu_has(X86_FEATURE_XSAVES) ? "compacted" : "standard");
971 return;
972
973out_disable:
974
975 fpu__init_disable_system_xstate(legacy_size);
976}
977
978
979
980
981void fpu__resume_cpu(void)
982{
983
984
985
986 if (cpu_feature_enabled(X86_FEATURE_XSAVE))
987 xsetbv(XCR_XFEATURE_ENABLED_MASK, fpu_user_cfg.max_features);
988
989
990
991
992
993 if (cpu_feature_enabled(X86_FEATURE_XSAVES)) {
994 wrmsrl(MSR_IA32_XSS, xfeatures_mask_supervisor() |
995 xfeatures_mask_independent());
996 }
997
998 if (fpu_state_size_dynamic())
999 wrmsrl(MSR_IA32_XFD, current->thread.fpu.fpstate->xfd);
1000}
1001
1002
1003
1004
1005
1006
1007static void *__raw_xsave_addr(struct xregs_state *xsave, int xfeature_nr)
1008{
1009 if (!xfeature_enabled(xfeature_nr)) {
1010 WARN_ON_FPU(1);
1011 return NULL;
1012 }
1013
1014 return (void *)xsave + xstate_comp_offsets[xfeature_nr];
1015}
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034void *get_xsave_addr(struct xregs_state *xsave, int xfeature_nr)
1035{
1036
1037
1038
1039 if (!boot_cpu_has(X86_FEATURE_XSAVE))
1040 return NULL;
1041
1042
1043
1044
1045
1046 WARN_ONCE(!(fpu_kernel_cfg.max_features & BIT_ULL(xfeature_nr)),
1047 "get of unsupported state");
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059 if (!(xsave->header.xfeatures & BIT_ULL(xfeature_nr)))
1060 return NULL;
1061
1062 return __raw_xsave_addr(xsave, xfeature_nr);
1063}
1064
1065#ifdef CONFIG_ARCH_HAS_PKEYS
1066
1067
1068
1069
1070
1071int arch_set_user_pkey_access(struct task_struct *tsk, int pkey,
1072 unsigned long init_val)
1073{
1074 u32 old_pkru, new_pkru_bits = 0;
1075 int pkey_shift;
1076
1077
1078
1079
1080
1081 if (!cpu_feature_enabled(X86_FEATURE_OSPKE))
1082 return -EINVAL;
1083
1084
1085
1086
1087
1088
1089 if (WARN_ON_ONCE(pkey >= arch_max_pkey()))
1090 return -EINVAL;
1091
1092
1093 if (init_val & PKEY_DISABLE_ACCESS)
1094 new_pkru_bits |= PKRU_AD_BIT;
1095 if (init_val & PKEY_DISABLE_WRITE)
1096 new_pkru_bits |= PKRU_WD_BIT;
1097
1098
1099 pkey_shift = pkey * PKRU_BITS_PER_PKEY;
1100 new_pkru_bits <<= pkey_shift;
1101
1102
1103 old_pkru = read_pkru();
1104 old_pkru &= ~((PKRU_AD_BIT|PKRU_WD_BIT) << pkey_shift);
1105
1106
1107 write_pkru(old_pkru | new_pkru_bits);
1108
1109 return 0;
1110}
1111#endif
1112
1113static void copy_feature(bool from_xstate, struct membuf *to, void *xstate,
1114 void *init_xstate, unsigned int size)
1115{
1116 membuf_write(to, from_xstate ? xstate : init_xstate, size);
1117}
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132void __copy_xstate_to_uabi_buf(struct membuf to, struct fpstate *fpstate,
1133 u32 pkru_val, enum xstate_copy_mode copy_mode)
1134{
1135 const unsigned int off_mxcsr = offsetof(struct fxregs_state, mxcsr);
1136 struct xregs_state *xinit = &init_fpstate.regs.xsave;
1137 struct xregs_state *xsave = &fpstate->regs.xsave;
1138 struct xstate_header header;
1139 unsigned int zerofrom;
1140 u64 mask;
1141 int i;
1142
1143 memset(&header, 0, sizeof(header));
1144 header.xfeatures = xsave->header.xfeatures;
1145
1146
1147 switch (copy_mode) {
1148 case XSTATE_COPY_FP:
1149 header.xfeatures &= XFEATURE_MASK_FP;
1150 break;
1151
1152 case XSTATE_COPY_FX:
1153 header.xfeatures &= XFEATURE_MASK_FP | XFEATURE_MASK_SSE;
1154 break;
1155
1156 case XSTATE_COPY_XSAVE:
1157 header.xfeatures &= fpstate->user_xfeatures;
1158 break;
1159 }
1160
1161
1162 copy_feature(header.xfeatures & XFEATURE_MASK_FP, &to, &xsave->i387,
1163 &xinit->i387, off_mxcsr);
1164
1165
1166 copy_feature(header.xfeatures & (XFEATURE_MASK_SSE | XFEATURE_MASK_YMM),
1167 &to, &xsave->i387.mxcsr, &xinit->i387.mxcsr,
1168 MXCSR_AND_FLAGS_SIZE);
1169
1170
1171 copy_feature(header.xfeatures & XFEATURE_MASK_FP,
1172 &to, &xsave->i387.st_space, &xinit->i387.st_space,
1173 sizeof(xsave->i387.st_space));
1174
1175
1176 copy_feature(header.xfeatures & XFEATURE_MASK_SSE,
1177 &to, &xsave->i387.xmm_space, &xinit->i387.xmm_space,
1178 sizeof(xsave->i387.xmm_space));
1179
1180 if (copy_mode != XSTATE_COPY_XSAVE)
1181 goto out;
1182
1183
1184 membuf_zero(&to, sizeof(xsave->i387.padding));
1185
1186
1187 membuf_write(&to, xstate_fx_sw_bytes, sizeof(xsave->i387.sw_reserved));
1188
1189
1190 membuf_write(&to, &header, sizeof(header));
1191
1192 zerofrom = offsetof(struct xregs_state, extended_state_area);
1193
1194
1195
1196
1197
1198
1199
1200 mask = fpstate->user_xfeatures;
1201
1202 for_each_extended_xfeature(i, mask) {
1203
1204
1205
1206
1207 if (zerofrom < xstate_offsets[i])
1208 membuf_zero(&to, xstate_offsets[i] - zerofrom);
1209
1210 if (i == XFEATURE_PKRU) {
1211 struct pkru_state pkru = {0};
1212
1213
1214
1215
1216 pkru.pkru = pkru_val;
1217 membuf_write(&to, &pkru, sizeof(pkru));
1218 } else {
1219 copy_feature(header.xfeatures & BIT_ULL(i), &to,
1220 __raw_xsave_addr(xsave, i),
1221 __raw_xsave_addr(xinit, i),
1222 xstate_sizes[i]);
1223 }
1224
1225
1226
1227
1228 zerofrom = xstate_offsets[i] + xstate_sizes[i];
1229 }
1230
1231out:
1232 if (to.left)
1233 membuf_zero(&to, to.left);
1234}
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248void copy_xstate_to_uabi_buf(struct membuf to, struct task_struct *tsk,
1249 enum xstate_copy_mode copy_mode)
1250{
1251 __copy_xstate_to_uabi_buf(to, tsk->thread.fpu.fpstate,
1252 tsk->thread.pkru, copy_mode);
1253}
1254
1255static int copy_from_buffer(void *dst, unsigned int offset, unsigned int size,
1256 const void *kbuf, const void __user *ubuf)
1257{
1258 if (kbuf) {
1259 memcpy(dst, kbuf + offset, size);
1260 } else {
1261 if (copy_from_user(dst, ubuf + offset, size))
1262 return -EFAULT;
1263 }
1264 return 0;
1265}
1266
1267
1268static int copy_uabi_to_xstate(struct fpstate *fpstate, const void *kbuf,
1269 const void __user *ubuf)
1270{
1271 struct xregs_state *xsave = &fpstate->regs.xsave;
1272 unsigned int offset, size;
1273 struct xstate_header hdr;
1274 u64 mask;
1275 int i;
1276
1277 offset = offsetof(struct xregs_state, header);
1278 if (copy_from_buffer(&hdr, offset, sizeof(hdr), kbuf, ubuf))
1279 return -EFAULT;
1280
1281 if (validate_user_xstate_header(&hdr, fpstate))
1282 return -EINVAL;
1283
1284
1285 mask = XFEATURE_MASK_FP | XFEATURE_MASK_SSE | XFEATURE_MASK_YMM;
1286 if (hdr.xfeatures & mask) {
1287 u32 mxcsr[2];
1288
1289 offset = offsetof(struct fxregs_state, mxcsr);
1290 if (copy_from_buffer(mxcsr, offset, sizeof(mxcsr), kbuf, ubuf))
1291 return -EFAULT;
1292
1293
1294 if (mxcsr[0] & ~mxcsr_feature_mask)
1295 return -EINVAL;
1296
1297
1298 if (!(hdr.xfeatures & XFEATURE_MASK_FP)) {
1299 xsave->i387.mxcsr = mxcsr[0];
1300 xsave->i387.mxcsr_mask = mxcsr[1];
1301 }
1302 }
1303
1304 for (i = 0; i < XFEATURE_MAX; i++) {
1305 u64 mask = ((u64)1 << i);
1306
1307 if (hdr.xfeatures & mask) {
1308 void *dst = __raw_xsave_addr(xsave, i);
1309
1310 offset = xstate_offsets[i];
1311 size = xstate_sizes[i];
1312
1313 if (copy_from_buffer(dst, offset, size, kbuf, ubuf))
1314 return -EFAULT;
1315 }
1316 }
1317
1318
1319
1320
1321
1322 xsave->header.xfeatures &= XFEATURE_MASK_SUPERVISOR_ALL;
1323
1324
1325
1326
1327 xsave->header.xfeatures |= hdr.xfeatures;
1328
1329 return 0;
1330}
1331
1332
1333
1334
1335
1336int copy_uabi_from_kernel_to_xstate(struct fpstate *fpstate, const void *kbuf)
1337{
1338 return copy_uabi_to_xstate(fpstate, kbuf, NULL);
1339}
1340
1341
1342
1343
1344
1345
1346int copy_sigframe_from_user_to_xstate(struct fpstate *fpstate,
1347 const void __user *ubuf)
1348{
1349 return copy_uabi_to_xstate(fpstate, NULL, ubuf);
1350}
1351
1352static bool validate_independent_components(u64 mask)
1353{
1354 u64 xchk;
1355
1356 if (WARN_ON_FPU(!cpu_feature_enabled(X86_FEATURE_XSAVES)))
1357 return false;
1358
1359 xchk = ~xfeatures_mask_independent();
1360
1361 if (WARN_ON_ONCE(!mask || mask & xchk))
1362 return false;
1363
1364 return true;
1365}
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379void xsaves(struct xregs_state *xstate, u64 mask)
1380{
1381 int err;
1382
1383 if (!validate_independent_components(mask))
1384 return;
1385
1386 XSTATE_OP(XSAVES, xstate, (u32)mask, (u32)(mask >> 32), err);
1387 WARN_ON_ONCE(err);
1388}
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403void xrstors(struct xregs_state *xstate, u64 mask)
1404{
1405 int err;
1406
1407 if (!validate_independent_components(mask))
1408 return;
1409
1410 XSTATE_OP(XRSTORS, xstate, (u32)mask, (u32)(mask >> 32), err);
1411 WARN_ON_ONCE(err);
1412}
1413
1414#if IS_ENABLED(CONFIG_KVM)
1415void fpstate_clear_xstate_component(struct fpstate *fps, unsigned int xfeature)
1416{
1417 void *addr = get_xsave_addr(&fps->regs.xsave, xfeature);
1418
1419 if (addr)
1420 memset(addr, 0, xstate_sizes[xfeature]);
1421}
1422EXPORT_SYMBOL_GPL(fpstate_clear_xstate_component);
1423#endif
1424
1425#ifdef CONFIG_X86_64
1426
1427#ifdef CONFIG_X86_DEBUG_FPU
1428
1429
1430
1431
1432static bool xstate_op_valid(struct fpstate *fpstate, u64 mask, bool rstor)
1433{
1434 u64 xfd = __this_cpu_read(xfd_state);
1435
1436 if (fpstate->xfd == xfd)
1437 return true;
1438
1439
1440
1441
1442
1443 if (fpstate->xfd == current->thread.fpu.fpstate->xfd)
1444 return false;
1445
1446
1447
1448
1449
1450
1451 if (fpstate == &init_fpstate)
1452 return rstor;
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463 mask &= ~xfd;
1464
1465
1466
1467
1468
1469 mask &= ~fpstate->xfeatures;
1470
1471
1472
1473
1474
1475 return !mask;
1476}
1477
1478void xfd_validate_state(struct fpstate *fpstate, u64 mask, bool rstor)
1479{
1480 WARN_ON_ONCE(!xstate_op_valid(fpstate, mask, rstor));
1481}
1482#endif
1483
1484static int __init xfd_update_static_branch(void)
1485{
1486
1487
1488
1489
1490 if (init_fpstate.xfd)
1491 static_branch_enable(&__fpu_state_size_dynamic);
1492 return 0;
1493}
1494arch_initcall(xfd_update_static_branch)
1495
1496void fpstate_free(struct fpu *fpu)
1497{
1498 if (fpu->fpstate && fpu->fpstate != &fpu->__fpstate)
1499 vfree(fpu->fpstate);
1500}
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513static struct fpstate *fpu_install_fpstate(struct fpu *fpu,
1514 struct fpstate *newfps)
1515{
1516 struct fpstate *oldfps = fpu->fpstate;
1517
1518 if (fpu->fpstate == newfps)
1519 return NULL;
1520
1521 fpu->fpstate = newfps;
1522 return oldfps != &fpu->__fpstate ? oldfps : NULL;
1523}
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539static int fpstate_realloc(u64 xfeatures, unsigned int ksize,
1540 unsigned int usize)
1541{
1542 struct fpu *fpu = ¤t->thread.fpu;
1543 struct fpstate *curfps, *newfps = NULL;
1544 unsigned int fpsize;
1545
1546 curfps = fpu->fpstate;
1547 fpsize = ksize + ALIGN(offsetof(struct fpstate, regs), 64);
1548
1549 newfps = vzalloc(fpsize);
1550 if (!newfps)
1551 return -ENOMEM;
1552 newfps->size = ksize;
1553 newfps->user_size = usize;
1554 newfps->is_valloc = true;
1555
1556 fpregs_lock();
1557
1558
1559
1560
1561
1562 if (test_thread_flag(TIF_NEED_FPU_LOAD))
1563 fpregs_restore_userregs();
1564
1565 newfps->xfeatures = curfps->xfeatures | xfeatures;
1566 newfps->user_xfeatures = curfps->user_xfeatures | xfeatures;
1567 newfps->xfd = curfps->xfd & ~xfeatures;
1568
1569 curfps = fpu_install_fpstate(fpu, newfps);
1570
1571
1572 xstate_init_xcomp_bv(&newfps->regs.xsave, newfps->xfeatures);
1573 xfd_update_state(newfps);
1574
1575 fpregs_unlock();
1576
1577 vfree(curfps);
1578 return 0;
1579}
1580
1581static int validate_sigaltstack(unsigned int usize)
1582{
1583 struct task_struct *thread, *leader = current->group_leader;
1584 unsigned long framesize = get_sigframe_size();
1585
1586 lockdep_assert_held(¤t->sighand->siglock);
1587
1588
1589 framesize -= fpu_user_cfg.max_size;
1590 framesize += usize;
1591 for_each_thread(leader, thread) {
1592 if (thread->sas_ss_size && thread->sas_ss_size < framesize)
1593 return -ENOSPC;
1594 }
1595 return 0;
1596}
1597
1598static int __xstate_request_perm(u64 permitted, u64 requested)
1599{
1600
1601
1602
1603
1604
1605
1606 bool compacted = cpu_feature_enabled(X86_FEATURE_XSAVES);
1607 struct fpu *fpu = ¤t->group_leader->thread.fpu;
1608 unsigned int ksize, usize;
1609 u64 mask;
1610 int ret;
1611
1612
1613 if ((permitted & requested) == requested)
1614 return 0;
1615
1616
1617 mask = permitted | requested;
1618 ksize = xstate_calculate_size(mask, compacted);
1619
1620
1621 mask &= XFEATURE_MASK_USER_SUPPORTED;
1622 usize = xstate_calculate_size(mask, false);
1623
1624 ret = validate_sigaltstack(usize);
1625 if (ret)
1626 return ret;
1627
1628
1629 WRITE_ONCE(fpu->perm.__state_perm, requested);
1630
1631 fpu->perm.__state_size = ksize;
1632 fpu->perm.__user_state_size = usize;
1633 return ret;
1634}
1635
1636
1637
1638
1639static const u64 xstate_prctl_req[XFEATURE_MAX] = {
1640 [XFEATURE_XTILE_DATA] = XFEATURE_MASK_XTILE_DATA,
1641};
1642
1643static int xstate_request_perm(unsigned long idx)
1644{
1645 u64 permitted, requested;
1646 int ret;
1647
1648 if (idx >= XFEATURE_MAX)
1649 return -EINVAL;
1650
1651
1652
1653
1654
1655 idx = array_index_nospec(idx, ARRAY_SIZE(xstate_prctl_req));
1656 requested = xstate_prctl_req[idx];
1657 if (!requested)
1658 return -EOPNOTSUPP;
1659
1660 if ((fpu_user_cfg.max_features & requested) != requested)
1661 return -EOPNOTSUPP;
1662
1663
1664 permitted = xstate_get_host_group_perm();
1665 if ((permitted & requested) == requested)
1666 return 0;
1667
1668
1669 spin_lock_irq(¤t->sighand->siglock);
1670 permitted = xstate_get_host_group_perm();
1671 ret = __xstate_request_perm(permitted, requested);
1672 spin_unlock_irq(¤t->sighand->siglock);
1673 return ret;
1674}
1675
1676int xfd_enable_feature(u64 xfd_err)
1677{
1678 u64 xfd_event = xfd_err & XFEATURE_MASK_USER_DYNAMIC;
1679 unsigned int ksize, usize;
1680 struct fpu *fpu;
1681
1682 if (!xfd_event) {
1683 pr_err_once("XFD: Invalid xfd error: %016llx\n", xfd_err);
1684 return 0;
1685 }
1686
1687
1688 spin_lock_irq(¤t->sighand->siglock);
1689
1690
1691 if ((xstate_get_host_group_perm() & xfd_event) != xfd_event) {
1692 spin_unlock_irq(¤t->sighand->siglock);
1693 return -EPERM;
1694 }
1695
1696 fpu = ¤t->group_leader->thread.fpu;
1697 ksize = fpu->perm.__state_size;
1698 usize = fpu->perm.__user_state_size;
1699
1700
1701
1702
1703
1704
1705 spin_unlock_irq(¤t->sighand->siglock);
1706
1707
1708
1709
1710
1711 if (fpstate_realloc(xfd_event, ksize, usize))
1712 return -EFAULT;
1713 return 0;
1714}
1715#else
1716static inline int xstate_request_perm(unsigned long idx)
1717{
1718 return -EPERM;
1719}
1720#endif
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740long fpu_xstate_prctl(struct task_struct *tsk, int option, unsigned long arg2)
1741{
1742 u64 __user *uptr = (u64 __user *)arg2;
1743 u64 permitted, supported;
1744 unsigned long idx = arg2;
1745
1746 if (tsk != current)
1747 return -EPERM;
1748
1749 switch (option) {
1750 case ARCH_GET_XCOMP_SUPP:
1751 supported = fpu_user_cfg.max_features | fpu_user_cfg.legacy_features;
1752 return put_user(supported, uptr);
1753
1754 case ARCH_GET_XCOMP_PERM:
1755
1756
1757
1758
1759 permitted = xstate_get_host_group_perm();
1760 permitted &= XFEATURE_MASK_USER_SUPPORTED;
1761 return put_user(permitted, uptr);
1762
1763 case ARCH_REQ_XCOMP_PERM:
1764 if (!IS_ENABLED(CONFIG_X86_64))
1765 return -EOPNOTSUPP;
1766
1767 return xstate_request_perm(idx);
1768
1769 default:
1770 return -EINVAL;
1771 }
1772}
1773
1774#ifdef CONFIG_PROC_PID_ARCH_STATUS
1775
1776
1777
1778
1779static void avx512_status(struct seq_file *m, struct task_struct *task)
1780{
1781 unsigned long timestamp = READ_ONCE(task->thread.fpu.avx512_timestamp);
1782 long delta;
1783
1784 if (!timestamp) {
1785
1786
1787
1788 delta = -1;
1789 } else {
1790 delta = (long)(jiffies - timestamp);
1791
1792
1793
1794 if (delta < 0)
1795 delta = LONG_MAX;
1796 delta = jiffies_to_msecs(delta);
1797 }
1798
1799 seq_put_decimal_ll(m, "AVX512_elapsed_ms:\t", delta);
1800 seq_putc(m, '\n');
1801}
1802
1803
1804
1805
1806int proc_pid_arch_status(struct seq_file *m, struct pid_namespace *ns,
1807 struct pid *pid, struct task_struct *task)
1808{
1809
1810
1811
1812 if (cpu_feature_enabled(X86_FEATURE_AVX512F))
1813 avx512_status(m, task);
1814
1815 return 0;
1816}
1817#endif
1818