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13#ifndef _XTENSA_CORE_TIE_H
14#define _XTENSA_CORE_TIE_H
15
16#define XCHAL_CP_NUM 0
17#define XCHAL_CP_MAX 0
18#define XCHAL_CP_MASK 0x00
19#define XCHAL_CP_PORT_MASK 0x00
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22#define XCHAL_NCP_SA_SIZE 0
23#define XCHAL_NCP_SA_ALIGN 1
24#define XCHAL_CP0_SA_SIZE 0
25#define XCHAL_CP0_SA_ALIGN 1
26#define XCHAL_CP1_SA_SIZE 0
27#define XCHAL_CP1_SA_ALIGN 1
28#define XCHAL_CP2_SA_SIZE 0
29#define XCHAL_CP2_SA_ALIGN 1
30#define XCHAL_CP3_SA_SIZE 0
31#define XCHAL_CP3_SA_ALIGN 1
32#define XCHAL_CP4_SA_SIZE 0
33#define XCHAL_CP4_SA_ALIGN 1
34#define XCHAL_CP5_SA_SIZE 0
35#define XCHAL_CP5_SA_ALIGN 1
36#define XCHAL_CP6_SA_SIZE 0
37#define XCHAL_CP6_SA_ALIGN 1
38#define XCHAL_CP7_SA_SIZE 0
39#define XCHAL_CP7_SA_ALIGN 1
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41
42#define XCHAL_NCP_SA_SIZE 0
43#define XCHAL_NCP_SA_ALIGN 1
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45
46#define XCHAL_TOTAL_SA_SIZE 0
47#define XCHAL_TOTAL_SA_ALIGN 1
48
49#define XCHAL_NCP_SA_NUM 0
50#define XCHAL_NCP_SA_LIST(s)
51#define XCHAL_CP0_SA_NUM 0
52#define XCHAL_CP0_SA_LIST(s)
53#define XCHAL_CP1_SA_NUM 0
54#define XCHAL_CP1_SA_LIST(s)
55#define XCHAL_CP2_SA_NUM 0
56#define XCHAL_CP2_SA_LIST(s)
57#define XCHAL_CP3_SA_NUM 0
58#define XCHAL_CP3_SA_LIST(s)
59#define XCHAL_CP4_SA_NUM 0
60#define XCHAL_CP4_SA_LIST(s)
61#define XCHAL_CP5_SA_NUM 0
62#define XCHAL_CP5_SA_LIST(s)
63#define XCHAL_CP6_SA_NUM 0
64#define XCHAL_CP6_SA_LIST(s)
65#define XCHAL_CP7_SA_NUM 0
66#define XCHAL_CP7_SA_LIST(s)
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68
69#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
70
71#endif
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