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18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <scsi/scsi_host.h>
26#include <linux/libata.h>
27
28#define DRV_NAME "pata_hpt366"
29#define DRV_VERSION "0.6.11"
30
31struct hpt_clock {
32 u8 xfer_mode;
33 u32 timing;
34};
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57static const struct hpt_clock hpt366_40[] = {
58 { XFER_UDMA_4, 0x900fd943 },
59 { XFER_UDMA_3, 0x900ad943 },
60 { XFER_UDMA_2, 0x900bd943 },
61 { XFER_UDMA_1, 0x9008d943 },
62 { XFER_UDMA_0, 0x9008d943 },
63
64 { XFER_MW_DMA_2, 0xa008d943 },
65 { XFER_MW_DMA_1, 0xa010d955 },
66 { XFER_MW_DMA_0, 0xa010d9fc },
67
68 { XFER_PIO_4, 0xc008d963 },
69 { XFER_PIO_3, 0xc010d974 },
70 { XFER_PIO_2, 0xc010d997 },
71 { XFER_PIO_1, 0xc010d9c7 },
72 { XFER_PIO_0, 0xc018d9d9 },
73 { 0, 0x0120d9d9 }
74};
75
76static const struct hpt_clock hpt366_33[] = {
77 { XFER_UDMA_4, 0x90c9a731 },
78 { XFER_UDMA_3, 0x90cfa731 },
79 { XFER_UDMA_2, 0x90caa731 },
80 { XFER_UDMA_1, 0x90cba731 },
81 { XFER_UDMA_0, 0x90c8a731 },
82
83 { XFER_MW_DMA_2, 0xa0c8a731 },
84 { XFER_MW_DMA_1, 0xa0c8a732 },
85 { XFER_MW_DMA_0, 0xa0c8a797 },
86
87 { XFER_PIO_4, 0xc0c8a731 },
88 { XFER_PIO_3, 0xc0c8a742 },
89 { XFER_PIO_2, 0xc0d0a753 },
90 { XFER_PIO_1, 0xc0d0a7a3 },
91 { XFER_PIO_0, 0xc0d0a7aa },
92 { 0, 0x0120a7a7 }
93};
94
95static const struct hpt_clock hpt366_25[] = {
96 { XFER_UDMA_4, 0x90c98521 },
97 { XFER_UDMA_3, 0x90cf8521 },
98 { XFER_UDMA_2, 0x90cf8521 },
99 { XFER_UDMA_1, 0x90cb8521 },
100 { XFER_UDMA_0, 0x90cb8521 },
101
102 { XFER_MW_DMA_2, 0xa0ca8521 },
103 { XFER_MW_DMA_1, 0xa0ca8532 },
104 { XFER_MW_DMA_0, 0xa0ca8575 },
105
106 { XFER_PIO_4, 0xc0ca8521 },
107 { XFER_PIO_3, 0xc0ca8532 },
108 { XFER_PIO_2, 0xc0ca8542 },
109 { XFER_PIO_1, 0xc0d08572 },
110 { XFER_PIO_0, 0xc0d08585 },
111 { 0, 0x01208585 }
112};
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123static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
124{
125 struct hpt_clock *clocks = ap->host->private_data;
126
127 while (clocks->xfer_mode) {
128 if (clocks->xfer_mode == speed)
129 return clocks->timing;
130 clocks++;
131 }
132 BUG();
133 return 0xffffffffU;
134}
135
136static const char * const bad_ata33[] = {
137 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
138 "Maxtor 90845U3", "Maxtor 90650U2",
139 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
140 "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
141 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
142 "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
143 "Maxtor 90510D4",
144 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
145 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
146 "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
147 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
148 "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
149 NULL
150};
151
152static const char * const bad_ata66_4[] = {
153 "IBM-DTLA-307075",
154 "IBM-DTLA-307060",
155 "IBM-DTLA-307045",
156 "IBM-DTLA-307030",
157 "IBM-DTLA-307020",
158 "IBM-DTLA-307015",
159 "IBM-DTLA-305040",
160 "IBM-DTLA-305030",
161 "IBM-DTLA-305020",
162 "IC35L010AVER07-0",
163 "IC35L020AVER07-0",
164 "IC35L030AVER07-0",
165 "IC35L040AVER07-0",
166 "IC35L060AVER07-0",
167 "WDC AC310200R",
168 NULL
169};
170
171static const char * const bad_ata66_3[] = {
172 "WDC AC310200R",
173 NULL
174};
175
176static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
177 const char * const list[])
178{
179 unsigned char model_num[ATA_ID_PROD_LEN + 1];
180 int i;
181
182 ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
183
184 i = match_string(list, -1, model_num);
185 if (i >= 0) {
186 pr_warn("%s is not supported for %s\n", modestr, list[i]);
187 return 1;
188 }
189 return 0;
190}
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200static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
201{
202 if (adev->class == ATA_DEV_ATA) {
203 if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
204 mask &= ~ATA_MASK_UDMA;
205 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
206 mask &= ~(0xF8 << ATA_SHIFT_UDMA);
207 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
208 mask &= ~(0xF0 << ATA_SHIFT_UDMA);
209 } else if (adev->class == ATA_DEV_ATAPI)
210 mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
211
212 return mask;
213}
214
215static int hpt36x_cable_detect(struct ata_port *ap)
216{
217 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
218 u8 ata66;
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224 pci_read_config_byte(pdev, 0x5A, &ata66);
225 if (ata66 & 2)
226 return ATA_CBL_PATA40;
227 return ATA_CBL_PATA80;
228}
229
230static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
231 u8 mode)
232{
233 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
234 u32 addr = 0x40 + 4 * adev->devno;
235 u32 mask, reg, t;
236
237
238 if (mode < XFER_MW_DMA_0)
239 mask = 0xc1f8ffff;
240 else if (mode < XFER_UDMA_0)
241 mask = 0x303800ff;
242 else
243 mask = 0x30070000;
244
245 t = hpt36x_find_mode(ap, mode);
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252 pci_read_config_dword(pdev, addr, ®);
253 reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000;
254 pci_write_config_dword(pdev, addr, reg);
255}
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265static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
266{
267 hpt366_set_mode(ap, adev, adev->pio_mode);
268}
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279static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
280{
281 hpt366_set_mode(ap, adev, adev->dma_mode);
282}
283
284static struct scsi_host_template hpt36x_sht = {
285 ATA_BMDMA_SHT(DRV_NAME),
286};
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292static struct ata_port_operations hpt366_port_ops = {
293 .inherits = &ata_bmdma_port_ops,
294 .cable_detect = hpt36x_cable_detect,
295 .mode_filter = hpt366_filter,
296 .set_piomode = hpt366_set_piomode,
297 .set_dmamode = hpt366_set_dmamode,
298};
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308static void hpt36x_init_chipset(struct pci_dev *dev)
309{
310 u8 drive_fast;
311
312 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
313 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
314 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
315 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
316
317 pci_read_config_byte(dev, 0x51, &drive_fast);
318 if (drive_fast & 0x80)
319 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
320}
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343static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
344{
345 static const struct ata_port_info info_hpt366 = {
346 .flags = ATA_FLAG_SLAVE_POSS,
347 .pio_mask = ATA_PIO4,
348 .mwdma_mask = ATA_MWDMA2,
349 .udma_mask = ATA_UDMA4,
350 .port_ops = &hpt366_port_ops
351 };
352 const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
353
354 const void *hpriv = NULL;
355 u32 reg1;
356 int rc;
357
358 rc = pcim_enable_device(dev);
359 if (rc)
360 return rc;
361
362
363
364 if (dev->revision > 2)
365 return -ENODEV;
366
367 hpt36x_init_chipset(dev);
368
369 pci_read_config_dword(dev, 0x40, ®1);
370
371
372
373 switch ((reg1 & 0xf00) >> 8) {
374 case 9:
375 hpriv = &hpt366_40;
376 break;
377 case 5:
378 hpriv = &hpt366_25;
379 break;
380 default:
381 hpriv = &hpt366_33;
382 break;
383 }
384
385 return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, (void *)hpriv, 0);
386}
387
388#ifdef CONFIG_PM_SLEEP
389static int hpt36x_reinit_one(struct pci_dev *dev)
390{
391 struct ata_host *host = pci_get_drvdata(dev);
392 int rc;
393
394 rc = ata_pci_device_do_resume(dev);
395 if (rc)
396 return rc;
397 hpt36x_init_chipset(dev);
398 ata_host_resume(host);
399 return 0;
400}
401#endif
402
403static const struct pci_device_id hpt36x[] = {
404 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
405 { },
406};
407
408static struct pci_driver hpt36x_pci_driver = {
409 .name = DRV_NAME,
410 .id_table = hpt36x,
411 .probe = hpt36x_init_one,
412 .remove = ata_pci_remove_one,
413#ifdef CONFIG_PM_SLEEP
414 .suspend = ata_pci_device_suspend,
415 .resume = hpt36x_reinit_one,
416#endif
417};
418
419module_pci_driver(hpt36x_pci_driver);
420
421MODULE_AUTHOR("Alan Cox");
422MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
423MODULE_LICENSE("GPL");
424MODULE_DEVICE_TABLE(pci, hpt36x);
425MODULE_VERSION(DRV_VERSION);
426