LXR linux/drivers/gpio/gpio-mlxbf2.c

   1// SPDX-License-Identifier: GPL-2.0
   2
   3/*
   4 * Copyright (C) 2020-2021 NVIDIA CORPORATION & AFFILIATES
   5 */
   6
   7#include <linux/bitfield.h>
   8#include <linux/bitops.h>
   9#include <linux/device.h>
  10#include <linux/gpio/driver.h>
  11#include <linux/interrupt.h>
  12#include <linux/io.h>
  13#include <linux/ioport.h>
  14#include <linux/kernel.h>
  15#include <linux/mod_devicetable.h>
  16#include <linux/module.h>
  17#include <linux/platform_device.h>
  18#include <linux/pm.h>
  19#include <linux/resource.h>
  20#include <linux/spinlock.h>
  21#include <linux/types.h>
  22
  23/*
  24 * There are 3 YU GPIO blocks:
  25 * gpio[0]: HOST_GPIO0->HOST_GPIO31
  26 * gpio[1]: HOST_GPIO32->HOST_GPIO63
  27 * gpio[2]: HOST_GPIO64->HOST_GPIO69
  28 */
  29#define MLXBF2_GPIO_MAX_PINS_PER_BLOCK 32
  30
  31/*
  32 * arm_gpio_lock register:
  33 * bit[31]      lock status: active if set
  34 * bit[15:0]    set lock
  35 * The lock is enabled only if 0xd42f is written to this field
  36 */
  37#define YU_ARM_GPIO_LOCK_ADDR           0x2801088
  38#define YU_ARM_GPIO_LOCK_SIZE           0x8
  39#define YU_LOCK_ACTIVE_BIT(val)         (val >> 31)
  40#define YU_ARM_GPIO_LOCK_ACQUIRE        0xd42f
  41#define YU_ARM_GPIO_LOCK_RELEASE        0x0
  42
  43/*
  44 * gpio[x] block registers and their offset
  45 */
  46#define YU_GPIO_DATAIN                  0x04
  47#define YU_GPIO_MODE1                   0x08
  48#define YU_GPIO_MODE0                   0x0c
  49#define YU_GPIO_DATASET                 0x14
  50#define YU_GPIO_DATACLEAR               0x18
  51#define YU_GPIO_CAUSE_RISE_EN           0x44
  52#define YU_GPIO_CAUSE_FALL_EN           0x48
  53#define YU_GPIO_MODE1_CLEAR             0x50
  54#define YU_GPIO_MODE0_SET               0x54
  55#define YU_GPIO_MODE0_CLEAR             0x58
  56#define YU_GPIO_CAUSE_OR_CAUSE_EVTEN0   0x80
  57#define YU_GPIO_CAUSE_OR_EVTEN0         0x94
  58#define YU_GPIO_CAUSE_OR_CLRCAUSE       0x98
  59
  60struct mlxbf2_gpio_context_save_regs {
  61        u32 gpio_mode0;
  62        u32 gpio_mode1;
  63};
  64
  65/* BlueField-2 gpio block context structure. */
  66struct mlxbf2_gpio_context {
  67        struct gpio_chip gc;
  68        struct irq_chip irq_chip;
  69
  70        /* YU GPIO blocks address */
  71        void __iomem *gpio_io;
  72
  73        struct mlxbf2_gpio_context_save_regs *csave_regs;
  74};
  75
  76/* BlueField-2 gpio shared structure. */
  77struct mlxbf2_gpio_param {
  78        void __iomem *io;
  79        struct resource *res;
  80        struct mutex *lock;
  81};
  82
  83static struct resource yu_arm_gpio_lock_res =
  84        DEFINE_RES_MEM_NAMED(YU_ARM_GPIO_LOCK_ADDR, YU_ARM_GPIO_LOCK_SIZE, "YU_ARM_GPIO_LOCK");
  85
  86static DEFINE_MUTEX(yu_arm_gpio_lock_mutex);
  87
  88static struct mlxbf2_gpio_param yu_arm_gpio_lock_param = {
  89        .res = &yu_arm_gpio_lock_res,
  90        .lock = &yu_arm_gpio_lock_mutex,
  91};
  92
  93/* Request memory region and map yu_arm_gpio_lock resource */
  94static int mlxbf2_gpio_get_lock_res(struct platform_device *pdev)
  95{
  96        struct device *dev = &pdev->dev;
  97        struct resource *res;
  98        resource_size_t size;
  99        int ret = 0;
 100
 101        mutex_lock(yu_arm_gpio_lock_param.lock);
 102
 103        /* Check if the memory map already exists */
 104        if (yu_arm_gpio_lock_param.io)
 105                goto exit;
 106
 107        res = yu_arm_gpio_lock_param.res;
 108        size = resource_size(res);
 109
 110        if (!devm_request_mem_region(dev, res->start, size, res->name)) {
 111                ret = -EFAULT;
 112                goto exit;
 113        }
 114
 115        yu_arm_gpio_lock_param.io = devm_ioremap(dev, res->start, size);
 116        if (!yu_arm_gpio_lock_param.io)
 117                ret = -ENOMEM;
 118
 119exit:
 120        mutex_unlock(yu_arm_gpio_lock_param.lock);
 121
 122        return ret;
 123}
 124
 125/*
 126 * Acquire the YU arm_gpio_lock to be able to change the direction
 127 * mode. If the lock_active bit is already set, return an error.
 128 */
 129static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs)
 130{
 131        u32 arm_gpio_lock_val;
 132
 133        mutex_lock(yu_arm_gpio_lock_param.lock);
 134        spin_lock(&gs->gc.bgpio_lock);
 135
 136        arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io);
 137
 138        /*
 139         * When lock active bit[31] is set, ModeX is write enabled
 140         */
 141        if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) {
 142                spin_unlock(&gs->gc.bgpio_lock);
 143                mutex_unlock(yu_arm_gpio_lock_param.lock);
 144                return -EINVAL;
 145        }
 146
 147        writel(YU_ARM_GPIO_LOCK_ACQUIRE, yu_arm_gpio_lock_param.io);
 148
 149        return 0;
 150}
 151
 152/*
 153 * Release the YU arm_gpio_lock after changing the direction mode.
 154 */
 155static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs)
 156        __releases(&gs->gc.bgpio_lock)
 157        __releases(yu_arm_gpio_lock_param.lock)
 158{
 159        writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io);
 160        spin_unlock(&gs->gc.bgpio_lock);
 161        mutex_unlock(yu_arm_gpio_lock_param.lock);
 162}
 163
 164/*
 165 * mode0 and mode1 are both locked by the gpio_lock field.
 166 *
 167 * Together, mode0 and mode1 define the gpio Mode dependeing also
 168 * on Reg_DataOut.
 169 *
 170 * {mode1,mode0}:{Reg_DataOut=0,Reg_DataOut=1}->{DataOut=0,DataOut=1}
 171 *
 172 * {0,0}:Reg_DataOut{0,1}->{Z,Z} Input PAD
 173 * {0,1}:Reg_DataOut{0,1}->{0,1} Full drive Output PAD
 174 * {1,0}:Reg_DataOut{0,1}->{0,Z} 0-set PAD to low, 1-float
 175 * {1,1}:Reg_DataOut{0,1}->{Z,1} 0-float, 1-set PAD to high
 176 */
 177
 178/*
 179 * Set input direction:
 180 * {mode1,mode0} = {0,0}
 181 */
 182static int mlxbf2_gpio_direction_input(struct gpio_chip *chip,
 183                                       unsigned int offset)
 184{
 185        struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
 186        int ret;
 187
 188        /*
 189         * Although the arm_gpio_lock was set in the probe function, check again
 190         * if it is still enabled to be able to write to the ModeX registers.
 191         */
 192        ret = mlxbf2_gpio_lock_acquire(gs);
 193        if (ret < 0)
 194                return ret;
 195
 196        writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_CLEAR);
 197        writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
 198
 199        mlxbf2_gpio_lock_release(gs);
 200
 201        return ret;
 202}
 203
 204/*
 205 * Set output direction:
 206 * {mode1,mode0} = {0,1}
 207 */
 208static int mlxbf2_gpio_direction_output(struct gpio_chip *chip,
 209                                        unsigned int offset,
 210                                        int value)
 211{
 212        struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip);
 213        int ret = 0;
 214
 215        /*
 216         * Although the arm_gpio_lock was set in the probe function,
 217         * check again it is still enabled to be able to write to the
 218         * ModeX registers.
 219         */
 220        ret = mlxbf2_gpio_lock_acquire(gs);
 221        if (ret < 0)
 222                return ret;
 223
 224        writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR);
 225        writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_SET);
 226
 227        mlxbf2_gpio_lock_release(gs);
 228
 229        return ret;
 230}
 231
 232static void mlxbf2_gpio_irq_enable(struct irq_data *irqd)
 233{
 234        struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 235        struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
 236        int offset = irqd_to_hwirq(irqd);
 237        unsigned long flags;
 238        u32 val;
 239
 240        spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
 241        val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
 242        val |= BIT(offset);
 243        writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
 244
 245        val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
 246        val |= BIT(offset);
 247        writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
 248        spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
 249}
 250
 251static void mlxbf2_gpio_irq_disable(struct irq_data *irqd)
 252{
 253        struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 254        struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
 255        int offset = irqd_to_hwirq(irqd);
 256        unsigned long flags;
 257        u32 val;
 258
 259        spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
 260        val = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
 261        val &= ~BIT(offset);
 262        writel(val, gs->gpio_io + YU_GPIO_CAUSE_OR_EVTEN0);
 263        spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
 264}
 265
 266static irqreturn_t mlxbf2_gpio_irq_handler(int irq, void *ptr)
 267{
 268        struct mlxbf2_gpio_context *gs = ptr;
 269        struct gpio_chip *gc = &gs->gc;
 270        unsigned long pending;
 271        u32 level;
 272
 273        pending = readl(gs->gpio_io + YU_GPIO_CAUSE_OR_CAUSE_EVTEN0);
 274        writel(pending, gs->gpio_io + YU_GPIO_CAUSE_OR_CLRCAUSE);
 275
 276        for_each_set_bit(level, &pending, gc->ngpio) {
 277                int gpio_irq = irq_find_mapping(gc->irq.domain, level);
 278                generic_handle_irq(gpio_irq);
 279        }
 280
 281        return IRQ_RETVAL(pending);
 282}
 283
 284static int
 285mlxbf2_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
 286{
 287        struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
 288        struct mlxbf2_gpio_context *gs = gpiochip_get_data(gc);
 289        int offset = irqd_to_hwirq(irqd);
 290        unsigned long flags;
 291        bool fall = false;
 292        bool rise = false;
 293        u32 val;
 294
 295        switch (type & IRQ_TYPE_SENSE_MASK) {
 296        case IRQ_TYPE_EDGE_BOTH:
 297                fall = true;
 298                rise = true;
 299                break;
 300        case IRQ_TYPE_EDGE_RISING:
 301                rise = true;
 302                break;
 303        case IRQ_TYPE_EDGE_FALLING:
 304                fall = true;
 305                break;
 306        default:
 307                return -EINVAL;
 308        }
 309
 310        spin_lock_irqsave(&gs->gc.bgpio_lock, flags);
 311        if (fall) {
 312                val = readl(gs->gpio_io + YU_GPIO_CAUSE_FALL_EN);
 313                val |= BIT(offset);
 314                writel(val, gs->gpio_io + YU_GPIO_CAUSE_FALL_EN);
 315        }
 316
 317        if (rise) {
 318                val = readl(gs->gpio_io + YU_GPIO_CAUSE_RISE_EN);
 319                val |= BIT(offset);
 320                writel(val, gs->gpio_io + YU_GPIO_CAUSE_RISE_EN);
 321        }
 322        spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);
 323
 324        return 0;
 325}
 326
 327/* BlueField-2 GPIO driver initialization routine. */
 328static int
 329mlxbf2_gpio_probe(struct platform_device *pdev)
 330{
 331        struct mlxbf2_gpio_context *gs;
 332        struct device *dev = &pdev->dev;
 333        struct gpio_irq_chip *girq;
 334        struct gpio_chip *gc;
 335        unsigned int npins;
 336        const char *name;
 337        int ret, irq;
 338
 339        name = dev_name(dev);
 340
 341        gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL);
 342        if (!gs)
 343                return -ENOMEM;
 344
 345        /* YU GPIO block address */
 346        gs->gpio_io = devm_platform_ioremap_resource(pdev, 0);
 347        if (IS_ERR(gs->gpio_io))
 348                return PTR_ERR(gs->gpio_io);
 349
 350        ret = mlxbf2_gpio_get_lock_res(pdev);
 351        if (ret) {
 352                dev_err(dev, "Failed to get yu_arm_gpio_lock resource\n");
 353                return ret;
 354        }
 355
 356        if (device_property_read_u32(dev, "npins", &npins))
 357                npins = MLXBF2_GPIO_MAX_PINS_PER_BLOCK;
 358
 359        gc = &gs->gc;
 360
 361        ret = bgpio_init(gc, dev, 4,
 362                        gs->gpio_io + YU_GPIO_DATAIN,
 363                        gs->gpio_io + YU_GPIO_DATASET,
 364                        gs->gpio_io + YU_GPIO_DATACLEAR,
 365                        NULL,
 366                        NULL,
 367                        0);
 368
 369        if (ret) {
 370                dev_err(dev, "bgpio_init failed\n");
 371                return ret;
 372        }
 373
 374        gc->direction_input = mlxbf2_gpio_direction_input;
 375        gc->direction_output = mlxbf2_gpio_direction_output;
 376        gc->ngpio = npins;
 377        gc->owner = THIS_MODULE;
 378
 379        irq = platform_get_irq(pdev, 0);
 380        if (irq >= 0) {
 381                gs->irq_chip.name = name;
 382                gs->irq_chip.irq_set_type = mlxbf2_gpio_irq_set_type;
 383                gs->irq_chip.irq_enable = mlxbf2_gpio_irq_enable;
 384                gs->irq_chip.irq_disable = mlxbf2_gpio_irq_disable;
 385
 386                girq = &gs->gc.irq;
 387                girq->chip = &gs->irq_chip;
 388                girq->handler = handle_simple_irq;
 389                girq->default_type = IRQ_TYPE_NONE;
 390                /* This will let us handle the parent IRQ in the driver */
 391                girq->num_parents = 0;
 392                girq->parents = NULL;
 393                girq->parent_handler = NULL;
 394
 395                /*
 396                 * Directly request the irq here instead of passing
 397                 * a flow-handler because the irq is shared.
 398                 */
 399                ret = devm_request_irq(dev, irq, mlxbf2_gpio_irq_handler,
 400                                       IRQF_SHARED, name, gs);
 401                if (ret) {
 402                        dev_err(dev, "failed to request IRQ");
 403                        return ret;
 404                }
 405        }
 406
 407        platform_set_drvdata(pdev, gs);
 408
 409        ret = devm_gpiochip_add_data(dev, &gs->gc, gs);
 410        if (ret) {
 411                dev_err(dev, "Failed adding memory mapped gpiochip\n");
 412                return ret;
 413        }
 414
 415        return 0;
 416}
 417
 418static int __maybe_unused mlxbf2_gpio_suspend(struct device *dev)
 419{
 420        struct mlxbf2_gpio_context *gs = dev_get_drvdata(dev);
 421
 422        gs->csave_regs->gpio_mode0 = readl(gs->gpio_io +
 423                YU_GPIO_MODE0);
 424        gs->csave_regs->gpio_mode1 = readl(gs->gpio_io +
 425                YU_GPIO_MODE1);
 426
 427        return 0;
 428}
 429
 430static int __maybe_unused mlxbf2_gpio_resume(struct device *dev)
 431{
 432        struct mlxbf2_gpio_context *gs = dev_get_drvdata(dev);
 433
 434        writel(gs->csave_regs->gpio_mode0, gs->gpio_io +
 435                YU_GPIO_MODE0);
 436        writel(gs->csave_regs->gpio_mode1, gs->gpio_io +
 437                YU_GPIO_MODE1);
 438
 439        return 0;
 440}
 441static SIMPLE_DEV_PM_OPS(mlxbf2_pm_ops, mlxbf2_gpio_suspend, mlxbf2_gpio_resume);
 442
 443static const struct acpi_device_id __maybe_unused mlxbf2_gpio_acpi_match[] = {
 444        { "MLNXBF22", 0 },
 445        {},
 446};
 447MODULE_DEVICE_TABLE(acpi, mlxbf2_gpio_acpi_match);
 448
 449static struct platform_driver mlxbf2_gpio_driver = {
 450        .driver = {
 451                .name = "mlxbf2_gpio",
 452                .acpi_match_table = mlxbf2_gpio_acpi_match,
 453                .pm = &mlxbf2_pm_ops,
 454        },
 455        .probe    = mlxbf2_gpio_probe,
 456};
 457
 458module_platform_driver(mlxbf2_gpio_driver);
 459
 460MODULE_DESCRIPTION("Mellanox BlueField-2 GPIO Driver");
 461MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>");
 462MODULE_LICENSE("GPL v2");
 463