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29#include <linux/dma-fence-array.h>
30#include <linux/interval_tree_generic.h>
31#include <linux/idr.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include "amdgpu.h"
37#include "amdgpu_trace.h"
38#include "amdgpu_amdkfd.h"
39#include "amdgpu_gmc.h"
40#include "amdgpu_xgmi.h"
41#include "amdgpu_dma_buf.h"
42#include "amdgpu_res_cursor.h"
43#include "kfd_svm.h"
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
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60
61
62
63
64
65
66#define START(node) ((node)->start)
67#define LAST(node) ((node)->last)
68
69INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
70 START, LAST, static, amdgpu_vm_it)
71
72#undef START
73#undef LAST
74
75
76
77
78struct amdgpu_prt_cb {
79
80
81
82
83 struct amdgpu_device *adev;
84
85
86
87
88 struct dma_fence_cb cb;
89};
90
91
92
93
94
95
96
97
98
99
100
101
102int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
103 u32 pasid)
104{
105 int r;
106
107 if (vm->pasid == pasid)
108 return 0;
109
110 if (vm->pasid) {
111 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
112 if (r < 0)
113 return r;
114
115 vm->pasid = 0;
116 }
117
118 if (pasid) {
119 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
120 GFP_KERNEL));
121 if (r < 0)
122 return r;
123
124 vm->pasid = pasid;
125 }
126
127
128 return 0;
129}
130
131
132
133
134
135
136static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
137{
138 mutex_lock(&vm->eviction_lock);
139 vm->saved_flags = memalloc_noreclaim_save();
140}
141
142static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
143{
144 if (mutex_trylock(&vm->eviction_lock)) {
145 vm->saved_flags = memalloc_noreclaim_save();
146 return 1;
147 }
148 return 0;
149}
150
151static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
152{
153 memalloc_noreclaim_restore(vm->saved_flags);
154 mutex_unlock(&vm->eviction_lock);
155}
156
157
158
159
160
161
162
163
164
165
166static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
167 unsigned level)
168{
169 switch (level) {
170 case AMDGPU_VM_PDB2:
171 case AMDGPU_VM_PDB1:
172 case AMDGPU_VM_PDB0:
173 return 9 * (AMDGPU_VM_PDB0 - level) +
174 adev->vm_manager.block_size;
175 case AMDGPU_VM_PTB:
176 return 0;
177 default:
178 return ~0;
179 }
180}
181
182
183
184
185
186
187
188
189
190
191static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
192 unsigned level)
193{
194 unsigned shift = amdgpu_vm_level_shift(adev,
195 adev->vm_manager.root_level);
196
197 if (level == adev->vm_manager.root_level)
198
199 return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
200 >> shift;
201 else if (level != AMDGPU_VM_PTB)
202
203 return 512;
204 else
205
206 return AMDGPU_VM_PTE_COUNT(adev);
207}
208
209
210
211
212
213
214
215
216
217static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
218{
219 unsigned shift;
220
221 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
222 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
223}
224
225
226
227
228
229
230
231
232
233
234static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
235 unsigned int level)
236{
237 if (level <= adev->vm_manager.root_level)
238 return 0xffffffff;
239 else if (level != AMDGPU_VM_PTB)
240 return 0x1ff;
241 else
242 return AMDGPU_VM_PTE_COUNT(adev) - 1;
243}
244
245
246
247
248
249
250
251
252
253
254static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
255{
256 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
257}
258
259
260
261
262
263
264
265
266
267static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
268{
269 struct amdgpu_vm *vm = vm_bo->vm;
270 struct amdgpu_bo *bo = vm_bo->bo;
271
272 vm_bo->moved = true;
273 if (bo->tbo.type == ttm_bo_type_kernel)
274 list_move(&vm_bo->vm_status, &vm->evicted);
275 else
276 list_move_tail(&vm_bo->vm_status, &vm->evicted);
277}
278
279
280
281
282
283
284
285
286static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
287{
288 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
289}
290
291
292
293
294
295
296
297
298
299static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
300{
301 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
302 vm_bo->moved = false;
303}
304
305
306
307
308
309
310
311
312
313static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
314{
315 spin_lock(&vm_bo->vm->invalidated_lock);
316 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
317 spin_unlock(&vm_bo->vm->invalidated_lock);
318}
319
320
321
322
323
324
325
326
327
328static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
329{
330 if (vm_bo->bo->parent)
331 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
332 else
333 amdgpu_vm_bo_idle(vm_bo);
334}
335
336
337
338
339
340
341
342
343
344static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
345{
346 spin_lock(&vm_bo->vm->invalidated_lock);
347 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
348 spin_unlock(&vm_bo->vm->invalidated_lock);
349}
350
351
352
353
354
355
356
357
358
359
360
361static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
362 struct amdgpu_vm *vm,
363 struct amdgpu_bo *bo)
364{
365 base->vm = vm;
366 base->bo = bo;
367 base->next = NULL;
368 INIT_LIST_HEAD(&base->vm_status);
369
370 if (!bo)
371 return;
372 base->next = bo->vm_bo;
373 bo->vm_bo = base;
374
375 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
376 return;
377
378 vm->bulk_moveable = false;
379 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
380 amdgpu_vm_bo_relocated(base);
381 else
382 amdgpu_vm_bo_idle(base);
383
384 if (bo->preferred_domains &
385 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
386 return;
387
388
389
390
391
392
393 amdgpu_vm_bo_evicted(base);
394}
395
396
397
398
399
400
401
402
403
404static struct amdgpu_vm_bo_base *amdgpu_vm_pt_parent(struct amdgpu_vm_bo_base *pt)
405{
406 struct amdgpu_bo *parent = pt->bo->parent;
407
408 if (!parent)
409 return NULL;
410
411 return parent->vm_bo;
412}
413
414
415
416
417struct amdgpu_vm_pt_cursor {
418 uint64_t pfn;
419 struct amdgpu_vm_bo_base *parent;
420 struct amdgpu_vm_bo_base *entry;
421 unsigned level;
422};
423
424
425
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427
428
429
430
431
432
433
434static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
435 struct amdgpu_vm *vm, uint64_t start,
436 struct amdgpu_vm_pt_cursor *cursor)
437{
438 cursor->pfn = start;
439 cursor->parent = NULL;
440 cursor->entry = &vm->root;
441 cursor->level = adev->vm_manager.root_level;
442}
443
444
445
446
447
448
449
450
451
452
453
454static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
455 struct amdgpu_vm_pt_cursor *cursor)
456{
457 unsigned mask, shift, idx;
458
459 if ((cursor->level == AMDGPU_VM_PTB) || !cursor->entry ||
460 !cursor->entry->bo)
461 return false;
462
463 mask = amdgpu_vm_entries_mask(adev, cursor->level);
464 shift = amdgpu_vm_level_shift(adev, cursor->level);
465
466 ++cursor->level;
467 idx = (cursor->pfn >> shift) & mask;
468 cursor->parent = cursor->entry;
469 cursor->entry = &to_amdgpu_bo_vm(cursor->entry->bo)->entries[idx];
470 return true;
471}
472
473
474
475
476
477
478
479
480
481
482
483static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
484 struct amdgpu_vm_pt_cursor *cursor)
485{
486 unsigned shift, num_entries;
487
488
489 if (!cursor->parent)
490 return false;
491
492
493 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
494 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
495
496 if (cursor->entry == &to_amdgpu_bo_vm(cursor->parent->bo)->entries[num_entries - 1])
497 return false;
498
499 cursor->pfn += 1ULL << shift;
500 cursor->pfn &= ~((1ULL << shift) - 1);
501 ++cursor->entry;
502 return true;
503}
504
505
506
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508
509
510
511
512
513
514static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
515{
516 if (!cursor->parent)
517 return false;
518
519 --cursor->level;
520 cursor->entry = cursor->parent;
521 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
522 return true;
523}
524
525
526
527
528
529
530
531
532
533static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
534 struct amdgpu_vm_pt_cursor *cursor)
535{
536
537 if (amdgpu_vm_pt_descendant(adev, cursor))
538 return;
539
540
541 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
542
543 if (!amdgpu_vm_pt_ancestor(cursor)) {
544 cursor->pfn = ~0ll;
545 return;
546 }
547 }
548}
549
550
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552
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557
558
559
560static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
561 struct amdgpu_vm *vm,
562 struct amdgpu_vm_pt_cursor *start,
563 struct amdgpu_vm_pt_cursor *cursor)
564{
565 if (start)
566 *cursor = *start;
567 else
568 amdgpu_vm_pt_start(adev, vm, 0, cursor);
569 while (amdgpu_vm_pt_descendant(adev, cursor));
570}
571
572
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575
576
577
578
579
580
581static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
582 struct amdgpu_vm_bo_base *entry)
583{
584 return entry && (!start || entry != start->entry);
585}
586
587
588
589
590
591
592
593
594
595static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
596 struct amdgpu_vm_pt_cursor *cursor)
597{
598 if (!cursor->entry)
599 return;
600
601 if (!cursor->parent)
602 cursor->entry = NULL;
603 else if (amdgpu_vm_pt_sibling(adev, cursor))
604 while (amdgpu_vm_pt_descendant(adev, cursor));
605 else
606 amdgpu_vm_pt_ancestor(cursor);
607}
608
609
610
611
612#define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
613 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
614 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
615 amdgpu_vm_pt_continue_dfs((start), (entry)); \
616 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
617
618
619
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621
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623
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625
626
627
628void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
629 struct list_head *validated,
630 struct amdgpu_bo_list_entry *entry)
631{
632 entry->priority = 0;
633 entry->tv.bo = &vm->root.bo->tbo;
634
635 entry->tv.num_shared = 4;
636 entry->user_pages = NULL;
637 list_add(&entry->tv.head, validated);
638}
639
640
641
642
643
644
645
646
647
648void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
649{
650 struct amdgpu_bo *abo;
651 struct amdgpu_vm_bo_base *bo_base;
652
653 if (!amdgpu_bo_is_amdgpu_bo(bo))
654 return;
655
656 if (bo->pin_count)
657 return;
658
659 abo = ttm_to_amdgpu_bo(bo);
660 if (!abo->parent)
661 return;
662 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
663 struct amdgpu_vm *vm = bo_base->vm;
664
665 if (abo->tbo.base.resv == vm->root.bo->tbo.base.resv)
666 vm->bulk_moveable = false;
667 }
668
669}
670
671
672
673
674
675
676
677
678
679void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
680 struct amdgpu_vm *vm)
681{
682 struct amdgpu_vm_bo_base *bo_base;
683
684 if (vm->bulk_moveable) {
685 spin_lock(&adev->mman.bdev.lru_lock);
686 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
687 spin_unlock(&adev->mman.bdev.lru_lock);
688 return;
689 }
690
691 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
692
693 spin_lock(&adev->mman.bdev.lru_lock);
694 list_for_each_entry(bo_base, &vm->idle, vm_status) {
695 struct amdgpu_bo *bo = bo_base->bo;
696 struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
697
698 if (!bo->parent)
699 continue;
700
701 ttm_bo_move_to_lru_tail(&bo->tbo, bo->tbo.resource,
702 &vm->lru_bulk_move);
703 if (shadow)
704 ttm_bo_move_to_lru_tail(&shadow->tbo,
705 shadow->tbo.resource,
706 &vm->lru_bulk_move);
707 }
708 spin_unlock(&adev->mman.bdev.lru_lock);
709
710 vm->bulk_moveable = true;
711}
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
727 int (*validate)(void *p, struct amdgpu_bo *bo),
728 void *param)
729{
730 struct amdgpu_vm_bo_base *bo_base, *tmp;
731 int r;
732
733 vm->bulk_moveable &= list_empty(&vm->evicted);
734
735 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
736 struct amdgpu_bo *bo = bo_base->bo;
737 struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
738
739 r = validate(param, bo);
740 if (r)
741 return r;
742 if (shadow) {
743 r = validate(param, shadow);
744 if (r)
745 return r;
746 }
747
748 if (bo->tbo.type != ttm_bo_type_kernel) {
749 amdgpu_vm_bo_moved(bo_base);
750 } else {
751 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
752 amdgpu_vm_bo_relocated(bo_base);
753 }
754 }
755
756 amdgpu_vm_eviction_lock(vm);
757 vm->evicting = false;
758 amdgpu_vm_eviction_unlock(vm);
759
760 return 0;
761}
762
763
764
765
766
767
768
769
770
771
772
773bool amdgpu_vm_ready(struct amdgpu_vm *vm)
774{
775 return list_empty(&vm->evicted);
776}
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
792 struct amdgpu_vm *vm,
793 struct amdgpu_bo_vm *vmbo,
794 bool immediate)
795{
796 struct ttm_operation_ctx ctx = { true, false };
797 unsigned level = adev->vm_manager.root_level;
798 struct amdgpu_vm_update_params params;
799 struct amdgpu_bo *ancestor = &vmbo->bo;
800 struct amdgpu_bo *bo = &vmbo->bo;
801 unsigned entries, ats_entries;
802 uint64_t addr;
803 int r, idx;
804
805
806 if (ancestor->parent) {
807 ++level;
808 while (ancestor->parent->parent) {
809 ++level;
810 ancestor = ancestor->parent;
811 }
812 }
813
814 entries = amdgpu_bo_size(bo) / 8;
815 if (!vm->pte_support_ats) {
816 ats_entries = 0;
817
818 } else if (!bo->parent) {
819 ats_entries = amdgpu_vm_num_ats_entries(adev);
820 ats_entries = min(ats_entries, entries);
821 entries -= ats_entries;
822
823 } else {
824 struct amdgpu_vm_bo_base *pt;
825
826 pt = ancestor->vm_bo;
827 ats_entries = amdgpu_vm_num_ats_entries(adev);
828 if ((pt - to_amdgpu_bo_vm(vm->root.bo)->entries) >= ats_entries) {
829 ats_entries = 0;
830 } else {
831 ats_entries = entries;
832 entries = 0;
833 }
834 }
835
836 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
837 if (r)
838 return r;
839
840 if (vmbo->shadow) {
841 struct amdgpu_bo *shadow = vmbo->shadow;
842
843 r = ttm_bo_validate(&shadow->tbo, &shadow->placement, &ctx);
844 if (r)
845 return r;
846 }
847
848 if (!drm_dev_enter(adev_to_drm(adev), &idx))
849 return -ENODEV;
850
851 r = vm->update_funcs->map_table(vmbo);
852 if (r)
853 goto exit;
854
855 memset(¶ms, 0, sizeof(params));
856 params.adev = adev;
857 params.vm = vm;
858 params.immediate = immediate;
859
860 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
861 if (r)
862 goto exit;
863
864 addr = 0;
865 if (ats_entries) {
866 uint64_t value = 0, flags;
867
868 flags = AMDGPU_PTE_DEFAULT_ATC;
869 if (level != AMDGPU_VM_PTB) {
870
871 flags |= AMDGPU_PDE_PTE;
872 amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
873 }
874
875 r = vm->update_funcs->update(¶ms, vmbo, addr, 0, ats_entries,
876 value, flags);
877 if (r)
878 goto exit;
879
880 addr += ats_entries * 8;
881 }
882
883 if (entries) {
884 uint64_t value = 0, flags = 0;
885
886 if (adev->asic_type >= CHIP_VEGA10) {
887 if (level != AMDGPU_VM_PTB) {
888
889 flags |= AMDGPU_PDE_PTE;
890 amdgpu_gmc_get_vm_pde(adev, level,
891 &value, &flags);
892 } else {
893
894 flags = AMDGPU_PTE_EXECUTABLE;
895 }
896 }
897
898 r = vm->update_funcs->update(¶ms, vmbo, addr, 0, entries,
899 value, flags);
900 if (r)
901 goto exit;
902 }
903
904 r = vm->update_funcs->commit(¶ms, NULL);
905exit:
906 drm_dev_exit(idx);
907 return r;
908}
909
910
911
912
913
914
915
916
917
918
919static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
920 struct amdgpu_vm *vm,
921 int level, bool immediate,
922 struct amdgpu_bo_vm **vmbo)
923{
924 struct amdgpu_bo_param bp;
925 struct amdgpu_bo *bo;
926 struct dma_resv *resv;
927 unsigned int num_entries;
928 int r;
929
930 memset(&bp, 0, sizeof(bp));
931
932 bp.size = amdgpu_vm_bo_size(adev, level);
933 bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
934 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
935 bp.domain = amdgpu_bo_get_preferred_domain(adev, bp.domain);
936 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
937 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
938
939 if (level < AMDGPU_VM_PTB)
940 num_entries = amdgpu_vm_num_entries(adev, level);
941 else
942 num_entries = 0;
943
944 bp.bo_ptr_size = struct_size((*vmbo), entries, num_entries);
945
946 if (vm->use_cpu_for_update)
947 bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
948
949 bp.type = ttm_bo_type_kernel;
950 bp.no_wait_gpu = immediate;
951 if (vm->root.bo)
952 bp.resv = vm->root.bo->tbo.base.resv;
953
954 r = amdgpu_bo_create_vm(adev, &bp, vmbo);
955 if (r)
956 return r;
957
958 bo = &(*vmbo)->bo;
959 if (vm->is_compute_context || (adev->flags & AMD_IS_APU)) {
960 (*vmbo)->shadow = NULL;
961 return 0;
962 }
963
964 if (!bp.resv)
965 WARN_ON(dma_resv_lock(bo->tbo.base.resv,
966 NULL));
967 resv = bp.resv;
968 memset(&bp, 0, sizeof(bp));
969 bp.size = amdgpu_vm_bo_size(adev, level);
970 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
971 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
972 bp.type = ttm_bo_type_kernel;
973 bp.resv = bo->tbo.base.resv;
974 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
975
976 r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow);
977
978 if (!resv)
979 dma_resv_unlock(bo->tbo.base.resv);
980
981 if (r) {
982 amdgpu_bo_unref(&bo);
983 return r;
984 }
985
986 (*vmbo)->shadow->parent = amdgpu_bo_ref(bo);
987 amdgpu_bo_add_to_shadow_list(*vmbo);
988
989 return 0;
990}
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
1007 struct amdgpu_vm *vm,
1008 struct amdgpu_vm_pt_cursor *cursor,
1009 bool immediate)
1010{
1011 struct amdgpu_vm_bo_base *entry = cursor->entry;
1012 struct amdgpu_bo *pt_bo;
1013 struct amdgpu_bo_vm *pt;
1014 int r;
1015
1016 if (entry->bo)
1017 return 0;
1018
1019 r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
1020 if (r)
1021 return r;
1022
1023
1024
1025
1026 pt_bo = &pt->bo;
1027 pt_bo->parent = amdgpu_bo_ref(cursor->parent->bo);
1028 amdgpu_vm_bo_base_init(entry, vm, pt_bo);
1029 r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
1030 if (r)
1031 goto error_free_pt;
1032
1033 return 0;
1034
1035error_free_pt:
1036 amdgpu_bo_unref(&pt->shadow);
1037 amdgpu_bo_unref(&pt_bo);
1038 return r;
1039}
1040
1041
1042
1043
1044
1045
1046static void amdgpu_vm_free_table(struct amdgpu_vm_bo_base *entry)
1047{
1048 struct amdgpu_bo *shadow;
1049
1050 if (!entry->bo)
1051 return;
1052 shadow = amdgpu_bo_shadowed(entry->bo);
1053 entry->bo->vm_bo = NULL;
1054 list_del(&entry->vm_status);
1055 amdgpu_bo_unref(&shadow);
1056 amdgpu_bo_unref(&entry->bo);
1057}
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
1069 struct amdgpu_vm *vm,
1070 struct amdgpu_vm_pt_cursor *start)
1071{
1072 struct amdgpu_vm_pt_cursor cursor;
1073 struct amdgpu_vm_bo_base *entry;
1074
1075 vm->bulk_moveable = false;
1076
1077 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
1078 amdgpu_vm_free_table(entry);
1079
1080 if (start)
1081 amdgpu_vm_free_table(start->entry);
1082}
1083
1084
1085
1086
1087
1088
1089void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
1090{
1091 const struct amdgpu_ip_block *ip_block;
1092 bool has_compute_vm_bug;
1093 struct amdgpu_ring *ring;
1094 int i;
1095
1096 has_compute_vm_bug = false;
1097
1098 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
1099 if (ip_block) {
1100
1101
1102 if (ip_block->version->major <= 7)
1103 has_compute_vm_bug = true;
1104 else if (ip_block->version->major == 8)
1105 if (adev->gfx.mec_fw_version < 673)
1106 has_compute_vm_bug = true;
1107 }
1108
1109 for (i = 0; i < adev->num_rings; i++) {
1110 ring = adev->rings[i];
1111 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
1112
1113 ring->has_compute_vm_bug = has_compute_vm_bug;
1114 else
1115 ring->has_compute_vm_bug = false;
1116 }
1117}
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
1129 struct amdgpu_job *job)
1130{
1131 struct amdgpu_device *adev = ring->adev;
1132 unsigned vmhub = ring->funcs->vmhub;
1133 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1134 struct amdgpu_vmid *id;
1135 bool gds_switch_needed;
1136 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1137
1138 if (job->vmid == 0)
1139 return false;
1140 id = &id_mgr->ids[job->vmid];
1141 gds_switch_needed = ring->funcs->emit_gds_switch && (
1142 id->gds_base != job->gds_base ||
1143 id->gds_size != job->gds_size ||
1144 id->gws_base != job->gws_base ||
1145 id->gws_size != job->gws_size ||
1146 id->oa_base != job->oa_base ||
1147 id->oa_size != job->oa_size);
1148
1149 if (amdgpu_vmid_had_gpu_reset(adev, id))
1150 return true;
1151
1152 return vm_flush_needed || gds_switch_needed;
1153}
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
1168 bool need_pipe_sync)
1169{
1170 struct amdgpu_device *adev = ring->adev;
1171 unsigned vmhub = ring->funcs->vmhub;
1172 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1173 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1174 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1175 id->gds_base != job->gds_base ||
1176 id->gds_size != job->gds_size ||
1177 id->gws_base != job->gws_base ||
1178 id->gws_size != job->gws_size ||
1179 id->oa_base != job->oa_base ||
1180 id->oa_size != job->oa_size);
1181 bool vm_flush_needed = job->vm_needs_flush;
1182 struct dma_fence *fence = NULL;
1183 bool pasid_mapping_needed = false;
1184 unsigned patch_offset = 0;
1185 bool update_spm_vmid_needed = (job->vm && (job->vm->reserved_vmid[vmhub] != NULL));
1186 int r;
1187
1188 if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
1189 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
1190
1191 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1192 gds_switch_needed = true;
1193 vm_flush_needed = true;
1194 pasid_mapping_needed = true;
1195 }
1196
1197 mutex_lock(&id_mgr->lock);
1198 if (id->pasid != job->pasid || !id->pasid_mapping ||
1199 !dma_fence_is_signaled(id->pasid_mapping))
1200 pasid_mapping_needed = true;
1201 mutex_unlock(&id_mgr->lock);
1202
1203 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1204 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1205 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1206 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1207 ring->funcs->emit_wreg;
1208
1209 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1210 return 0;
1211
1212 if (ring->funcs->init_cond_exec)
1213 patch_offset = amdgpu_ring_init_cond_exec(ring);
1214
1215 if (need_pipe_sync)
1216 amdgpu_ring_emit_pipeline_sync(ring);
1217
1218 if (vm_flush_needed) {
1219 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1220 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1221 }
1222
1223 if (pasid_mapping_needed)
1224 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1225
1226 if (vm_flush_needed || pasid_mapping_needed) {
1227 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
1228 if (r)
1229 return r;
1230 }
1231
1232 if (vm_flush_needed) {
1233 mutex_lock(&id_mgr->lock);
1234 dma_fence_put(id->last_flush);
1235 id->last_flush = dma_fence_get(fence);
1236 id->current_gpu_reset_count =
1237 atomic_read(&adev->gpu_reset_counter);
1238 mutex_unlock(&id_mgr->lock);
1239 }
1240
1241 if (pasid_mapping_needed) {
1242 mutex_lock(&id_mgr->lock);
1243 id->pasid = job->pasid;
1244 dma_fence_put(id->pasid_mapping);
1245 id->pasid_mapping = dma_fence_get(fence);
1246 mutex_unlock(&id_mgr->lock);
1247 }
1248 dma_fence_put(fence);
1249
1250 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1251 id->gds_base = job->gds_base;
1252 id->gds_size = job->gds_size;
1253 id->gws_base = job->gws_base;
1254 id->gws_size = job->gws_size;
1255 id->oa_base = job->oa_base;
1256 id->oa_size = job->oa_size;
1257 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1258 job->gds_size, job->gws_base,
1259 job->gws_size, job->oa_base,
1260 job->oa_size);
1261 }
1262
1263 if (ring->funcs->patch_cond_exec)
1264 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1265
1266
1267 if (ring->funcs->emit_switch_buffer) {
1268 amdgpu_ring_emit_switch_buffer(ring);
1269 amdgpu_ring_emit_switch_buffer(ring);
1270 }
1271 return 0;
1272}
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1290 struct amdgpu_bo *bo)
1291{
1292 struct amdgpu_vm_bo_base *base;
1293
1294 for (base = bo->vm_bo; base; base = base->next) {
1295 if (base->vm != vm)
1296 continue;
1297
1298 return container_of(base, struct amdgpu_bo_va, base);
1299 }
1300 return NULL;
1301}
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1316{
1317 uint64_t result;
1318
1319
1320 result = pages_addr[addr >> PAGE_SHIFT];
1321
1322
1323 result |= addr & (~PAGE_MASK);
1324
1325 result &= 0xFFFFFFFFFFFFF000ULL;
1326
1327 return result;
1328}
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1340 struct amdgpu_vm *vm,
1341 struct amdgpu_vm_bo_base *entry)
1342{
1343 struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
1344 struct amdgpu_bo *bo = parent->bo, *pbo;
1345 uint64_t pde, pt, flags;
1346 unsigned level;
1347
1348 for (level = 0, pbo = bo->parent; pbo; ++level)
1349 pbo = pbo->parent;
1350
1351 level += params->adev->vm_manager.root_level;
1352 amdgpu_gmc_get_pde_for_bo(entry->bo, level, &pt, &flags);
1353 pde = (entry - to_amdgpu_bo_vm(parent->bo)->entries) * 8;
1354 return vm->update_funcs->update(params, to_amdgpu_bo_vm(bo), pde, pt,
1355 1, 0, flags);
1356}
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1367 struct amdgpu_vm *vm)
1368{
1369 struct amdgpu_vm_pt_cursor cursor;
1370 struct amdgpu_vm_bo_base *entry;
1371
1372 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1373 if (entry->bo && !entry->moved)
1374 amdgpu_vm_bo_relocated(entry);
1375}
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
1390 struct amdgpu_vm *vm, bool immediate)
1391{
1392 struct amdgpu_vm_update_params params;
1393 int r, idx;
1394
1395 if (list_empty(&vm->relocated))
1396 return 0;
1397
1398 if (!drm_dev_enter(adev_to_drm(adev), &idx))
1399 return -ENODEV;
1400
1401 memset(¶ms, 0, sizeof(params));
1402 params.adev = adev;
1403 params.vm = vm;
1404 params.immediate = immediate;
1405
1406 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
1407 if (r)
1408 goto exit;
1409
1410 while (!list_empty(&vm->relocated)) {
1411 struct amdgpu_vm_bo_base *entry;
1412
1413 entry = list_first_entry(&vm->relocated,
1414 struct amdgpu_vm_bo_base,
1415 vm_status);
1416 amdgpu_vm_bo_idle(entry);
1417
1418 r = amdgpu_vm_update_pde(¶ms, vm, entry);
1419 if (r)
1420 goto error;
1421 }
1422
1423 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1424 if (r)
1425 goto error;
1426 drm_dev_exit(idx);
1427 return 0;
1428
1429error:
1430 amdgpu_vm_invalidate_pds(adev, vm);
1431exit:
1432 drm_dev_exit(idx);
1433 return r;
1434}
1435
1436
1437
1438
1439
1440
1441static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1442 struct amdgpu_bo_vm *pt, unsigned int level,
1443 uint64_t pe, uint64_t addr,
1444 unsigned int count, uint32_t incr,
1445 uint64_t flags)
1446
1447{
1448 if (level != AMDGPU_VM_PTB) {
1449 flags |= AMDGPU_PDE_PTE;
1450 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1451
1452 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1453 !(flags & AMDGPU_PTE_VALID) &&
1454 !(flags & AMDGPU_PTE_PRT)) {
1455
1456
1457 flags |= AMDGPU_PTE_EXECUTABLE;
1458 }
1459
1460 params->vm->update_funcs->update(params, pt, pe, addr, count, incr,
1461 flags);
1462}
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1477 uint64_t start, uint64_t end, uint64_t flags,
1478 unsigned int *frag, uint64_t *frag_end)
1479{
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501 unsigned max_frag;
1502
1503 if (params->adev->asic_type < CHIP_VEGA10)
1504 max_frag = params->adev->vm_manager.fragment_size;
1505 else
1506 max_frag = 31;
1507
1508
1509 if (params->pages_addr) {
1510 *frag = 0;
1511 *frag_end = end;
1512 return;
1513 }
1514
1515
1516 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1517 if (*frag >= max_frag) {
1518 *frag = max_frag;
1519 *frag_end = end & ~((1ULL << max_frag) - 1);
1520 } else {
1521 *frag_end = start + (1 << *frag);
1522 }
1523}
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1540 uint64_t start, uint64_t end,
1541 uint64_t dst, uint64_t flags)
1542{
1543 struct amdgpu_device *adev = params->adev;
1544 struct amdgpu_vm_pt_cursor cursor;
1545 uint64_t frag_start = start, frag_end;
1546 unsigned int frag;
1547 int r;
1548
1549
1550 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1551
1552
1553 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1554 while (cursor.pfn < end) {
1555 unsigned shift, parent_shift, mask;
1556 uint64_t incr, entry_end, pe_start;
1557 struct amdgpu_bo *pt;
1558
1559 if (!params->unlocked) {
1560
1561
1562
1563 r = amdgpu_vm_alloc_pts(params->adev, params->vm,
1564 &cursor, params->immediate);
1565 if (r)
1566 return r;
1567 }
1568
1569 shift = amdgpu_vm_level_shift(adev, cursor.level);
1570 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1571 if (params->unlocked) {
1572
1573 if (amdgpu_vm_pt_descendant(adev, &cursor))
1574 continue;
1575 } else if (adev->asic_type < CHIP_VEGA10 &&
1576 (flags & AMDGPU_PTE_VALID)) {
1577
1578 if (cursor.level != AMDGPU_VM_PTB) {
1579 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1580 return -ENOENT;
1581 continue;
1582 }
1583 } else if (frag < shift) {
1584
1585
1586
1587
1588 if (amdgpu_vm_pt_descendant(adev, &cursor))
1589 continue;
1590 } else if (frag >= parent_shift) {
1591
1592
1593
1594 if (!amdgpu_vm_pt_ancestor(&cursor))
1595 return -EINVAL;
1596 continue;
1597 }
1598
1599 pt = cursor.entry->bo;
1600 if (!pt) {
1601
1602 if (flags & AMDGPU_PTE_VALID)
1603 return -ENOENT;
1604
1605
1606
1607
1608 if (!amdgpu_vm_pt_ancestor(&cursor))
1609 return -EINVAL;
1610
1611 pt = cursor.entry->bo;
1612 shift = parent_shift;
1613 frag_end = max(frag_end, ALIGN(frag_start + 1,
1614 1ULL << shift));
1615 }
1616
1617
1618 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1619 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1620 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1621 entry_end = ((uint64_t)mask + 1) << shift;
1622 entry_end += cursor.pfn & ~(entry_end - 1);
1623 entry_end = min(entry_end, end);
1624
1625 do {
1626 struct amdgpu_vm *vm = params->vm;
1627 uint64_t upd_end = min(entry_end, frag_end);
1628 unsigned nptes = (upd_end - frag_start) >> shift;
1629 uint64_t upd_flags = flags | AMDGPU_PTE_FRAG(frag);
1630
1631
1632
1633
1634 nptes = max(nptes, 1u);
1635
1636 trace_amdgpu_vm_update_ptes(params, frag_start, upd_end,
1637 nptes, dst, incr, upd_flags,
1638 vm->task_info.pid,
1639 vm->immediate.fence_context);
1640 amdgpu_vm_update_flags(params, to_amdgpu_bo_vm(pt),
1641 cursor.level, pe_start, dst,
1642 nptes, incr, upd_flags);
1643
1644 pe_start += nptes * 8;
1645 dst += nptes * incr;
1646
1647 frag_start = upd_end;
1648 if (frag_start >= frag_end) {
1649
1650 amdgpu_vm_fragment(params, frag_start, end,
1651 flags, &frag, &frag_end);
1652 if (frag < shift)
1653 break;
1654 }
1655 } while (frag_start < entry_end);
1656
1657 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1658
1659
1660
1661
1662
1663
1664 while (cursor.pfn < frag_start) {
1665
1666 if (cursor.entry->bo) {
1667 params->table_freed = true;
1668 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1669 }
1670 amdgpu_vm_pt_next(adev, &cursor);
1671 }
1672
1673 } else if (frag >= shift) {
1674
1675 amdgpu_vm_pt_next(adev, &cursor);
1676 }
1677 }
1678
1679 return 0;
1680}
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1706 struct amdgpu_device *bo_adev,
1707 struct amdgpu_vm *vm, bool immediate,
1708 bool unlocked, struct dma_resv *resv,
1709 uint64_t start, uint64_t last,
1710 uint64_t flags, uint64_t offset,
1711 struct ttm_resource *res,
1712 dma_addr_t *pages_addr,
1713 struct dma_fence **fence,
1714 bool *table_freed)
1715{
1716 struct amdgpu_vm_update_params params;
1717 struct amdgpu_res_cursor cursor;
1718 enum amdgpu_sync_mode sync_mode;
1719 int r, idx;
1720
1721 if (!drm_dev_enter(adev_to_drm(adev), &idx))
1722 return -ENODEV;
1723
1724 memset(¶ms, 0, sizeof(params));
1725 params.adev = adev;
1726 params.vm = vm;
1727 params.immediate = immediate;
1728 params.pages_addr = pages_addr;
1729 params.unlocked = unlocked;
1730
1731
1732
1733
1734 if (!(flags & AMDGPU_PTE_VALID))
1735 sync_mode = AMDGPU_SYNC_EQ_OWNER;
1736 else
1737 sync_mode = AMDGPU_SYNC_EXPLICIT;
1738
1739 amdgpu_vm_eviction_lock(vm);
1740 if (vm->evicting) {
1741 r = -EBUSY;
1742 goto error_unlock;
1743 }
1744
1745 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1746 struct dma_fence *tmp = dma_fence_get_stub();
1747
1748 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
1749 swap(vm->last_unlocked, tmp);
1750 dma_fence_put(tmp);
1751 }
1752
1753 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
1754 if (r)
1755 goto error_unlock;
1756
1757 amdgpu_res_first(pages_addr ? NULL : res, offset,
1758 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
1759 while (cursor.remaining) {
1760 uint64_t tmp, num_entries, addr;
1761
1762 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
1763 if (pages_addr) {
1764 bool contiguous = true;
1765
1766 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1767 uint64_t pfn = cursor.start >> PAGE_SHIFT;
1768 uint64_t count;
1769
1770 contiguous = pages_addr[pfn + 1] ==
1771 pages_addr[pfn] + PAGE_SIZE;
1772
1773 tmp = num_entries /
1774 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1775 for (count = 2; count < tmp; ++count) {
1776 uint64_t idx = pfn + count;
1777
1778 if (contiguous != (pages_addr[idx] ==
1779 pages_addr[idx - 1] + PAGE_SIZE))
1780 break;
1781 }
1782 num_entries = count *
1783 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1784 }
1785
1786 if (!contiguous) {
1787 addr = cursor.start;
1788 params.pages_addr = pages_addr;
1789 } else {
1790 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1791 params.pages_addr = NULL;
1792 }
1793
1794 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1795 addr = bo_adev->vm_manager.vram_base_offset +
1796 cursor.start;
1797 } else {
1798 addr = 0;
1799 }
1800
1801 tmp = start + num_entries;
1802 r = amdgpu_vm_update_ptes(¶ms, start, tmp, addr, flags);
1803 if (r)
1804 goto error_unlock;
1805
1806 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1807 start = tmp;
1808 }
1809
1810 r = vm->update_funcs->commit(¶ms, fence);
1811
1812 if (table_freed)
1813 *table_freed = *table_freed || params.table_freed;
1814
1815error_unlock:
1816 amdgpu_vm_eviction_unlock(vm);
1817 drm_dev_exit(idx);
1818 return r;
1819}
1820
1821void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
1822 uint64_t *gtt_mem, uint64_t *cpu_mem)
1823{
1824 struct amdgpu_bo_va *bo_va, *tmp;
1825
1826 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
1827 if (!bo_va->base.bo)
1828 continue;
1829 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1830 gtt_mem, cpu_mem);
1831 }
1832 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
1833 if (!bo_va->base.bo)
1834 continue;
1835 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1836 gtt_mem, cpu_mem);
1837 }
1838 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
1839 if (!bo_va->base.bo)
1840 continue;
1841 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1842 gtt_mem, cpu_mem);
1843 }
1844 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1845 if (!bo_va->base.bo)
1846 continue;
1847 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1848 gtt_mem, cpu_mem);
1849 }
1850 spin_lock(&vm->invalidated_lock);
1851 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
1852 if (!bo_va->base.bo)
1853 continue;
1854 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1855 gtt_mem, cpu_mem);
1856 }
1857 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
1858 if (!bo_va->base.bo)
1859 continue;
1860 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1861 gtt_mem, cpu_mem);
1862 }
1863 spin_unlock(&vm->invalidated_lock);
1864}
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1879 bool clear, bool *table_freed)
1880{
1881 struct amdgpu_bo *bo = bo_va->base.bo;
1882 struct amdgpu_vm *vm = bo_va->base.vm;
1883 struct amdgpu_bo_va_mapping *mapping;
1884 dma_addr_t *pages_addr = NULL;
1885 struct ttm_resource *mem;
1886 struct dma_fence **last_update;
1887 struct dma_resv *resv;
1888 uint64_t flags;
1889 struct amdgpu_device *bo_adev = adev;
1890 int r;
1891
1892 if (clear || !bo) {
1893 mem = NULL;
1894 resv = vm->root.bo->tbo.base.resv;
1895 } else {
1896 struct drm_gem_object *obj = &bo->tbo.base;
1897
1898 resv = bo->tbo.base.resv;
1899 if (obj->import_attach && bo_va->is_xgmi) {
1900 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1901 struct drm_gem_object *gobj = dma_buf->priv;
1902 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1903
1904 if (abo->tbo.resource->mem_type == TTM_PL_VRAM)
1905 bo = gem_to_amdgpu_bo(gobj);
1906 }
1907 mem = bo->tbo.resource;
1908 if (mem->mem_type == TTM_PL_TT ||
1909 mem->mem_type == AMDGPU_PL_PREEMPT)
1910 pages_addr = bo->tbo.ttm->dma_address;
1911 }
1912
1913 if (bo) {
1914 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1915
1916 if (amdgpu_bo_encrypted(bo))
1917 flags |= AMDGPU_PTE_TMZ;
1918
1919 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1920 } else {
1921 flags = 0x0;
1922 }
1923
1924 if (clear || (bo && bo->tbo.base.resv ==
1925 vm->root.bo->tbo.base.resv))
1926 last_update = &vm->last_update;
1927 else
1928 last_update = &bo_va->last_pt_update;
1929
1930 if (!clear && bo_va->base.moved) {
1931 bo_va->base.moved = false;
1932 list_splice_init(&bo_va->valids, &bo_va->invalids);
1933
1934 } else if (bo_va->cleared != clear) {
1935 list_splice_init(&bo_va->valids, &bo_va->invalids);
1936 }
1937
1938 list_for_each_entry(mapping, &bo_va->invalids, list) {
1939 uint64_t update_flags = flags;
1940
1941
1942
1943
1944 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1945 update_flags &= ~AMDGPU_PTE_READABLE;
1946 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1947 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1948
1949
1950 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1951
1952 trace_amdgpu_vm_bo_update(mapping);
1953
1954 r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false,
1955 resv, mapping->start,
1956 mapping->last, update_flags,
1957 mapping->offset, mem,
1958 pages_addr, last_update, table_freed);
1959 if (r)
1960 return r;
1961 }
1962
1963
1964
1965
1966
1967 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1968 uint32_t mem_type = bo->tbo.resource->mem_type;
1969
1970 if (!(bo->preferred_domains &
1971 amdgpu_mem_type_to_domain(mem_type)))
1972 amdgpu_vm_bo_evicted(&bo_va->base);
1973 else
1974 amdgpu_vm_bo_idle(&bo_va->base);
1975 } else {
1976 amdgpu_vm_bo_done(&bo_va->base);
1977 }
1978
1979 list_splice_init(&bo_va->invalids, &bo_va->valids);
1980 bo_va->cleared = clear;
1981
1982 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1983 list_for_each_entry(mapping, &bo_va->valids, list)
1984 trace_amdgpu_vm_bo_mapping(mapping);
1985 }
1986
1987 return 0;
1988}
1989
1990
1991
1992
1993
1994
1995static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1996{
1997 unsigned long flags;
1998 bool enable;
1999
2000 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
2001 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
2002 adev->gmc.gmc_funcs->set_prt(adev, enable);
2003 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
2004}
2005
2006
2007
2008
2009
2010
2011static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
2012{
2013 if (!adev->gmc.gmc_funcs->set_prt)
2014 return;
2015
2016 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
2017 amdgpu_vm_update_prt_state(adev);
2018}
2019
2020
2021
2022
2023
2024
2025static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
2026{
2027 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
2028 amdgpu_vm_update_prt_state(adev);
2029}
2030
2031
2032
2033
2034
2035
2036
2037static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
2038{
2039 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
2040
2041 amdgpu_vm_prt_put(cb->adev);
2042 kfree(cb);
2043}
2044
2045
2046
2047
2048
2049
2050
2051static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
2052 struct dma_fence *fence)
2053{
2054 struct amdgpu_prt_cb *cb;
2055
2056 if (!adev->gmc.gmc_funcs->set_prt)
2057 return;
2058
2059 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
2060 if (!cb) {
2061
2062 if (fence)
2063 dma_fence_wait(fence, false);
2064
2065 amdgpu_vm_prt_put(adev);
2066 } else {
2067 cb->adev = adev;
2068 if (!fence || dma_fence_add_callback(fence, &cb->cb,
2069 amdgpu_vm_prt_cb))
2070 amdgpu_vm_prt_cb(fence, &cb->cb);
2071 }
2072}
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
2085 struct amdgpu_vm *vm,
2086 struct amdgpu_bo_va_mapping *mapping,
2087 struct dma_fence *fence)
2088{
2089 if (mapping->flags & AMDGPU_PTE_PRT)
2090 amdgpu_vm_add_prt_cb(adev, fence);
2091 kfree(mapping);
2092}
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2103{
2104 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
2105 struct dma_fence *excl, **shared;
2106 unsigned i, shared_count;
2107 int r;
2108
2109 r = dma_resv_get_fences(resv, &excl, &shared_count, &shared);
2110 if (r) {
2111
2112
2113
2114 dma_resv_wait_timeout(resv, true, false,
2115 MAX_SCHEDULE_TIMEOUT);
2116 return;
2117 }
2118
2119
2120 amdgpu_vm_prt_get(adev);
2121 amdgpu_vm_add_prt_cb(adev, excl);
2122
2123 for (i = 0; i < shared_count; ++i) {
2124 amdgpu_vm_prt_get(adev);
2125 amdgpu_vm_add_prt_cb(adev, shared[i]);
2126 }
2127
2128 kfree(shared);
2129}
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2147 struct amdgpu_vm *vm,
2148 struct dma_fence **fence)
2149{
2150 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
2151 struct amdgpu_bo_va_mapping *mapping;
2152 uint64_t init_pte_value = 0;
2153 struct dma_fence *f = NULL;
2154 int r;
2155
2156 while (!list_empty(&vm->freed)) {
2157 mapping = list_first_entry(&vm->freed,
2158 struct amdgpu_bo_va_mapping, list);
2159 list_del(&mapping->list);
2160
2161 if (vm->pte_support_ats &&
2162 mapping->start < AMDGPU_GMC_HOLE_START)
2163 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2164
2165 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false,
2166 resv, mapping->start,
2167 mapping->last, init_pte_value,
2168 0, NULL, NULL, &f, NULL);
2169 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2170 if (r) {
2171 dma_fence_put(f);
2172 return r;
2173 }
2174 }
2175
2176 if (fence && f) {
2177 dma_fence_put(*fence);
2178 *fence = f;
2179 } else {
2180 dma_fence_put(f);
2181 }
2182
2183 return 0;
2184
2185}
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2201 struct amdgpu_vm *vm)
2202{
2203 struct amdgpu_bo_va *bo_va, *tmp;
2204 struct dma_resv *resv;
2205 bool clear;
2206 int r;
2207
2208 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2209
2210 r = amdgpu_vm_bo_update(adev, bo_va, false, NULL);
2211 if (r)
2212 return r;
2213 }
2214
2215 spin_lock(&vm->invalidated_lock);
2216 while (!list_empty(&vm->invalidated)) {
2217 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2218 base.vm_status);
2219 resv = bo_va->base.bo->tbo.base.resv;
2220 spin_unlock(&vm->invalidated_lock);
2221
2222
2223 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
2224 clear = false;
2225
2226 else
2227 clear = true;
2228
2229 r = amdgpu_vm_bo_update(adev, bo_va, clear, NULL);
2230 if (r)
2231 return r;
2232
2233 if (!clear)
2234 dma_resv_unlock(resv);
2235 spin_lock(&vm->invalidated_lock);
2236 }
2237 spin_unlock(&vm->invalidated_lock);
2238
2239 return 0;
2240}
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2258 struct amdgpu_vm *vm,
2259 struct amdgpu_bo *bo)
2260{
2261 struct amdgpu_bo_va *bo_va;
2262
2263 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2264 if (bo_va == NULL) {
2265 return NULL;
2266 }
2267 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2268
2269 bo_va->ref_count = 1;
2270 INIT_LIST_HEAD(&bo_va->valids);
2271 INIT_LIST_HEAD(&bo_va->invalids);
2272
2273 if (!bo)
2274 return bo_va;
2275
2276 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
2277 bo_va->is_xgmi = true;
2278
2279 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
2280 }
2281
2282 return bo_va;
2283}
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2296 struct amdgpu_bo_va *bo_va,
2297 struct amdgpu_bo_va_mapping *mapping)
2298{
2299 struct amdgpu_vm *vm = bo_va->base.vm;
2300 struct amdgpu_bo *bo = bo_va->base.bo;
2301
2302 mapping->bo_va = bo_va;
2303 list_add(&mapping->list, &bo_va->invalids);
2304 amdgpu_vm_it_insert(mapping, &vm->va);
2305
2306 if (mapping->flags & AMDGPU_PTE_PRT)
2307 amdgpu_vm_prt_get(adev);
2308
2309 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
2310 !bo_va->base.moved) {
2311 list_move(&bo_va->base.vm_status, &vm->moved);
2312 }
2313 trace_amdgpu_vm_bo_map(bo_va, mapping);
2314}
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2334 struct amdgpu_bo_va *bo_va,
2335 uint64_t saddr, uint64_t offset,
2336 uint64_t size, uint64_t flags)
2337{
2338 struct amdgpu_bo_va_mapping *mapping, *tmp;
2339 struct amdgpu_bo *bo = bo_va->base.bo;
2340 struct amdgpu_vm *vm = bo_va->base.vm;
2341 uint64_t eaddr;
2342
2343
2344 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2345 size == 0 || size & ~PAGE_MASK)
2346 return -EINVAL;
2347
2348
2349 eaddr = saddr + size - 1;
2350 if (saddr >= eaddr ||
2351 (bo && offset + size > amdgpu_bo_size(bo)) ||
2352 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2353 return -EINVAL;
2354
2355 saddr /= AMDGPU_GPU_PAGE_SIZE;
2356 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2357
2358 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2359 if (tmp) {
2360
2361 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2362 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2363 tmp->start, tmp->last + 1);
2364 return -EINVAL;
2365 }
2366
2367 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2368 if (!mapping)
2369 return -ENOMEM;
2370
2371 mapping->start = saddr;
2372 mapping->last = eaddr;
2373 mapping->offset = offset;
2374 mapping->flags = flags;
2375
2376 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2377
2378 return 0;
2379}
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2400 struct amdgpu_bo_va *bo_va,
2401 uint64_t saddr, uint64_t offset,
2402 uint64_t size, uint64_t flags)
2403{
2404 struct amdgpu_bo_va_mapping *mapping;
2405 struct amdgpu_bo *bo = bo_va->base.bo;
2406 uint64_t eaddr;
2407 int r;
2408
2409
2410 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2411 size == 0 || size & ~PAGE_MASK)
2412 return -EINVAL;
2413
2414
2415 eaddr = saddr + size - 1;
2416 if (saddr >= eaddr ||
2417 (bo && offset + size > amdgpu_bo_size(bo)) ||
2418 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2419 return -EINVAL;
2420
2421
2422 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2423 if (!mapping)
2424 return -ENOMEM;
2425
2426 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2427 if (r) {
2428 kfree(mapping);
2429 return r;
2430 }
2431
2432 saddr /= AMDGPU_GPU_PAGE_SIZE;
2433 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2434
2435 mapping->start = saddr;
2436 mapping->last = eaddr;
2437 mapping->offset = offset;
2438 mapping->flags = flags;
2439
2440 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2441
2442 return 0;
2443}
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2460 struct amdgpu_bo_va *bo_va,
2461 uint64_t saddr)
2462{
2463 struct amdgpu_bo_va_mapping *mapping;
2464 struct amdgpu_vm *vm = bo_va->base.vm;
2465 bool valid = true;
2466
2467 saddr /= AMDGPU_GPU_PAGE_SIZE;
2468
2469 list_for_each_entry(mapping, &bo_va->valids, list) {
2470 if (mapping->start == saddr)
2471 break;
2472 }
2473
2474 if (&mapping->list == &bo_va->valids) {
2475 valid = false;
2476
2477 list_for_each_entry(mapping, &bo_va->invalids, list) {
2478 if (mapping->start == saddr)
2479 break;
2480 }
2481
2482 if (&mapping->list == &bo_va->invalids)
2483 return -ENOENT;
2484 }
2485
2486 list_del(&mapping->list);
2487 amdgpu_vm_it_remove(mapping, &vm->va);
2488 mapping->bo_va = NULL;
2489 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2490
2491 if (valid)
2492 list_add(&mapping->list, &vm->freed);
2493 else
2494 amdgpu_vm_free_mapping(adev, vm, mapping,
2495 bo_va->last_pt_update);
2496
2497 return 0;
2498}
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2514 struct amdgpu_vm *vm,
2515 uint64_t saddr, uint64_t size)
2516{
2517 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2518 LIST_HEAD(removed);
2519 uint64_t eaddr;
2520
2521 eaddr = saddr + size - 1;
2522 saddr /= AMDGPU_GPU_PAGE_SIZE;
2523 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2524
2525
2526 before = kzalloc(sizeof(*before), GFP_KERNEL);
2527 if (!before)
2528 return -ENOMEM;
2529 INIT_LIST_HEAD(&before->list);
2530
2531 after = kzalloc(sizeof(*after), GFP_KERNEL);
2532 if (!after) {
2533 kfree(before);
2534 return -ENOMEM;
2535 }
2536 INIT_LIST_HEAD(&after->list);
2537
2538
2539 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2540 while (tmp) {
2541
2542 if (tmp->start < saddr) {
2543 before->start = tmp->start;
2544 before->last = saddr - 1;
2545 before->offset = tmp->offset;
2546 before->flags = tmp->flags;
2547 before->bo_va = tmp->bo_va;
2548 list_add(&before->list, &tmp->bo_va->invalids);
2549 }
2550
2551
2552 if (tmp->last > eaddr) {
2553 after->start = eaddr + 1;
2554 after->last = tmp->last;
2555 after->offset = tmp->offset;
2556 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
2557 after->flags = tmp->flags;
2558 after->bo_va = tmp->bo_va;
2559 list_add(&after->list, &tmp->bo_va->invalids);
2560 }
2561
2562 list_del(&tmp->list);
2563 list_add(&tmp->list, &removed);
2564
2565 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2566 }
2567
2568
2569 list_for_each_entry_safe(tmp, next, &removed, list) {
2570 amdgpu_vm_it_remove(tmp, &vm->va);
2571 list_del(&tmp->list);
2572
2573 if (tmp->start < saddr)
2574 tmp->start = saddr;
2575 if (tmp->last > eaddr)
2576 tmp->last = eaddr;
2577
2578 tmp->bo_va = NULL;
2579 list_add(&tmp->list, &vm->freed);
2580 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2581 }
2582
2583
2584 if (!list_empty(&before->list)) {
2585 amdgpu_vm_it_insert(before, &vm->va);
2586 if (before->flags & AMDGPU_PTE_PRT)
2587 amdgpu_vm_prt_get(adev);
2588 } else {
2589 kfree(before);
2590 }
2591
2592
2593 if (!list_empty(&after->list)) {
2594 amdgpu_vm_it_insert(after, &vm->va);
2595 if (after->flags & AMDGPU_PTE_PRT)
2596 amdgpu_vm_prt_get(adev);
2597 } else {
2598 kfree(after);
2599 }
2600
2601 return 0;
2602}
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2617 uint64_t addr)
2618{
2619 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2620}
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2631{
2632 struct amdgpu_bo_va_mapping *mapping;
2633
2634 if (!trace_amdgpu_vm_bo_cs_enabled())
2635 return;
2636
2637 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2638 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2639 if (mapping->bo_va && mapping->bo_va->base.bo) {
2640 struct amdgpu_bo *bo;
2641
2642 bo = mapping->bo_va->base.bo;
2643 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2644 ticket)
2645 continue;
2646 }
2647
2648 trace_amdgpu_vm_bo_cs(mapping);
2649 }
2650}
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2663 struct amdgpu_bo_va *bo_va)
2664{
2665 struct amdgpu_bo_va_mapping *mapping, *next;
2666 struct amdgpu_bo *bo = bo_va->base.bo;
2667 struct amdgpu_vm *vm = bo_va->base.vm;
2668 struct amdgpu_vm_bo_base **base;
2669
2670 if (bo) {
2671 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2672 vm->bulk_moveable = false;
2673
2674 for (base = &bo_va->base.bo->vm_bo; *base;
2675 base = &(*base)->next) {
2676 if (*base != &bo_va->base)
2677 continue;
2678
2679 *base = bo_va->base.next;
2680 break;
2681 }
2682 }
2683
2684 spin_lock(&vm->invalidated_lock);
2685 list_del(&bo_va->base.vm_status);
2686 spin_unlock(&vm->invalidated_lock);
2687
2688 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2689 list_del(&mapping->list);
2690 amdgpu_vm_it_remove(mapping, &vm->va);
2691 mapping->bo_va = NULL;
2692 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2693 list_add(&mapping->list, &vm->freed);
2694 }
2695 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2696 list_del(&mapping->list);
2697 amdgpu_vm_it_remove(mapping, &vm->va);
2698 amdgpu_vm_free_mapping(adev, vm, mapping,
2699 bo_va->last_pt_update);
2700 }
2701
2702 dma_fence_put(bo_va->last_pt_update);
2703
2704 if (bo && bo_va->is_xgmi)
2705 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2706
2707 kfree(bo_va);
2708}
2709
2710
2711
2712
2713
2714
2715
2716
2717bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2718{
2719 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2720
2721
2722 if (!bo_base || !bo_base->vm)
2723 return true;
2724
2725
2726 if (!dma_resv_test_signaled(bo->tbo.base.resv, true))
2727 return false;
2728
2729
2730 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2731 return false;
2732
2733
2734 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2735 amdgpu_vm_eviction_unlock(bo_base->vm);
2736 return false;
2737 }
2738
2739 bo_base->vm->evicting = true;
2740 amdgpu_vm_eviction_unlock(bo_base->vm);
2741 return true;
2742}
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2754 struct amdgpu_bo *bo, bool evicted)
2755{
2756 struct amdgpu_vm_bo_base *bo_base;
2757
2758
2759 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
2760 bo = bo->parent;
2761
2762 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2763 struct amdgpu_vm *vm = bo_base->vm;
2764
2765 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
2766 amdgpu_vm_bo_evicted(bo_base);
2767 continue;
2768 }
2769
2770 if (bo_base->moved)
2771 continue;
2772 bo_base->moved = true;
2773
2774 if (bo->tbo.type == ttm_bo_type_kernel)
2775 amdgpu_vm_bo_relocated(bo_base);
2776 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2777 amdgpu_vm_bo_moved(bo_base);
2778 else
2779 amdgpu_vm_bo_invalidated(bo_base);
2780 }
2781}
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2792{
2793
2794 unsigned bits = ilog2(vm_size) + 18;
2795
2796
2797
2798 if (vm_size <= 8)
2799 return (bits - 9);
2800 else
2801 return ((bits + 3) / 2);
2802}
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2815 uint32_t fragment_size_default, unsigned max_level,
2816 unsigned max_bits)
2817{
2818 unsigned int max_size = 1 << (max_bits - 30);
2819 unsigned int vm_size;
2820 uint64_t tmp;
2821
2822
2823 if (amdgpu_vm_size != -1) {
2824 vm_size = amdgpu_vm_size;
2825 if (vm_size > max_size) {
2826 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2827 amdgpu_vm_size, max_size);
2828 vm_size = max_size;
2829 }
2830 } else {
2831 struct sysinfo si;
2832 unsigned int phys_ram_gb;
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849 si_meminfo(&si);
2850 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2851 (1 << 30) - 1) >> 30;
2852 vm_size = roundup_pow_of_two(
2853 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2854 }
2855
2856 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2857
2858 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2859 if (amdgpu_vm_block_size != -1)
2860 tmp >>= amdgpu_vm_block_size - 9;
2861 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2862 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2863 switch (adev->vm_manager.num_level) {
2864 case 3:
2865 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2866 break;
2867 case 2:
2868 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2869 break;
2870 case 1:
2871 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2872 break;
2873 default:
2874 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2875 }
2876
2877 if (amdgpu_vm_block_size != -1)
2878 adev->vm_manager.block_size =
2879 min((unsigned)amdgpu_vm_block_size, max_bits
2880 - AMDGPU_GPU_PAGE_SHIFT
2881 - 9 * adev->vm_manager.num_level);
2882 else if (adev->vm_manager.num_level > 1)
2883 adev->vm_manager.block_size = 9;
2884 else
2885 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2886
2887 if (amdgpu_vm_fragment_size == -1)
2888 adev->vm_manager.fragment_size = fragment_size_default;
2889 else
2890 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2891
2892 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2893 vm_size, adev->vm_manager.num_level + 1,
2894 adev->vm_manager.block_size,
2895 adev->vm_manager.fragment_size);
2896}
2897
2898
2899
2900
2901
2902
2903
2904long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2905{
2906 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv, true,
2907 true, timeout);
2908 if (timeout <= 0)
2909 return timeout;
2910
2911 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2912}
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2926{
2927 struct amdgpu_bo *root_bo;
2928 struct amdgpu_bo_vm *root;
2929 int r, i;
2930
2931 vm->va = RB_ROOT_CACHED;
2932 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2933 vm->reserved_vmid[i] = NULL;
2934 INIT_LIST_HEAD(&vm->evicted);
2935 INIT_LIST_HEAD(&vm->relocated);
2936 INIT_LIST_HEAD(&vm->moved);
2937 INIT_LIST_HEAD(&vm->idle);
2938 INIT_LIST_HEAD(&vm->invalidated);
2939 spin_lock_init(&vm->invalidated_lock);
2940 INIT_LIST_HEAD(&vm->freed);
2941 INIT_LIST_HEAD(&vm->done);
2942
2943
2944 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2945 adev->vm_manager.vm_pte_scheds,
2946 adev->vm_manager.vm_pte_num_scheds, NULL);
2947 if (r)
2948 return r;
2949
2950 r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2951 adev->vm_manager.vm_pte_scheds,
2952 adev->vm_manager.vm_pte_num_scheds, NULL);
2953 if (r)
2954 goto error_free_immediate;
2955
2956 vm->pte_support_ats = false;
2957 vm->is_compute_context = false;
2958
2959 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2960 AMDGPU_VM_USE_CPU_FOR_GFX);
2961
2962 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2963 vm->use_cpu_for_update ? "CPU" : "SDMA");
2964 WARN_ONCE((vm->use_cpu_for_update &&
2965 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2966 "CPU update of VM recommended only for large BAR system\n");
2967
2968 if (vm->use_cpu_for_update)
2969 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2970 else
2971 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2972 vm->last_update = NULL;
2973 vm->last_unlocked = dma_fence_get_stub();
2974
2975 mutex_init(&vm->eviction_lock);
2976 vm->evicting = false;
2977
2978 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2979 false, &root);
2980 if (r)
2981 goto error_free_delayed;
2982 root_bo = &root->bo;
2983 r = amdgpu_bo_reserve(root_bo, true);
2984 if (r)
2985 goto error_free_root;
2986
2987 r = dma_resv_reserve_shared(root_bo->tbo.base.resv, 1);
2988 if (r)
2989 goto error_unreserve;
2990
2991 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2992
2993 r = amdgpu_vm_clear_bo(adev, vm, root, false);
2994 if (r)
2995 goto error_unreserve;
2996
2997 amdgpu_bo_unreserve(vm->root.bo);
2998
2999 INIT_KFIFO(vm->faults);
3000
3001 return 0;
3002
3003error_unreserve:
3004 amdgpu_bo_unreserve(vm->root.bo);
3005
3006error_free_root:
3007 amdgpu_bo_unref(&root->shadow);
3008 amdgpu_bo_unref(&root_bo);
3009 vm->root.bo = NULL;
3010
3011error_free_delayed:
3012 dma_fence_put(vm->last_unlocked);
3013 drm_sched_entity_destroy(&vm->delayed);
3014
3015error_free_immediate:
3016 drm_sched_entity_destroy(&vm->immediate);
3017
3018 return r;
3019}
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
3035 struct amdgpu_vm *vm)
3036{
3037 enum amdgpu_vm_level root = adev->vm_manager.root_level;
3038 unsigned int entries = amdgpu_vm_num_entries(adev, root);
3039 unsigned int i = 0;
3040
3041 for (i = 0; i < entries; i++) {
3042 if (to_amdgpu_bo_vm(vm->root.bo)->entries[i].bo)
3043 return -EINVAL;
3044 }
3045
3046 return 0;
3047}
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3069{
3070 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
3071 int r;
3072
3073 r = amdgpu_bo_reserve(vm->root.bo, true);
3074 if (r)
3075 return r;
3076
3077
3078 r = amdgpu_vm_check_clean_reserved(adev, vm);
3079 if (r)
3080 goto unreserve_bo;
3081
3082
3083
3084
3085 if (pte_support_ats != vm->pte_support_ats) {
3086 vm->pte_support_ats = pte_support_ats;
3087 r = amdgpu_vm_clear_bo(adev, vm,
3088 to_amdgpu_bo_vm(vm->root.bo),
3089 false);
3090 if (r)
3091 goto unreserve_bo;
3092 }
3093
3094
3095 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3096 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
3097 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3098 vm->use_cpu_for_update ? "CPU" : "SDMA");
3099 WARN_ONCE((vm->use_cpu_for_update &&
3100 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3101 "CPU update of VM recommended only for large BAR system\n");
3102
3103 if (vm->use_cpu_for_update) {
3104
3105 r = amdgpu_bo_sync_wait(vm->root.bo,
3106 AMDGPU_FENCE_OWNER_UNDEFINED, true);
3107 if (r)
3108 goto unreserve_bo;
3109
3110 vm->update_funcs = &amdgpu_vm_cpu_funcs;
3111 } else {
3112 vm->update_funcs = &amdgpu_vm_sdma_funcs;
3113 }
3114 dma_fence_put(vm->last_update);
3115 vm->last_update = NULL;
3116 vm->is_compute_context = true;
3117
3118
3119 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
3120
3121 goto unreserve_bo;
3122
3123unreserve_bo:
3124 amdgpu_bo_unreserve(vm->root.bo);
3125 return r;
3126}
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3137{
3138 amdgpu_vm_set_pasid(adev, vm, 0);
3139 vm->is_compute_context = false;
3140}
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3152{
3153 struct amdgpu_bo_va_mapping *mapping, *tmp;
3154 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
3155 struct amdgpu_bo *root;
3156 int i;
3157
3158 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
3159
3160 root = amdgpu_bo_ref(vm->root.bo);
3161 amdgpu_bo_reserve(root, true);
3162 amdgpu_vm_set_pasid(adev, vm, 0);
3163 dma_fence_wait(vm->last_unlocked, false);
3164 dma_fence_put(vm->last_unlocked);
3165
3166 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3167 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3168 amdgpu_vm_prt_fini(adev, vm);
3169 prt_fini_needed = false;
3170 }
3171
3172 list_del(&mapping->list);
3173 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3174 }
3175
3176 amdgpu_vm_free_pts(adev, vm, NULL);
3177 amdgpu_bo_unreserve(root);
3178 amdgpu_bo_unref(&root);
3179 WARN_ON(vm->root.bo);
3180
3181 drm_sched_entity_destroy(&vm->immediate);
3182 drm_sched_entity_destroy(&vm->delayed);
3183
3184 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3185 dev_err(adev->dev, "still active bo inside vm\n");
3186 }
3187 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3188 &vm->va.rb_root, rb) {
3189
3190
3191
3192 list_del(&mapping->list);
3193 kfree(mapping);
3194 }
3195
3196 dma_fence_put(vm->last_update);
3197 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3198 amdgpu_vmid_free_reserved(adev, vm, i);
3199}
3200
3201
3202
3203
3204
3205
3206
3207
3208void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3209{
3210 unsigned i;
3211
3212
3213
3214
3215 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
3216 adev->asic_type == CHIP_NAVI10 ||
3217 adev->asic_type == CHIP_NAVI14);
3218 amdgpu_vmid_mgr_init(adev);
3219
3220 adev->vm_manager.fence_context =
3221 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3222 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3223 adev->vm_manager.seqno[i] = 0;
3224
3225 spin_lock_init(&adev->vm_manager.prt_lock);
3226 atomic_set(&adev->vm_manager.num_prt_users, 0);
3227
3228
3229
3230
3231#ifdef CONFIG_X86_64
3232 if (amdgpu_vm_update_mode == -1) {
3233 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3234 adev->vm_manager.vm_update_mode =
3235 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3236 else
3237 adev->vm_manager.vm_update_mode = 0;
3238 } else
3239 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3240#else
3241 adev->vm_manager.vm_update_mode = 0;
3242#endif
3243
3244 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
3245}
3246
3247
3248
3249
3250
3251
3252
3253
3254void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3255{
3256 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
3257 xa_destroy(&adev->vm_manager.pasids);
3258
3259 amdgpu_vmid_mgr_fini(adev);
3260}
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3273{
3274 union drm_amdgpu_vm *args = data;
3275 struct amdgpu_device *adev = drm_to_adev(dev);
3276 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3277 long timeout = msecs_to_jiffies(2000);
3278 int r;
3279
3280 switch (args->in.op) {
3281 case AMDGPU_VM_OP_RESERVE_VMID:
3282
3283 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
3284 AMDGPU_GFXHUB_0);
3285 if (r)
3286 return r;
3287 break;
3288 case AMDGPU_VM_OP_UNRESERVE_VMID:
3289 if (amdgpu_sriov_runtime(adev))
3290 timeout = 8 * timeout;
3291
3292
3293
3294
3295 r = amdgpu_bo_reserve(fpriv->vm.root.bo, true);
3296 if (r)
3297 return r;
3298
3299 r = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
3300 if (r < 0)
3301 return r;
3302
3303 amdgpu_bo_unreserve(fpriv->vm.root.bo);
3304 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3305 break;
3306 default:
3307 return -EINVAL;
3308 }
3309
3310 return 0;
3311}
3312
3313
3314
3315
3316
3317
3318
3319
3320void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
3321 struct amdgpu_task_info *task_info)
3322{
3323 struct amdgpu_vm *vm;
3324 unsigned long flags;
3325
3326 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
3327
3328 vm = xa_load(&adev->vm_manager.pasids, pasid);
3329 if (vm)
3330 *task_info = vm->task_info;
3331
3332 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
3333}
3334
3335
3336
3337
3338
3339
3340void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3341{
3342 if (vm->task_info.pid)
3343 return;
3344
3345 vm->task_info.pid = current->pid;
3346 get_task_comm(vm->task_info.task_name, current);
3347
3348 if (current->group_leader->mm != current->mm)
3349 return;
3350
3351 vm->task_info.tgid = current->group_leader->pid;
3352 get_task_comm(vm->task_info.process_name, current->group_leader);
3353}
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
3366 uint64_t addr, bool write_fault)
3367{
3368 bool is_compute_context = false;
3369 struct amdgpu_bo *root;
3370 unsigned long irqflags;
3371 uint64_t value, flags;
3372 struct amdgpu_vm *vm;
3373 int r;
3374
3375 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
3376 vm = xa_load(&adev->vm_manager.pasids, pasid);
3377 if (vm) {
3378 root = amdgpu_bo_ref(vm->root.bo);
3379 is_compute_context = vm->is_compute_context;
3380 } else {
3381 root = NULL;
3382 }
3383 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
3384
3385 if (!root)
3386 return false;
3387
3388 addr /= AMDGPU_GPU_PAGE_SIZE;
3389
3390 if (is_compute_context &&
3391 !svm_range_restore_pages(adev, pasid, addr, write_fault)) {
3392 amdgpu_bo_unref(&root);
3393 return true;
3394 }
3395
3396 r = amdgpu_bo_reserve(root, true);
3397 if (r)
3398 goto error_unref;
3399
3400
3401 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
3402 vm = xa_load(&adev->vm_manager.pasids, pasid);
3403 if (vm && vm->root.bo != root)
3404 vm = NULL;
3405 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
3406 if (!vm)
3407 goto error_unlock;
3408
3409 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
3410 AMDGPU_PTE_SYSTEM;
3411
3412 if (is_compute_context) {
3413
3414
3415
3416 flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
3417 AMDGPU_PTE_TF;
3418 value = 0;
3419 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
3420
3421 value = adev->dummy_page_addr;
3422 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
3423 AMDGPU_PTE_WRITEABLE;
3424
3425 } else {
3426
3427 value = 0;
3428 }
3429
3430 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
3431 if (r) {
3432 pr_debug("failed %d to reserve fence slot\n", r);
3433 goto error_unlock;
3434 }
3435
3436 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
3437 addr, flags, value, NULL, NULL, NULL,
3438 NULL);
3439 if (r)
3440 goto error_unlock;
3441
3442 r = amdgpu_vm_update_pdes(adev, vm, true);
3443
3444error_unlock:
3445 amdgpu_bo_unreserve(root);
3446 if (r < 0)
3447 DRM_ERROR("Can't handle page fault (%d)\n", r);
3448
3449error_unref:
3450 amdgpu_bo_unref(&root);
3451
3452 return false;
3453}
3454
3455#if defined(CONFIG_DEBUG_FS)
3456
3457
3458
3459
3460
3461
3462
3463
3464void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
3465{
3466 struct amdgpu_bo_va *bo_va, *tmp;
3467 u64 total_idle = 0;
3468 u64 total_evicted = 0;
3469 u64 total_relocated = 0;
3470 u64 total_moved = 0;
3471 u64 total_invalidated = 0;
3472 u64 total_done = 0;
3473 unsigned int total_idle_objs = 0;
3474 unsigned int total_evicted_objs = 0;
3475 unsigned int total_relocated_objs = 0;
3476 unsigned int total_moved_objs = 0;
3477 unsigned int total_invalidated_objs = 0;
3478 unsigned int total_done_objs = 0;
3479 unsigned int id = 0;
3480
3481 seq_puts(m, "\tIdle BOs:\n");
3482 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
3483 if (!bo_va->base.bo)
3484 continue;
3485 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3486 }
3487 total_idle_objs = id;
3488 id = 0;
3489
3490 seq_puts(m, "\tEvicted BOs:\n");
3491 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
3492 if (!bo_va->base.bo)
3493 continue;
3494 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3495 }
3496 total_evicted_objs = id;
3497 id = 0;
3498
3499 seq_puts(m, "\tRelocated BOs:\n");
3500 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
3501 if (!bo_va->base.bo)
3502 continue;
3503 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3504 }
3505 total_relocated_objs = id;
3506 id = 0;
3507
3508 seq_puts(m, "\tMoved BOs:\n");
3509 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
3510 if (!bo_va->base.bo)
3511 continue;
3512 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3513 }
3514 total_moved_objs = id;
3515 id = 0;
3516
3517 seq_puts(m, "\tInvalidated BOs:\n");
3518 spin_lock(&vm->invalidated_lock);
3519 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
3520 if (!bo_va->base.bo)
3521 continue;
3522 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3523 }
3524 total_invalidated_objs = id;
3525 id = 0;
3526
3527 seq_puts(m, "\tDone BOs:\n");
3528 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
3529 if (!bo_va->base.bo)
3530 continue;
3531 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3532 }
3533 spin_unlock(&vm->invalidated_lock);
3534 total_done_objs = id;
3535
3536 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
3537 total_idle_objs);
3538 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
3539 total_evicted_objs);
3540 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
3541 total_relocated_objs);
3542 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
3543 total_moved_objs);
3544 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
3545 total_invalidated_objs);
3546 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
3547 total_done_objs);
3548}
3549#endif
3550