LXR linux/drivers/gpu/drm/amd/amdgpu/amdgv

   1/*
   2 * Copyright 2018-2019 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#ifndef AMDGV_SRIOV_MSG__H_
  25#define AMDGV_SRIOV_MSG__H_
  26
  27/* unit in kilobytes */
  28#define AMD_SRIOV_MSG_VBIOS_OFFSET              0
  29#define AMD_SRIOV_MSG_VBIOS_SIZE_KB             64
  30#define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB    AMD_SRIOV_MSG_VBIOS_SIZE_KB
  31#define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB      4
  32
  33/*
  34 * layout
  35 * 0           64KB        65KB        66KB
  36 * |   VBIOS   |   PF2VF   |   VF2PF   |   Bad Page   | ...
  37 * |   64KB    |   1KB     |   1KB     |
  38 */
  39#define AMD_SRIOV_MSG_SIZE_KB                   1
  40#define AMD_SRIOV_MSG_PF2VF_OFFSET_KB           AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB
  41#define AMD_SRIOV_MSG_VF2PF_OFFSET_KB           (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
  42#define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB        (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
  43
  44/*
  45 * PF2VF history log:
  46 * v1 defined in amdgim
  47 * v2 current
  48 *
  49 * VF2PF history log:
  50 * v1 defined in amdgim
  51 * v2 defined in amdgim
  52 * v3 current
  53 */
  54#define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER                 2
  55#define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER                 3
  56
  57#define AMD_SRIOV_MSG_RESERVE_UCODE             24
  58
  59#define AMD_SRIOV_MSG_RESERVE_VCN_INST 4
  60
  61enum amd_sriov_ucode_engine_id {
  62        AMD_SRIOV_UCODE_ID_VCE = 0,
  63        AMD_SRIOV_UCODE_ID_UVD,
  64        AMD_SRIOV_UCODE_ID_MC,
  65        AMD_SRIOV_UCODE_ID_ME,
  66        AMD_SRIOV_UCODE_ID_PFP,
  67        AMD_SRIOV_UCODE_ID_CE,
  68        AMD_SRIOV_UCODE_ID_RLC,
  69        AMD_SRIOV_UCODE_ID_RLC_SRLC,
  70        AMD_SRIOV_UCODE_ID_RLC_SRLG,
  71        AMD_SRIOV_UCODE_ID_RLC_SRLS,
  72        AMD_SRIOV_UCODE_ID_MEC,
  73        AMD_SRIOV_UCODE_ID_MEC2,
  74        AMD_SRIOV_UCODE_ID_SOS,
  75        AMD_SRIOV_UCODE_ID_ASD,
  76        AMD_SRIOV_UCODE_ID_TA_RAS,
  77        AMD_SRIOV_UCODE_ID_TA_XGMI,
  78        AMD_SRIOV_UCODE_ID_SMC,
  79        AMD_SRIOV_UCODE_ID_SDMA,
  80        AMD_SRIOV_UCODE_ID_SDMA2,
  81        AMD_SRIOV_UCODE_ID_VCN,
  82        AMD_SRIOV_UCODE_ID_DMCU,
  83        AMD_SRIOV_UCODE_ID__MAX
  84};
  85
  86#pragma pack(push, 1)   // PF2VF / VF2PF data areas are byte packed
  87
  88union amd_sriov_msg_feature_flags {
  89        struct {
  90                uint32_t  error_log_collect  : 1;
  91                uint32_t  host_load_ucodes   : 1;
  92                uint32_t  host_flr_vramlost  : 1;
  93                uint32_t  mm_bw_management   : 1;
  94                uint32_t  pp_one_vf_mode     : 1;
  95                uint32_t  reg_indirect_acc   : 1;
  96                uint32_t  reserved           : 26;
  97        } flags;
  98        uint32_t      all;
  99};
 100
 101union amd_sriov_reg_access_flags {
 102        struct {
 103                uint32_t vf_reg_access_ih        : 1;
 104                uint32_t vf_reg_access_mmhub : 1;
 105                uint32_t vf_reg_access_gc        : 1;
 106                uint32_t reserved                : 29;
 107        } flags;
 108        uint32_t all;
 109};
 110
 111union amd_sriov_msg_os_info {
 112        struct {
 113                uint32_t  windows            : 1;
 114                uint32_t  reserved           : 31;
 115        } info;
 116        uint32_t      all;
 117};
 118
 119struct amd_sriov_msg_uuid_info {
 120        union {
 121                struct {
 122                        uint32_t did    : 16;
 123                        uint32_t fcn    : 8;
 124                        uint32_t asic_7 : 8;
 125                };
 126                uint32_t time_low;
 127        };
 128
 129        struct {
 130                uint32_t time_mid  : 16;
 131                uint32_t time_high : 12;
 132                uint32_t version   : 4;
 133        };
 134
 135        struct {
 136                struct {
 137                        uint8_t clk_seq_hi : 6;
 138                        uint8_t variant    : 2;
 139                };
 140                union {
 141                        uint8_t clk_seq_low;
 142                        uint8_t asic_6;
 143                };
 144                uint16_t asic_4;
 145        };
 146
 147        uint32_t asic_0;
 148};
 149
 150struct amd_sriov_msg_pf2vf_info_header {
 151        /* the total structure size in byte */
 152        uint32_t size;
 153        /* version of this structure, written by the HOST */
 154        uint32_t version;
 155        /* reserved */
 156        uint32_t reserved[2];
 157};
 158
 159struct amd_sriov_msg_pf2vf_info {
 160        /* header contains size and version */
 161        struct amd_sriov_msg_pf2vf_info_header header;
 162        /* use private key from mailbox 2 to create checksum */
 163        uint32_t checksum;
 164        /* The features flags of the HOST driver supports */
 165        union amd_sriov_msg_feature_flags feature_flags;
 166        /* (max_width * max_height * fps) / (16 * 16) */
 167        uint32_t hevc_enc_max_mb_per_second;
 168        /* (max_width * max_height) / (16 * 16) */
 169        uint32_t hevc_enc_max_mb_per_frame;
 170        /* (max_width * max_height * fps) / (16 * 16) */
 171        uint32_t avc_enc_max_mb_per_second;
 172        /* (max_width * max_height) / (16 * 16) */
 173        uint32_t avc_enc_max_mb_per_frame;
 174        /* MEC FW position in BYTE from the start of VF visible frame buffer */
 175        uint64_t mecfw_offset;
 176        /* MEC FW size in BYTE */
 177        uint32_t mecfw_size;
 178        /* UVD FW position in BYTE from the start of VF visible frame buffer */
 179        uint64_t uvdfw_offset;
 180        /* UVD FW size in BYTE */
 181        uint32_t uvdfw_size;
 182        /* VCE FW position in BYTE from the start of VF visible frame buffer */
 183        uint64_t vcefw_offset;
 184        /* VCE FW size in BYTE */
 185        uint32_t vcefw_size;
 186        /* Bad pages block position in BYTE */
 187        uint32_t bp_block_offset_low;
 188        uint32_t bp_block_offset_high;
 189        /* Bad pages block size in BYTE */
 190        uint32_t bp_block_size;
 191        /* frequency for VF to update the VF2PF area in msec, 0 = manual */
 192        uint32_t vf2pf_update_interval_ms;
 193        /* identification in ROCm SMI */
 194        uint64_t uuid;
 195        uint32_t fcn_idx;
 196        /* flags to indicate which register access method VF should use */
 197        union amd_sriov_reg_access_flags reg_access_flags;
 198        /* MM BW management */
 199        struct {
 200                uint32_t decode_max_dimension_pixels;
 201                uint32_t decode_max_frame_pixels;
 202                uint32_t encode_max_dimension_pixels;
 203                uint32_t encode_max_frame_pixels;
 204        } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST];
 205        /* UUID info */
 206        struct amd_sriov_msg_uuid_info uuid_info;
 207        /* pcie atomic Ops info */
 208        uint32_t pcie_atomic_ops_enabled_flags;
 209        /* reserved */
 210        uint32_t reserved[256 - 48];
 211};
 212
 213struct amd_sriov_msg_vf2pf_info_header {
 214        /* the total structure size in byte */
 215        uint32_t size;
 216        /* version of this structure, written by the guest */
 217        uint32_t version;
 218        /* reserved */
 219        uint32_t reserved[2];
 220};
 221
 222struct amd_sriov_msg_vf2pf_info {
 223        /* header contains size and version */
 224        struct amd_sriov_msg_vf2pf_info_header header;
 225        uint32_t checksum;
 226        /* driver version */
 227        uint8_t  driver_version[64];
 228        /* driver certification, 1=WHQL, 0=None */
 229        uint32_t driver_cert;
 230        /* guest OS type and version */
 231        union amd_sriov_msg_os_info os_info;
 232        /* guest fb information in the unit of MB */
 233        uint32_t fb_usage;
 234        /* guest gfx engine usage percentage */
 235        uint32_t gfx_usage;
 236        /* guest gfx engine health percentage */
 237        uint32_t gfx_health;
 238        /* guest compute engine usage percentage */
 239        uint32_t compute_usage;
 240        /* guest compute engine health percentage */
 241        uint32_t compute_health;
 242        /* guest avc engine usage percentage. 0xffff means N/A */
 243        uint32_t avc_enc_usage;
 244        /* guest avc engine health percentage. 0xffff means N/A */
 245        uint32_t avc_enc_health;
 246        /* guest hevc engine usage percentage. 0xffff means N/A */
 247        uint32_t hevc_enc_usage;
 248        /* guest hevc engine usage percentage. 0xffff means N/A */
 249        uint32_t hevc_enc_health;
 250        /* combined encode/decode usage */
 251        uint32_t encode_usage;
 252        uint32_t decode_usage;
 253        /* Version of PF2VF that VF understands */
 254        uint32_t pf2vf_version_required;
 255        /* additional FB usage */
 256        uint32_t fb_vis_usage;
 257        uint32_t fb_vis_size;
 258        uint32_t fb_size;
 259        /* guest ucode data, each one is 1.25 Dword */
 260        struct {
 261                uint8_t  id;
 262                uint32_t version;
 263        } ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];
 264        uint64_t dummy_page_addr;
 265
 266        /* reserved */
 267        uint32_t reserved[256-70];
 268};
 269
 270/* mailbox message send from guest to host  */
 271enum amd_sriov_mailbox_request_message {
 272        MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1,
 273        MB_REQ_MSG_REL_GPU_INIT_ACCESS,
 274        MB_REQ_MSG_REQ_GPU_FINI_ACCESS,
 275        MB_REQ_MSG_REL_GPU_FINI_ACCESS,
 276        MB_REQ_MSG_REQ_GPU_RESET_ACCESS,
 277        MB_REQ_MSG_REQ_GPU_INIT_DATA,
 278
 279        MB_REQ_MSG_LOG_VF_ERROR       = 200,
 280};
 281
 282/* mailbox message send from host to guest  */
 283enum amd_sriov_mailbox_response_message {
 284        MB_RES_MSG_CLR_MSG_BUF = 0,
 285        MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
 286        MB_RES_MSG_FLR_NOTIFICATION,
 287        MB_RES_MSG_FLR_NOTIFICATION_COMPLETION,
 288        MB_RES_MSG_SUCCESS,
 289        MB_RES_MSG_FAIL,
 290        MB_RES_MSG_QUERY_ALIVE,
 291        MB_RES_MSG_GPU_INIT_DATA_READY,
 292
 293        MB_RES_MSG_TEXT_MESSAGE = 255
 294};
 295
 296/* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */
 297enum amd_sriov_gpu_init_data_version {
 298        GPU_INIT_DATA_READY_V1 = 1,
 299};
 300
 301#pragma pack(pop)       // Restore previous packing option
 302
 303/* checksum function between host and guest */
 304unsigned int amd_sriov_msg_checksum(void *obj,
 305                                unsigned long obj_size,
 306                                unsigned int key,
 307                                unsigned int checksum);
 308
 309/* assertion at compile time */
 310#ifdef __linux__
 311#define stringification(s) _stringification(s)
 312#define _stringification(s) #s
 313
 314_Static_assert(
 315        sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
 316        "amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
 317
 318_Static_assert(
 319        sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
 320        "amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
 321
 322_Static_assert(
 323        AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0,
 324        "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4");
 325
 326_Static_assert(
 327        AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX,
 328        "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX");
 329
 330#undef _stringification
 331#undef stringification
 332#endif
 333
 334#endif /* AMDGV_SRIOV_MSG__H_ */
 335