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24#include <linux/printk.h>
25#include <linux/slab.h>
26#include <linux/mm_types.h>
27
28#include "kfd_priv.h"
29#include "kfd_mqd_manager.h"
30#include "vi_structs.h"
31#include "gca/gfx_8_0_sh_mask.h"
32#include "gca/gfx_8_0_enum.h"
33#include "oss/oss_3_0_sh_mask.h"
34
35#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
36
37static inline struct vi_mqd *get_mqd(void *mqd)
38{
39 return (struct vi_mqd *)mqd;
40}
41
42static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
43{
44 return (struct vi_sdma_mqd *)mqd;
45}
46
47static void update_cu_mask(struct mqd_manager *mm, void *mqd,
48 struct mqd_update_info *minfo)
49{
50 struct vi_mqd *m;
51 uint32_t se_mask[4] = {0};
52
53 if (!minfo || (minfo->update_flag != UPDATE_FLAG_CU_MASK) ||
54 !minfo->cu_mask.ptr)
55 return;
56
57 mqd_symmetrically_map_cu_mask(mm,
58 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask);
59
60 m = get_mqd(mqd);
61 m->compute_static_thread_mgmt_se0 = se_mask[0];
62 m->compute_static_thread_mgmt_se1 = se_mask[1];
63 m->compute_static_thread_mgmt_se2 = se_mask[2];
64 m->compute_static_thread_mgmt_se3 = se_mask[3];
65
66 pr_debug("Update cu mask to %#x %#x %#x %#x\n",
67 m->compute_static_thread_mgmt_se0,
68 m->compute_static_thread_mgmt_se1,
69 m->compute_static_thread_mgmt_se2,
70 m->compute_static_thread_mgmt_se3);
71}
72
73static void set_priority(struct vi_mqd *m, struct queue_properties *q)
74{
75 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
76 m->cp_hqd_queue_priority = q->priority;
77}
78
79static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
80 struct queue_properties *q)
81{
82 struct kfd_mem_obj *mqd_mem_obj;
83
84 if (kfd_gtt_sa_allocate(kfd, sizeof(struct vi_mqd),
85 &mqd_mem_obj))
86 return NULL;
87
88 return mqd_mem_obj;
89}
90
91static void init_mqd(struct mqd_manager *mm, void **mqd,
92 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
93 struct queue_properties *q)
94{
95 uint64_t addr;
96 struct vi_mqd *m;
97
98 m = (struct vi_mqd *) mqd_mem_obj->cpu_ptr;
99 addr = mqd_mem_obj->gpu_addr;
100
101 memset(m, 0, sizeof(struct vi_mqd));
102
103 m->header = 0xC0310800;
104 m->compute_pipelinestat_enable = 1;
105 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
106 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
107 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
108 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
109
110 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
111 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
112
113 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT |
114 MTYPE_UC << CP_MQD_CONTROL__MTYPE__SHIFT;
115
116 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
117 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
118
119 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
120 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
121 1 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
122
123 set_priority(m, q);
124 m->cp_hqd_eop_rptr = 1 << CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT;
125
126 if (q->format == KFD_QUEUE_FORMAT_AQL)
127 m->cp_hqd_iq_rptr = 1;
128
129 if (q->tba_addr) {
130 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8);
131 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8);
132 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8);
133 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8);
134 m->compute_pgm_rsrc2 |=
135 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT);
136 }
137
138 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) {
139 m->cp_hqd_persistent_state |=
140 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
141 m->cp_hqd_ctx_save_base_addr_lo =
142 lower_32_bits(q->ctx_save_restore_area_address);
143 m->cp_hqd_ctx_save_base_addr_hi =
144 upper_32_bits(q->ctx_save_restore_area_address);
145 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
146 m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
147 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
148 m->cp_hqd_wg_state_offset = q->ctl_stack_size;
149 }
150
151 *mqd = m;
152 if (gart_addr)
153 *gart_addr = addr;
154 mm->update_mqd(mm, m, q, NULL);
155}
156
157static int load_mqd(struct mqd_manager *mm, void *mqd,
158 uint32_t pipe_id, uint32_t queue_id,
159 struct queue_properties *p, struct mm_struct *mms)
160{
161
162 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
163 uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);
164
165 return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
166 (uint32_t __user *)p->write_ptr,
167 wptr_shift, wptr_mask, mms);
168}
169
170static void __update_mqd(struct mqd_manager *mm, void *mqd,
171 struct queue_properties *q, struct mqd_update_info *minfo,
172 unsigned int mtype, unsigned int atc_bit)
173{
174 struct vi_mqd *m;
175
176 m = get_mqd(mqd);
177
178 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
179 atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT |
180 mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
181 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
182 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
183
184 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
185 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
186
187 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
188 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
189 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
190 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
191
192 m->cp_hqd_pq_doorbell_control =
193 q->doorbell_off <<
194 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
195 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
196 m->cp_hqd_pq_doorbell_control);
197
198 m->cp_hqd_eop_control = atc_bit << CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT |
199 mtype << CP_HQD_EOP_CONTROL__MTYPE__SHIFT;
200
201 m->cp_hqd_ib_control = atc_bit << CP_HQD_IB_CONTROL__IB_ATC__SHIFT |
202 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT |
203 mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT;
204
205
206
207
208
209
210
211
212 m->cp_hqd_eop_control |= min(0xA,
213 order_base_2(q->eop_ring_buffer_size / 4) - 1);
214 m->cp_hqd_eop_base_addr_lo =
215 lower_32_bits(q->eop_ring_buffer_address >> 8);
216 m->cp_hqd_eop_base_addr_hi =
217 upper_32_bits(q->eop_ring_buffer_address >> 8);
218
219 m->cp_hqd_iq_timer = atc_bit << CP_HQD_IQ_TIMER__IQ_ATC__SHIFT |
220 mtype << CP_HQD_IQ_TIMER__MTYPE__SHIFT;
221
222 m->cp_hqd_vmid = q->vmid;
223
224 if (q->format == KFD_QUEUE_FORMAT_AQL) {
225 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
226 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT;
227 }
228
229 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address)
230 m->cp_hqd_ctx_save_control =
231 atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT |
232 mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT;
233
234 update_cu_mask(mm, mqd, minfo);
235 set_priority(m, q);
236
237 q->is_active = QUEUE_IS_ACTIVE(*q);
238}
239
240
241static void update_mqd(struct mqd_manager *mm, void *mqd,
242 struct queue_properties *q,
243 struct mqd_update_info *minfo)
244{
245 __update_mqd(mm, mqd, q, minfo, MTYPE_CC, 1);
246}
247
248static uint32_t read_doorbell_id(void *mqd)
249{
250 struct vi_mqd *m = (struct vi_mqd *)mqd;
251
252 return m->queue_doorbell_id0;
253}
254
255static void update_mqd_tonga(struct mqd_manager *mm, void *mqd,
256 struct queue_properties *q,
257 struct mqd_update_info *minfo)
258{
259 __update_mqd(mm, mqd, q, minfo, MTYPE_UC, 0);
260}
261
262static int destroy_mqd(struct mqd_manager *mm, void *mqd,
263 enum kfd_preempt_type type,
264 unsigned int timeout, uint32_t pipe_id,
265 uint32_t queue_id)
266{
267 return mm->dev->kfd2kgd->hqd_destroy
268 (mm->dev->kgd, mqd, type, timeout,
269 pipe_id, queue_id);
270}
271
272static void free_mqd(struct mqd_manager *mm, void *mqd,
273 struct kfd_mem_obj *mqd_mem_obj)
274{
275 kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
276}
277
278static bool is_occupied(struct mqd_manager *mm, void *mqd,
279 uint64_t queue_address, uint32_t pipe_id,
280 uint32_t queue_id)
281{
282 return mm->dev->kfd2kgd->hqd_is_occupied(
283 mm->dev->kgd, queue_address,
284 pipe_id, queue_id);
285}
286
287static int get_wave_state(struct mqd_manager *mm, void *mqd,
288 void __user *ctl_stack,
289 u32 *ctl_stack_used_size,
290 u32 *save_area_used_size)
291{
292 struct vi_mqd *m;
293
294 m = get_mqd(mqd);
295
296 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
297 m->cp_hqd_cntl_stack_offset;
298 *save_area_used_size = m->cp_hqd_wg_state_offset -
299 m->cp_hqd_cntl_stack_size;
300
301
302
303
304
305
306 return 0;
307}
308
309static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
310 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
311 struct queue_properties *q)
312{
313 struct vi_mqd *m;
314 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
315
316 m = get_mqd(*mqd);
317
318 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
319 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
320}
321
322static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
323 struct queue_properties *q,
324 struct mqd_update_info *minfo)
325{
326 __update_mqd(mm, mqd, q, minfo, MTYPE_UC, 0);
327}
328
329static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
330 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
331 struct queue_properties *q)
332{
333 struct vi_sdma_mqd *m;
334
335 m = (struct vi_sdma_mqd *) mqd_mem_obj->cpu_ptr;
336
337 memset(m, 0, sizeof(struct vi_sdma_mqd));
338
339 *mqd = m;
340 if (gart_addr)
341 *gart_addr = mqd_mem_obj->gpu_addr;
342
343 mm->update_mqd(mm, m, q, NULL);
344}
345
346static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
347 uint32_t pipe_id, uint32_t queue_id,
348 struct queue_properties *p, struct mm_struct *mms)
349{
350 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
351 (uint32_t __user *)p->write_ptr,
352 mms);
353}
354
355static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
356 struct queue_properties *q,
357 struct mqd_update_info *minfo)
358{
359 struct vi_sdma_mqd *m;
360
361 m = get_sdma_mqd(mqd);
362 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
363 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
364 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
365 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
366 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
367
368 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
369 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
370 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
371 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
372 m->sdmax_rlcx_doorbell =
373 q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
374
375 m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr;
376
377 m->sdma_engine_id = q->sdma_engine_id;
378 m->sdma_queue_id = q->sdma_queue_id;
379
380 q->is_active = QUEUE_IS_ACTIVE(*q);
381}
382
383
384
385
386
387static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
388 enum kfd_preempt_type type,
389 unsigned int timeout, uint32_t pipe_id,
390 uint32_t queue_id)
391{
392 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
393}
394
395static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
396 uint64_t queue_address, uint32_t pipe_id,
397 uint32_t queue_id)
398{
399 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
400}
401
402#if defined(CONFIG_DEBUG_FS)
403
404static int debugfs_show_mqd(struct seq_file *m, void *data)
405{
406 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
407 data, sizeof(struct vi_mqd), false);
408 return 0;
409}
410
411static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
412{
413 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
414 data, sizeof(struct vi_sdma_mqd), false);
415 return 0;
416}
417
418#endif
419
420struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
421 struct kfd_dev *dev)
422{
423 struct mqd_manager *mqd;
424
425 if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
426 return NULL;
427
428 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
429 if (!mqd)
430 return NULL;
431
432 mqd->dev = dev;
433
434 switch (type) {
435 case KFD_MQD_TYPE_CP:
436 mqd->allocate_mqd = allocate_mqd;
437 mqd->init_mqd = init_mqd;
438 mqd->free_mqd = free_mqd;
439 mqd->load_mqd = load_mqd;
440 mqd->update_mqd = update_mqd;
441 mqd->destroy_mqd = destroy_mqd;
442 mqd->is_occupied = is_occupied;
443 mqd->get_wave_state = get_wave_state;
444 mqd->mqd_size = sizeof(struct vi_mqd);
445#if defined(CONFIG_DEBUG_FS)
446 mqd->debugfs_show_mqd = debugfs_show_mqd;
447#endif
448 break;
449 case KFD_MQD_TYPE_HIQ:
450 mqd->allocate_mqd = allocate_hiq_mqd;
451 mqd->init_mqd = init_mqd_hiq;
452 mqd->free_mqd = free_mqd_hiq_sdma;
453 mqd->load_mqd = load_mqd;
454 mqd->update_mqd = update_mqd_hiq;
455 mqd->destroy_mqd = destroy_mqd;
456 mqd->is_occupied = is_occupied;
457 mqd->mqd_size = sizeof(struct vi_mqd);
458#if defined(CONFIG_DEBUG_FS)
459 mqd->debugfs_show_mqd = debugfs_show_mqd;
460#endif
461 mqd->read_doorbell_id = read_doorbell_id;
462 break;
463 case KFD_MQD_TYPE_DIQ:
464 mqd->allocate_mqd = allocate_mqd;
465 mqd->init_mqd = init_mqd_hiq;
466 mqd->free_mqd = free_mqd;
467 mqd->load_mqd = load_mqd;
468 mqd->update_mqd = update_mqd_hiq;
469 mqd->destroy_mqd = destroy_mqd;
470 mqd->is_occupied = is_occupied;
471 mqd->mqd_size = sizeof(struct vi_mqd);
472#if defined(CONFIG_DEBUG_FS)
473 mqd->debugfs_show_mqd = debugfs_show_mqd;
474#endif
475 break;
476 case KFD_MQD_TYPE_SDMA:
477 mqd->allocate_mqd = allocate_sdma_mqd;
478 mqd->init_mqd = init_mqd_sdma;
479 mqd->free_mqd = free_mqd_hiq_sdma;
480 mqd->load_mqd = load_mqd_sdma;
481 mqd->update_mqd = update_mqd_sdma;
482 mqd->destroy_mqd = destroy_mqd_sdma;
483 mqd->is_occupied = is_occupied_sdma;
484 mqd->mqd_size = sizeof(struct vi_sdma_mqd);
485#if defined(CONFIG_DEBUG_FS)
486 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
487#endif
488 break;
489 default:
490 kfree(mqd);
491 return NULL;
492 }
493
494 return mqd;
495}
496
497struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,
498 struct kfd_dev *dev)
499{
500 struct mqd_manager *mqd;
501
502 mqd = mqd_manager_init_vi(type, dev);
503 if (!mqd)
504 return NULL;
505 if (type == KFD_MQD_TYPE_CP)
506 mqd->update_mqd = update_mqd_tonga;
507 return mqd;
508}
509
