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26#include "reg_helper.h"
27#include "core_types.h"
28#include "dccg.h"
29#include "clk_mgr_internal.h"
30#include "dcn201_clk_mgr.h"
31#include "dcn20/dcn20_clk_mgr.h"
32#include "dce100/dce_clk_mgr.h"
33#include "dm_helpers.h"
34#include "dm_services.h"
35
36#include "cyan_skillfish_ip_offset.h"
37#include "dcn/dcn_2_0_3_offset.h"
38#include "dcn/dcn_2_0_3_sh_mask.h"
39#include "clk/clk_11_0_1_offset.h"
40#include "clk/clk_11_0_1_sh_mask.h"
41
42#define REG(reg) \
43 (clk_mgr->regs->reg)
44
45#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
46
47#define BASE(seg) BASE_INNER(seg)
48
49#define SR(reg_name)\
50 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
51 mm ## reg_name
52
53#define CLK_BASE_INNER(seg) \
54 CLK_BASE__INST0_SEG ## seg
55
56#undef FN
57#define FN(reg_name, field_name) \
58 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
59
60#define CTX \
61 clk_mgr->base.ctx
62#define DC_LOGGER \
63 clk_mgr->base.ctx->logger
64
65static const struct clk_mgr_registers clk_mgr_regs = {
66 CLK_COMMON_REG_LIST_DCN_201()
67};
68
69static const struct clk_mgr_shift clk_mgr_shift = {
70 CLK_COMMON_MASK_SH_LIST_DCN201_BASE(__SHIFT)
71};
72
73static const struct clk_mgr_mask clk_mgr_mask = {
74 CLK_COMMON_MASK_SH_LIST_DCN201_BASE(_MASK)
75};
76
77void dcn201_update_clocks_vbios(struct clk_mgr *clk_mgr,
78 struct dc_state *context,
79 bool safe_to_lower)
80{
81 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
82
83 bool update_dppclk = false;
84 bool update_dispclk = false;
85
86 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
87 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
88 update_dppclk = true;
89 }
90
91 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
92 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
93 update_dispclk = true;
94 }
95
96 if (update_dppclk || update_dispclk) {
97 struct bp_set_dce_clock_parameters dce_clk_params;
98 struct dc_bios *bp = clk_mgr->ctx->dc_bios;
99
100 if (update_dispclk) {
101 memset(&dce_clk_params, 0, sizeof(dce_clk_params));
102 dce_clk_params.target_clock_frequency = new_clocks->dispclk_khz;
103 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
104 dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
105 bp->funcs->set_dce_clock(bp, &dce_clk_params);
106 }
107
108
109
110 }
111}
112
113static void dcn201_init_clocks(struct clk_mgr *clk_mgr)
114{
115 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
116 clk_mgr->clks.p_state_change_support = true;
117 clk_mgr->clks.prev_p_state_change_support = true;
118 clk_mgr->clks.max_supported_dppclk_khz = 1200000;
119 clk_mgr->clks.max_supported_dispclk_khz = 1200000;
120}
121
122static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base,
123 struct dc_state *context,
124 bool safe_to_lower)
125{
126 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
127 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
128 struct dc *dc = clk_mgr_base->ctx->dc;
129 int display_count;
130 bool update_dppclk = false;
131 bool update_dispclk = false;
132 bool enter_display_off = false;
133 bool dpp_clock_lowered = false;
134 bool force_reset = false;
135 bool p_state_change_support;
136 int total_plane_count;
137
138 if (dc->work_arounds.skip_clock_update)
139 return;
140
141 if (clk_mgr_base->clks.dispclk_khz == 0 ||
142 dc->debug.force_clock_mode & 0x1) {
143 force_reset = true;
144
145 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
146 }
147
148 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
149
150 if (display_count == 0)
151 enter_display_off = true;
152
153 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz))
154 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
155
156 if (dc->debug.force_min_dcfclk_mhz > 0)
157 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
158 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
159
160 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz))
161 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
162
163 if (should_set_clock(safe_to_lower,
164 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz))
165 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
166
167 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
168 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
169
170 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
171 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
172 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
173 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
174 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
175 }
176
177 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz))
178 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
179
180 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
181 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
182 dpp_clock_lowered = true;
183 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
184
185 update_dppclk = true;
186 }
187
188 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
189 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
190
191 update_dispclk = true;
192 }
193
194 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
195 if (dpp_clock_lowered) {
196 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
197 dcn20_update_clocks_update_dentist(clk_mgr, context);
198 } else {
199 if (update_dppclk || update_dispclk)
200 dcn20_update_clocks_update_dentist(clk_mgr, context);
201 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
202 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
203 }
204 }
205}
206
207struct clk_mgr_funcs dcn201_funcs = {
208 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
209 .update_clocks = dcn201_update_clocks,
210 .init_clocks = dcn201_init_clocks,
211 .get_clock = dcn2_get_clock,
212};
213
214void dcn201_clk_mgr_construct(struct dc_context *ctx,
215 struct clk_mgr_internal *clk_mgr,
216 struct pp_smu_funcs *pp_smu,
217 struct dccg *dccg)
218{
219 struct dc_debug_options *debug = &ctx->dc->debug;
220 struct dc_bios *bp = ctx->dc_bios;
221 clk_mgr->base.ctx = ctx;
222 clk_mgr->base.funcs = &dcn201_funcs;
223 clk_mgr->regs = &clk_mgr_regs;
224 clk_mgr->clk_mgr_shift = &clk_mgr_shift;
225 clk_mgr->clk_mgr_mask = &clk_mgr_mask;
226
227 clk_mgr->dccg = dccg;
228
229 clk_mgr->dfs_bypass_disp_clk = 0;
230
231 clk_mgr->dprefclk_ss_percentage = 0;
232 clk_mgr->dprefclk_ss_divider = 1000;
233 clk_mgr->ss_on_dprefclk = false;
234
235 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
236 dcn201_funcs.update_clocks = dcn2_update_clocks_fpga;
237 clk_mgr->base.dprefclk_khz = 600000;
238 clk_mgr->base.dentist_vco_freq_khz = 3000000;
239 } else {
240 clk_mgr->base.dprefclk_khz = REG_READ(CLK4_CLK2_CURRENT_CNT);
241 clk_mgr->base.dprefclk_khz *= 100;
242
243 if (clk_mgr->base.dprefclk_khz == 0)
244 clk_mgr->base.dprefclk_khz = 600000;
245
246 REG_GET(CLK4_CLK_PLL_REQ, FbMult_int, &clk_mgr->base.dentist_vco_freq_khz);
247 clk_mgr->base.dentist_vco_freq_khz *= 100000;
248
249 if (clk_mgr->base.dentist_vco_freq_khz == 0)
250 clk_mgr->base.dentist_vco_freq_khz = 3000000;
251 }
252
253 if (!debug->disable_dfs_bypass && bp->integrated_info)
254 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
255 clk_mgr->dfs_bypass_enabled = true;
256
257 dce_clock_read_ss_info(clk_mgr);
258}
259
