LXR linux/drivers/gpu/drm/amd/display/dc/dcn201/dcn201

   1/*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "dcn201_dccg.h"
  27
  28#include "reg_helper.h"
  29#include "core_types.h"
  30
  31#define TO_DCN_DCCG(dccg)\
  32        container_of(dccg, struct dcn_dccg, base)
  33
  34#define REG(reg) \
  35        (dccg_dcn->regs->reg)
  36
  37#undef FN
  38#define FN(reg_name, field_name) \
  39        dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
  40
  41#define CTX \
  42        dccg_dcn->base.ctx
  43
  44#define DC_LOGGER \
  45        dccg->ctx->logger
  46
  47void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
  48{
  49        /* vbios handles it */
  50}
  51
  52static const struct dccg_funcs dccg201_funcs = {
  53        .update_dpp_dto = dccg201_update_dpp_dto,
  54        .get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
  55        .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
  56        .otg_add_pixel = dccg2_otg_add_pixel,
  57        .otg_drop_pixel = dccg2_otg_drop_pixel,
  58        .dccg_init = dccg2_init
  59};
  60
  61struct dccg *dccg201_create(
  62        struct dc_context *ctx,
  63        const struct dccg_registers *regs,
  64        const struct dccg_shift *dccg_shift,
  65        const struct dccg_mask *dccg_mask)
  66{
  67        struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
  68        struct dccg *base;
  69
  70        if (dccg_dcn == NULL) {
  71                BREAK_TO_DEBUGGER();
  72                return NULL;
  73        }
  74
  75        base = &dccg_dcn->base;
  76        base->ctx = ctx;
  77        base->funcs = &dccg201_funcs;
  78
  79        dccg_dcn->regs = regs;
  80        dccg_dcn->dccg_shift = dccg_shift;
  81        dccg_dcn->dccg_mask = dccg_mask;
  82
  83        return &dccg_dcn->base;
  84}
  85