LXR linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service

   1/*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include <linux/slab.h>
  27
  28#include "dm_services.h"
  29
  30#include "include/logger_interface.h"
  31
  32#include "../dce110/irq_service_dce110.h"
  33
  34#include "dcn/dcn_2_0_0_offset.h"
  35#include "dcn/dcn_2_0_0_sh_mask.h"
  36#include "navi10_ip_offset.h"
  37
  38
  39#include "irq_service_dcn20.h"
  40
  41#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  42
  43enum dc_irq_source to_dal_irq_source_dcn20(
  44                struct irq_service *irq_service,
  45                uint32_t src_id,
  46                uint32_t ext_id)
  47{
  48        switch (src_id) {
  49        case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
  50                return DC_IRQ_SOURCE_VBLANK1;
  51        case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
  52                return DC_IRQ_SOURCE_VBLANK2;
  53        case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
  54                return DC_IRQ_SOURCE_VBLANK3;
  55        case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
  56                return DC_IRQ_SOURCE_VBLANK4;
  57        case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
  58                return DC_IRQ_SOURCE_VBLANK5;
  59        case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
  60                return DC_IRQ_SOURCE_VBLANK6;
  61        case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
  62                return DC_IRQ_SOURCE_DC1_VLINE0;
  63        case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
  64                return DC_IRQ_SOURCE_DC2_VLINE0;
  65        case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
  66                return DC_IRQ_SOURCE_DC3_VLINE0;
  67        case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
  68                return DC_IRQ_SOURCE_DC4_VLINE0;
  69        case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
  70                return DC_IRQ_SOURCE_DC5_VLINE0;
  71        case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
  72                return DC_IRQ_SOURCE_DC6_VLINE0;
  73        case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
  74                return DC_IRQ_SOURCE_PFLIP1;
  75        case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
  76                return DC_IRQ_SOURCE_PFLIP2;
  77        case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
  78                return DC_IRQ_SOURCE_PFLIP3;
  79        case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
  80                return DC_IRQ_SOURCE_PFLIP4;
  81        case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
  82                return DC_IRQ_SOURCE_PFLIP5;
  83        case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
  84                return DC_IRQ_SOURCE_PFLIP6;
  85        case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  86                return DC_IRQ_SOURCE_VUPDATE1;
  87        case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  88                return DC_IRQ_SOURCE_VUPDATE2;
  89        case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  90                return DC_IRQ_SOURCE_VUPDATE3;
  91        case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  92                return DC_IRQ_SOURCE_VUPDATE4;
  93        case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  94                return DC_IRQ_SOURCE_VUPDATE5;
  95        case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  96                return DC_IRQ_SOURCE_VUPDATE6;
  97
  98        case DCN_1_0__SRCID__DC_HPD1_INT:
  99                /* generic src_id for all HPD and HPDRX interrupts */
 100                switch (ext_id) {
 101                case DCN_1_0__CTXID__DC_HPD1_INT:
 102                        return DC_IRQ_SOURCE_HPD1;
 103                case DCN_1_0__CTXID__DC_HPD2_INT:
 104                        return DC_IRQ_SOURCE_HPD2;
 105                case DCN_1_0__CTXID__DC_HPD3_INT:
 106                        return DC_IRQ_SOURCE_HPD3;
 107                case DCN_1_0__CTXID__DC_HPD4_INT:
 108                        return DC_IRQ_SOURCE_HPD4;
 109                case DCN_1_0__CTXID__DC_HPD5_INT:
 110                        return DC_IRQ_SOURCE_HPD5;
 111                case DCN_1_0__CTXID__DC_HPD6_INT:
 112                        return DC_IRQ_SOURCE_HPD6;
 113                case DCN_1_0__CTXID__DC_HPD1_RX_INT:
 114                        return DC_IRQ_SOURCE_HPD1RX;
 115                case DCN_1_0__CTXID__DC_HPD2_RX_INT:
 116                        return DC_IRQ_SOURCE_HPD2RX;
 117                case DCN_1_0__CTXID__DC_HPD3_RX_INT:
 118                        return DC_IRQ_SOURCE_HPD3RX;
 119                case DCN_1_0__CTXID__DC_HPD4_RX_INT:
 120                        return DC_IRQ_SOURCE_HPD4RX;
 121                case DCN_1_0__CTXID__DC_HPD5_RX_INT:
 122                        return DC_IRQ_SOURCE_HPD5RX;
 123                case DCN_1_0__CTXID__DC_HPD6_RX_INT:
 124                        return DC_IRQ_SOURCE_HPD6RX;
 125                default:
 126                        return DC_IRQ_SOURCE_INVALID;
 127                }
 128                break;
 129
 130        default:
 131                return DC_IRQ_SOURCE_INVALID;
 132        }
 133}
 134
 135uint32_t dc_get_hpd_state_dcn20(struct irq_service *irq_service, enum dc_irq_source source)
 136{
 137        const struct irq_source_info *info;
 138        uint32_t addr;
 139        uint32_t value;
 140        uint32_t current_status;
 141
 142        info = find_irq_source_info(irq_service, source);
 143        if (!info)
 144                return 0;
 145
 146        addr = info->status_reg;
 147        if (!addr)
 148                return 0;
 149
 150        value = dm_read_reg(irq_service->ctx, addr);
 151        current_status =
 152                get_reg_field_value(
 153                        value,
 154                        HPD0_DC_HPD_INT_STATUS,
 155                        DC_HPD_SENSE);
 156
 157        return current_status;
 158}
 159
 160static bool hpd_ack(
 161        struct irq_service *irq_service,
 162        const struct irq_source_info *info)
 163{
 164        uint32_t addr = info->status_reg;
 165        uint32_t value = dm_read_reg(irq_service->ctx, addr);
 166        uint32_t current_status =
 167                get_reg_field_value(
 168                        value,
 169                        HPD0_DC_HPD_INT_STATUS,
 170                        DC_HPD_SENSE_DELAYED);
 171
 172        dal_irq_service_ack_generic(irq_service, info);
 173
 174        value = dm_read_reg(irq_service->ctx, info->enable_reg);
 175
 176        set_reg_field_value(
 177                value,
 178                current_status ? 0 : 1,
 179                HPD0_DC_HPD_INT_CONTROL,
 180                DC_HPD_INT_POLARITY);
 181
 182        dm_write_reg(irq_service->ctx, info->enable_reg, value);
 183
 184        return true;
 185}
 186
 187static const struct irq_source_info_funcs hpd_irq_info_funcs = {
 188        .set = NULL,
 189        .ack = hpd_ack
 190};
 191
 192static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
 193        .set = NULL,
 194        .ack = NULL
 195};
 196
 197static const struct irq_source_info_funcs pflip_irq_info_funcs = {
 198        .set = NULL,
 199        .ack = NULL
 200};
 201
 202static const struct irq_source_info_funcs vblank_irq_info_funcs = {
 203        .set = NULL,
 204        .ack = NULL
 205};
 206
 207static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
 208        .set = NULL,
 209        .ack = NULL
 210};
 211
 212static const struct irq_source_info_funcs vline0_irq_info_funcs = {
 213        .set = NULL,
 214        .ack = NULL
 215};
 216
 217#undef BASE_INNER
 218#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 219
 220/* compile time expand base address. */
 221#define BASE(seg) \
 222        BASE_INNER(seg)
 223
 224
 225#define SRI(reg_name, block, id)\
 226        BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 227                        mm ## block ## id ## _ ## reg_name
 228
 229
 230#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
 231        .enable_reg = SRI(reg1, block, reg_num),\
 232        .enable_mask = \
 233                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 234        .enable_value = {\
 235                block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 236                ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
 237        },\
 238        .ack_reg = SRI(reg2, block, reg_num),\
 239        .ack_mask = \
 240                block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
 241        .ack_value = \
 242                block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
 243
 244
 245
 246#define hpd_int_entry(reg_num)\
 247        [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
 248                IRQ_REG_ENTRY(HPD, reg_num,\
 249                        DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
 250                        DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
 251                .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 252                .funcs = &hpd_irq_info_funcs\
 253        }
 254
 255#define hpd_rx_int_entry(reg_num)\
 256        [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
 257                IRQ_REG_ENTRY(HPD, reg_num,\
 258                        DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
 259                        DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
 260                .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 261                .funcs = &hpd_rx_irq_info_funcs\
 262        }
 263#define pflip_int_entry(reg_num)\
 264        [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
 265                IRQ_REG_ENTRY(HUBPREQ, reg_num,\
 266                        DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
 267                        DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
 268                .funcs = &pflip_irq_info_funcs\
 269        }
 270
 271/* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
 272 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
 273 */
 274#define vupdate_no_lock_int_entry(reg_num)\
 275        [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
 276                IRQ_REG_ENTRY(OTG, reg_num,\
 277                        OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
 278                        OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
 279                .funcs = &vupdate_no_lock_irq_info_funcs\
 280        }
 281
 282#define vblank_int_entry(reg_num)\
 283        [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
 284                IRQ_REG_ENTRY(OTG, reg_num,\
 285                        OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
 286                        OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
 287                .funcs = &vblank_irq_info_funcs\
 288        }
 289
 290#define vline0_int_entry(reg_num)\
 291        [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
 292                IRQ_REG_ENTRY(OTG, reg_num,\
 293                        OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
 294                        OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
 295                .funcs = &vline0_irq_info_funcs\
 296        }
 297
 298#define dummy_irq_entry() \
 299        {\
 300                .funcs = &dummy_irq_info_funcs\
 301        }
 302
 303#define i2c_int_entry(reg_num) \
 304        [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
 305
 306#define dp_sink_int_entry(reg_num) \
 307        [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
 308
 309#define gpio_pad_int_entry(reg_num) \
 310        [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
 311
 312#define dc_underflow_int_entry(reg_num) \
 313        [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
 314
 315static const struct irq_source_info_funcs dummy_irq_info_funcs = {
 316        .set = dal_irq_service_dummy_set,
 317        .ack = dal_irq_service_dummy_ack
 318};
 319
 320static const struct irq_source_info
 321irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
 322        [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
 323        hpd_int_entry(0),
 324        hpd_int_entry(1),
 325        hpd_int_entry(2),
 326        hpd_int_entry(3),
 327        hpd_int_entry(4),
 328        hpd_int_entry(5),
 329        hpd_rx_int_entry(0),
 330        hpd_rx_int_entry(1),
 331        hpd_rx_int_entry(2),
 332        hpd_rx_int_entry(3),
 333        hpd_rx_int_entry(4),
 334        hpd_rx_int_entry(5),
 335        i2c_int_entry(1),
 336        i2c_int_entry(2),
 337        i2c_int_entry(3),
 338        i2c_int_entry(4),
 339        i2c_int_entry(5),
 340        i2c_int_entry(6),
 341        dp_sink_int_entry(1),
 342        dp_sink_int_entry(2),
 343        dp_sink_int_entry(3),
 344        dp_sink_int_entry(4),
 345        dp_sink_int_entry(5),
 346        dp_sink_int_entry(6),
 347        [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
 348        pflip_int_entry(0),
 349        pflip_int_entry(1),
 350        pflip_int_entry(2),
 351        pflip_int_entry(3),
 352        pflip_int_entry(4),
 353        pflip_int_entry(5),
 354        [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
 355        gpio_pad_int_entry(0),
 356        gpio_pad_int_entry(1),
 357        gpio_pad_int_entry(2),
 358        gpio_pad_int_entry(3),
 359        gpio_pad_int_entry(4),
 360        gpio_pad_int_entry(5),
 361        gpio_pad_int_entry(6),
 362        gpio_pad_int_entry(7),
 363        gpio_pad_int_entry(8),
 364        gpio_pad_int_entry(9),
 365        gpio_pad_int_entry(10),
 366        gpio_pad_int_entry(11),
 367        gpio_pad_int_entry(12),
 368        gpio_pad_int_entry(13),
 369        gpio_pad_int_entry(14),
 370        gpio_pad_int_entry(15),
 371        gpio_pad_int_entry(16),
 372        gpio_pad_int_entry(17),
 373        gpio_pad_int_entry(18),
 374        gpio_pad_int_entry(19),
 375        gpio_pad_int_entry(20),
 376        gpio_pad_int_entry(21),
 377        gpio_pad_int_entry(22),
 378        gpio_pad_int_entry(23),
 379        gpio_pad_int_entry(24),
 380        gpio_pad_int_entry(25),
 381        gpio_pad_int_entry(26),
 382        gpio_pad_int_entry(27),
 383        gpio_pad_int_entry(28),
 384        gpio_pad_int_entry(29),
 385        gpio_pad_int_entry(30),
 386        dc_underflow_int_entry(1),
 387        dc_underflow_int_entry(2),
 388        dc_underflow_int_entry(3),
 389        dc_underflow_int_entry(4),
 390        dc_underflow_int_entry(5),
 391        dc_underflow_int_entry(6),
 392        [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
 393        [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
 394        vupdate_no_lock_int_entry(0),
 395        vupdate_no_lock_int_entry(1),
 396        vupdate_no_lock_int_entry(2),
 397        vupdate_no_lock_int_entry(3),
 398        vupdate_no_lock_int_entry(4),
 399        vupdate_no_lock_int_entry(5),
 400        vblank_int_entry(0),
 401        vblank_int_entry(1),
 402        vblank_int_entry(2),
 403        vblank_int_entry(3),
 404        vblank_int_entry(4),
 405        vblank_int_entry(5),
 406        vline0_int_entry(0),
 407        vline0_int_entry(1),
 408        vline0_int_entry(2),
 409        vline0_int_entry(3),
 410        vline0_int_entry(4),
 411        vline0_int_entry(5),
 412};
 413
 414static const struct irq_service_funcs irq_service_funcs_dcn20 = {
 415                .to_dal_irq_source = to_dal_irq_source_dcn20
 416};
 417
 418static void dcn20_irq_construct(
 419        struct irq_service *irq_service,
 420        struct irq_service_init_data *init_data)
 421{
 422        dal_irq_service_construct(irq_service, init_data);
 423
 424        irq_service->info = irq_source_info_dcn20;
 425        irq_service->funcs = &irq_service_funcs_dcn20;
 426}
 427
 428struct irq_service *dal_irq_service_dcn20_create(
 429        struct irq_service_init_data *init_data)
 430{
 431        struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
 432                                                  GFP_KERNEL);
 433
 434        if (!irq_service)
 435                return NULL;
 436
 437        dcn20_irq_construct(irq_service, init_data);
 438        return irq_service;
 439}
 440