1/* 2 * 3 * Copyright (C) 2016 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23#ifndef GMC_6_0_D_H 24#define GMC_6_0_D_H 25 26#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0x00CE 27#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0x00DE 28#define ixMC_IO_DEBUG_ACMD_MISC_D0 0x00AE 29#define ixMC_IO_DEBUG_ACMD_MISC_D1 0x00BE 30#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0x00EE 31#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0x00FE 32#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x010E 33#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x011E 34#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x018E 35#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x019E 36#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x01AE 37#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x01BE 38#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x012E 39#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x013E 40#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x016E 41#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x017E 42#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0x00CD 43#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0x00DD 44#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0x00AD 45#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0x00BD 46#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x010D 47#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x011D 48#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x018D 49#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x019D 50#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x01AD 51#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x01BD 52#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x012D 53#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x013D 54#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x016D 55#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x017D 56#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0x00CC 57#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0x00DC 58#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0x00AC 59#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0x00BC 60#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x010C 61#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x011C 62#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x018C 63#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x019C 64#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x01AC 65#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x01BC 66#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x012C 67#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x013C 68#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x016C 69#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x017C 70#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0x00CB 71#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0x00DB 72#define ixMC_IO_DEBUG_CK_MISC_D0 0x00AB 73#define ixMC_IO_DEBUG_CK_MISC_D1 0x00BB 74#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x010B 75#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x011B 76#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x018B 77#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x019B 78#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x01AB 79#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x01BB 80#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x012B 81#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x013B 82#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x016B 83#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x017B 84#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0x00CF 85#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0x00DF 86#define ixMC_IO_DEBUG_CMD_MISC_D0 0x00AF 87#define ixMC_IO_DEBUG_CMD_MISC_D1 0x00BF 88#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0x00EF 89#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0x00FF 90#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x01CF 91#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x01DF 92#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x010F 93#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x011F 94#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x018F 95#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x019F 96#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x01AF 97#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x01BF 98#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x012F 99#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x013F 100#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x016F 101#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x017F 102#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x014F 103#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x015F 104#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0x00C8 105#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0x00D8 106#define ixMC_IO_DEBUG_DBI_MISC_D0 0x00A8 107#define ixMC_IO_DEBUG_DBI_MISC_D1 0x00B8 108#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0x00E8 109#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0x00F8 110#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x01C8 111#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x01D8 112#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x0108 113#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x0118 114#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x0148 115#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x0158 116#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x0188 117#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x0198 118#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x01A8 119#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x01B8 120#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x0128 121#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x0138 122#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x0168 123#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x0178 124#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x01CD 125#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x01DD 126#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x01CB 127#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x01DB 128#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x01CE 129#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x01DE 130#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x01CC 131#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x01DC 132#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x014B 133#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x015B 134#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0x00C1 135#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0x00D1 136#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0x00A1 137#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0x00B1 138#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0x00E1 139#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0x00F1 140#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x01C1 141#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x01D1 142#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x0101 143#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x0111 144#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x0141 145#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x0151 146#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x0181 147#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x0191 148#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x01A1 149#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x01B1 150#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x0121 151#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x0131 152#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x0161 153#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x0171 154#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0x00C0 155#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0x00D0 156#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0x00A0 157#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0x00B0 158#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0x00E0 159#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0x00F0 160#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x01C0 161#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x01D0 162#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x0100 163#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x0110 164#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x0140 165#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x0150 166#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x0180 167#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x0190 168#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x01A0 169#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x01B0 170#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x0120 171#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x0130 172#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x0160 173#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x0170 174#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x014C 175#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x015C 176#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0x00C3 177#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0x00D3 178#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0x00A3 179#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0x00B3 180#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0x00E3 181#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0x00F3 182#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x01C3 183#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x01D3 184#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x0103 185#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x0113 186#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x0143 187#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x0153 188#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x0183 189#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x0193 190#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x01A3 191#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x01B3 192#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x0123 193#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x0133 194#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x0163 195#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x0173 196#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0x00C2 197#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0x00D2 198#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0x00A2 199#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0x00B2 200#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0x00E2 201#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0x00F2 202#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x01C2 203#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x01D2 204#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x0102 205#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x0112 206#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x0142 207#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x0152 208#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x0182 209#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x0192 210#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x01A2 211#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x01B2 212#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x0122 213#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x0132 214#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x0162 215#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x0172 216#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x014D 217#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x015D 218#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0x00C5 219#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0x00D5 220#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0x00A5 221#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0x00B5 222#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0x00E5 223#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0x00F5 224#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x01C5 225#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x01D5 226#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x0105 227#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x0115 228#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x0145 229#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x0155 230#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x0185 231#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x0195 232#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x01A5 233#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x01B5 234#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x0125 235#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x0135 236#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x0165 237#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x0175 238#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0x00C4 239#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0x00D4 240#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0x00A4 241#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0x00B4 242#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0x00E4 243#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0x00F4 244#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x01C4 245#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x01D4 246#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x0104 247#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x0114 248#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x0144 249#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x0154 250#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x0184 251#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x0194 252#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x01A4 253#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x01B4 254#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x0124 255#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x0134 256#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x0164 257#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x0174 258#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x014E 259#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x015E 260#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0x00C7 261#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0x00D7 262#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0x00A7 263#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0x00B7 264#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0x00E7 265#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0x00F7 266#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x01C7 267#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x01D7 268#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x0107 269#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x0117 270#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x0147 271#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x0157 272#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x0187 273#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x0197 274#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x01A7 275#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x01B7 276#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x0127 277#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x0137 278#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x0167 279#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x0177 280#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0x00C6 281#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0x00D6 282#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0x00A6 283#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0x00B6 284#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0x00E6 285#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0x00F6 286#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x01C6 287#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x01D6 288#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x0106 289#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x0116 290#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x0146 291#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x0156 292#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x0186 293#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x0196 294#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x01A6 295#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x01B6 296#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x0126 297#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x0136 298#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x0166 299#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x0176 300#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0x00ED 301#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0x00FD 302#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0x00C9 303#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0x00D9 304#define ixMC_IO_DEBUG_EDC_MISC_D0 0x00A9 305#define ixMC_IO_DEBUG_EDC_MISC_D1 0x00B9 306#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0x00E9 307#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0x00F9 308#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0x00EC 309#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0x00FC 310#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x01C9 311#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x01D9 312#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0x00EB 313#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0x00FB 314#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x0109 315#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x0119 316#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x0149 317#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x0159 318#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x0189 319#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x0199 320#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x01A9 321#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x01B9 322#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x0129 323#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x0139 324#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x0169 325#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x0179 326#define ixMC_IO_DEBUG_UP_0 0x0000 327#define ixMC_IO_DEBUG_UP_100 0x0064 328#define ixMC_IO_DEBUG_UP_10 0x000A 329#define ixMC_IO_DEBUG_UP_101 0x0065 330#define ixMC_IO_DEBUG_UP_102 0x0066 331#define ixMC_IO_DEBUG_UP_103 0x0067 332#define ixMC_IO_DEBUG_UP_104 0x0068 333#define ixMC_IO_DEBUG_UP_105 0x0069 334#define ixMC_IO_DEBUG_UP_106 0x006A 335#define ixMC_IO_DEBUG_UP_107 0x006B 336#define ixMC_IO_DEBUG_UP_108 0x006C 337#define ixMC_IO_DEBUG_UP_109 0x006D 338#define ixMC_IO_DEBUG_UP_1 0x0001 339#define ixMC_IO_DEBUG_UP_110 0x006E 340#define ixMC_IO_DEBUG_UP_11 0x000B 341#define ixMC_IO_DEBUG_UP_111 0x006F 342#define ixMC_IO_DEBUG_UP_112 0x0070 343#define ixMC_IO_DEBUG_UP_113 0x0071 344#define ixMC_IO_DEBUG_UP_114 0x0072 345#define ixMC_IO_DEBUG_UP_115 0x0073 346#define ixMC_IO_DEBUG_UP_116 0x0074 347#define ixMC_IO_DEBUG_UP_117 0x0075 348#define ixMC_IO_DEBUG_UP_118 0x0076 349#define ixMC_IO_DEBUG_UP_119 0x0077 350#define ixMC_IO_DEBUG_UP_120 0x0078 351#define ixMC_IO_DEBUG_UP_12 0x000C 352#define ixMC_IO_DEBUG_UP_121 0x0079 353#define ixMC_IO_DEBUG_UP_122 0x007A 354#define ixMC_IO_DEBUG_UP_123 0x007B 355#define ixMC_IO_DEBUG_UP_124 0x007C 356#define ixMC_IO_DEBUG_UP_125 0x007D 357#define ixMC_IO_DEBUG_UP_126 0x007E 358#define ixMC_IO_DEBUG_UP_127 0x007F 359#define ixMC_IO_DEBUG_UP_128 0x0080 360#define ixMC_IO_DEBUG_UP_129 0x0081 361#define ixMC_IO_DEBUG_UP_130 0x0082 362#define ixMC_IO_DEBUG_UP_13 0x000D 363#define ixMC_IO_DEBUG_UP_131 0x0083 364#define ixMC_IO_DEBUG_UP_132 0x0084 365#define ixMC_IO_DEBUG_UP_133 0x0085 366#define ixMC_IO_DEBUG_UP_134 0x0086 367#define ixMC_IO_DEBUG_UP_135 0x0087 368#define ixMC_IO_DEBUG_UP_136 0x0088 369#define ixMC_IO_DEBUG_UP_137 0x0089 370#define ixMC_IO_DEBUG_UP_138 0x008A 371#define ixMC_IO_DEBUG_UP_139 0x008B 372#define ixMC_IO_DEBUG_UP_140 0x008C 373#define ixMC_IO_DEBUG_UP_14 0x000E 374#define ixMC_IO_DEBUG_UP_141 0x008D 375#define ixMC_IO_DEBUG_UP_142 0x008E 376#define ixMC_IO_DEBUG_UP_143 0x008F 377#define ixMC_IO_DEBUG_UP_144 0x0090 378#define ixMC_IO_DEBUG_UP_145 0x0091 379#define ixMC_IO_DEBUG_UP_146 0x0092 380#define ixMC_IO_DEBUG_UP_147 0x0093 381#define ixMC_IO_DEBUG_UP_148 0x0094 382#define ixMC_IO_DEBUG_UP_149 0x0095 383#define ixMC_IO_DEBUG_UP_150 0x0096 384#define ixMC_IO_DEBUG_UP_15 0x000F 385#define ixMC_IO_DEBUG_UP_151 0x0097 386#define ixMC_IO_DEBUG_UP_152 0x0098 387#define ixMC_IO_DEBUG_UP_153 0x0099 388#define ixMC_IO_DEBUG_UP_154 0x009A 389#define ixMC_IO_DEBUG_UP_155 0x009B 390#define ixMC_IO_DEBUG_UP_156 0x009C 391#define ixMC_IO_DEBUG_UP_157 0x009D 392#define ixMC_IO_DEBUG_UP_158 0x009E 393#define ixMC_IO_DEBUG_UP_159 0x009F 394#define ixMC_IO_DEBUG_UP_16 0x0010 395#define ixMC_IO_DEBUG_UP_17 0x0011 396#define ixMC_IO_DEBUG_UP_18 0x0012 397#define ixMC_IO_DEBUG_UP_19 0x0013 398#define ixMC_IO_DEBUG_UP_20 0x0014 399#define ixMC_IO_DEBUG_UP_2 0x0002 400#define ixMC_IO_DEBUG_UP_21 0x0015 401#define ixMC_IO_DEBUG_UP_22 0x0016 402#define ixMC_IO_DEBUG_UP_23 0x0017 403#define ixMC_IO_DEBUG_UP_24 0x0018 404#define ixMC_IO_DEBUG_UP_25 0x0019 405#define ixMC_IO_DEBUG_UP_26 0x001A 406#define ixMC_IO_DEBUG_UP_27 0x001B 407#define ixMC_IO_DEBUG_UP_28 0x001C 408#define ixMC_IO_DEBUG_UP_29 0x001D 409#define ixMC_IO_DEBUG_UP_30 0x001E 410#define ixMC_IO_DEBUG_UP_3 0x0003 411#define ixMC_IO_DEBUG_UP_31 0x001F 412#define ixMC_IO_DEBUG_UP_32 0x0020 413#define ixMC_IO_DEBUG_UP_33 0x0021 414#define ixMC_IO_DEBUG_UP_34 0x0022 415#define ixMC_IO_DEBUG_UP_35 0x0023 416#define ixMC_IO_DEBUG_UP_36 0x0024 417#define ixMC_IO_DEBUG_UP_37 0x0025 418#define ixMC_IO_DEBUG_UP_38 0x0026 419#define ixMC_IO_DEBUG_UP_39 0x0027 420#define ixMC_IO_DEBUG_UP_40 0x0028 421#define ixMC_IO_DEBUG_UP_4 0x0004 422#define ixMC_IO_DEBUG_UP_41 0x0029 423#define ixMC_IO_DEBUG_UP_42 0x002A 424#define ixMC_IO_DEBUG_UP_43 0x002B 425#define ixMC_IO_DEBUG_UP_44 0x002C 426#define ixMC_IO_DEBUG_UP_45 0x002D 427#define ixMC_IO_DEBUG_UP_46 0x002E 428#define ixMC_IO_DEBUG_UP_47 0x002F 429#define ixMC_IO_DEBUG_UP_48 0x0030 430#define ixMC_IO_DEBUG_UP_49 0x0031 431#define ixMC_IO_DEBUG_UP_50 0x0032 432#define ixMC_IO_DEBUG_UP_5 0x0005 433#define ixMC_IO_DEBUG_UP_51 0x0033 434#define ixMC_IO_DEBUG_UP_52 0x0034 435#define ixMC_IO_DEBUG_UP_53 0x0035 436#define ixMC_IO_DEBUG_UP_54 0x0036 437#define ixMC_IO_DEBUG_UP_55 0x0037 438#define ixMC_IO_DEBUG_UP_56 0x0038 439#define ixMC_IO_DEBUG_UP_57 0x0039 440#define ixMC_IO_DEBUG_UP_58 0x003A 441#define ixMC_IO_DEBUG_UP_59 0x003B 442#define ixMC_IO_DEBUG_UP_60 0x003C 443#define ixMC_IO_DEBUG_UP_6 0x0006 444#define ixMC_IO_DEBUG_UP_61 0x003D 445#define ixMC_IO_DEBUG_UP_62 0x003E 446#define ixMC_IO_DEBUG_UP_63 0x003F 447#define ixMC_IO_DEBUG_UP_64 0x0040 448#define ixMC_IO_DEBUG_UP_65 0x0041 449#define ixMC_IO_DEBUG_UP_66 0x0042 450#define ixMC_IO_DEBUG_UP_67 0x0043 451#define ixMC_IO_DEBUG_UP_68 0x0044 452#define ixMC_IO_DEBUG_UP_69 0x0045 453#define ixMC_IO_DEBUG_UP_70 0x0046 454#define ixMC_IO_DEBUG_UP_7 0x0007 455#define ixMC_IO_DEBUG_UP_71 0x0047 456#define ixMC_IO_DEBUG_UP_72 0x0048 457#define ixMC_IO_DEBUG_UP_73 0x0049 458#define ixMC_IO_DEBUG_UP_74 0x004A 459#define ixMC_IO_DEBUG_UP_75 0x004B 460#define ixMC_IO_DEBUG_UP_76 0x004C 461#define ixMC_IO_DEBUG_UP_77 0x004D 462#define ixMC_IO_DEBUG_UP_78 0x004E 463#define ixMC_IO_DEBUG_UP_79 0x004F 464#define ixMC_IO_DEBUG_UP_80 0x0050 465#define ixMC_IO_DEBUG_UP_8 0x0008 466#define ixMC_IO_DEBUG_UP_81 0x0051 467#define ixMC_IO_DEBUG_UP_82 0x0052 468#define ixMC_IO_DEBUG_UP_83 0x0053 469#define ixMC_IO_DEBUG_UP_84 0x0054 470#define ixMC_IO_DEBUG_UP_85 0x0055 471#define ixMC_IO_DEBUG_UP_86 0x0056 472#define ixMC_IO_DEBUG_UP_87 0x0057 473#define ixMC_IO_DEBUG_UP_88 0x0058 474#define ixMC_IO_DEBUG_UP_89 0x0059 475#define ixMC_IO_DEBUG_UP_90 0x005A 476#define ixMC_IO_DEBUG_UP_9 0x0009 477#define ixMC_IO_DEBUG_UP_91 0x005B 478#define ixMC_IO_DEBUG_UP_92 0x005C 479#define ixMC_IO_DEBUG_UP_93 0x005D 480#define ixMC_IO_DEBUG_UP_94 0x005E 481#define ixMC_IO_DEBUG_UP_95 0x005F 482#define ixMC_IO_DEBUG_UP_96 0x0060 483#define ixMC_IO_DEBUG_UP_97 0x0061 484#define ixMC_IO_DEBUG_UP_98 0x0062 485#define ixMC_IO_DEBUG_UP_99 0x0063 486#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x01EA 487#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x01FA 488#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x01E1 489#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x01F1 490#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x01E0 491#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x01F0 492#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x01E2 493#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x01F2 494#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x01EC 495#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x01FC 496#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x01E9 497#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x01F9 498#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x01EB 499#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x01FB 500#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x01E3 501#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x01F3 502#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x01E5 503#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x01F5 504#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x01E7 505#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x01F7 506#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x01E8 507#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x01F8 508#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x01E4 509#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x01F4 510#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x01E6 511#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x01F6 512#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0x00CA 513#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0x00DA 514#define ixMC_IO_DEBUG_WCK_MISC_D0 0x00AA 515#define ixMC_IO_DEBUG_WCK_MISC_D1 0x00BA 516#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0x00EA 517#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0x00FA 518#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x01CA 519#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x01DA 520#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x010A 521#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x011A 522#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x014A 523#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x015A 524#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x018A 525#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x019A 526#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x01AA 527#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x01BA 528#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x012A 529#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x013A 530#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x016A 531#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x017A 532#define ixMC_TSM_DEBUG_BCNT0 0x0003 533#define ixMC_TSM_DEBUG_BCNT10 0x000D 534#define ixMC_TSM_DEBUG_BCNT1 0x0004 535#define ixMC_TSM_DEBUG_BCNT2 0x0005 536#define ixMC_TSM_DEBUG_BCNT3 0x0006 537#define ixMC_TSM_DEBUG_BCNT4 0x0007 538#define ixMC_TSM_DEBUG_BCNT5 0x0008 539#define ixMC_TSM_DEBUG_BCNT6 0x0009 540#define ixMC_TSM_DEBUG_BCNT7 0x000A 541#define ixMC_TSM_DEBUG_BCNT8 0x000B 542#define ixMC_TSM_DEBUG_BCNT9 0x000C 543#define ixMC_TSM_DEBUG_BKPT 0x0013 544#define ixMC_TSM_DEBUG_FLAG 0x0001 545#define ixMC_TSM_DEBUG_GCNT 0x0000 546#define ixMC_TSM_DEBUG_MISC 0x0002 547#define ixMC_TSM_DEBUG_ST01 0x0010 548#define ixMC_TSM_DEBUG_ST23 0x0011 549#define ixMC_TSM_DEBUG_ST45 0x0012 550#define mmATC_ATS_CNTL 0x0CC9 551#define mmATC_ATS_DEBUG 0x0CCA 552#define mmATC_ATS_DEFAULT_PAGE_CNTL 0x0CD1 553#define mmATC_ATS_DEFAULT_PAGE_LOW 0x0CD0 554#define mmATC_ATS_FAULT_CNTL 0x0CCD 555#define mmATC_ATS_FAULT_DEBUG 0x0CCB 556#define mmATC_ATS_FAULT_STATUS_ADDR 0x0CCF 557#define mmATC_ATS_FAULT_STATUS_INFO 0x0CCE 558#define mmATC_ATS_STATUS 0x0CCC 559#define mmATC_L1_ADDRESS_OFFSET 0x0CDD 560#define mmATC_L1_CNTL 0x0CDC 561#define mmATC_L1RD_DEBUG_TLB 0x0CDE 562#define mmATC_L1RD_STATUS 0x0CE0 563#define mmATC_L1WR_DEBUG_TLB 0x0CDF 564#define mmATC_L1WR_STATUS 0x0CE1 565#define mmATC_L2_CNTL 0x0CD5 566#define mmATC_L2_DEBUG 0x0CD7 567#define mmATC_MISC_CG 0x0CD4 568#define mmATC_VM_APERTURE0_CNTL 0x0CC4 569#define mmATC_VM_APERTURE0_CNTL2 0x0CC6 570#define mmATC_VM_APERTURE0_HIGH_ADDR 0x0CC2 571#define mmATC_VM_APERTURE0_LOW_ADDR 0x0CC0 572#define mmATC_VM_APERTURE1_CNTL 0x0CC5 573#define mmATC_VM_APERTURE1_CNTL2 0x0CC7 574#define mmATC_VM_APERTURE1_HIGH_ADDR 0x0CC3 575#define mmATC_VM_APERTURE1_LOW_ADDR 0x0CC1 576#define mmATC_VMID0_PASID_MAPPING 0x0CE7 577#define mmATC_VMID10_PASID_MAPPING 0x0CF1 578#define mmATC_VMID11_PASID_MAPPING 0x0CF2 579#define mmATC_VMID12_PASID_MAPPING 0x0CF3 580#define mmATC_VMID13_PASID_MAPPING 0x0CF4 581#define mmATC_VMID14_PASID_MAPPING 0x0CF5 582#define mmATC_VMID15_PASID_MAPPING 0x0CF6 583#define mmATC_VMID1_PASID_MAPPING 0x0CE8 584#define mmATC_VMID2_PASID_MAPPING 0x0CE9 585#define mmATC_VMID3_PASID_MAPPING 0x0CEA 586#define mmATC_VMID4_PASID_MAPPING 0x0CEB 587#define mmATC_VMID5_PASID_MAPPING 0x0CEC 588#define mmATC_VMID6_PASID_MAPPING 0x0CED 589#define mmATC_VMID7_PASID_MAPPING 0x0CEE 590#define mmATC_VMID8_PASID_MAPPING 0x0CEF 591#define mmATC_VMID9_PASID_MAPPING 0x0CF0 592#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x0CE6 593#define mmCC_MC_MAX_CHANNEL 0x096E 594#define mmDLL_CNTL 0x0AE9 595#define mmGMCON_DEBUG 0x0D5F 596#define mmGMCON_MISC 0x0D43 597#define mmGMCON_MISC2 0x0D44 598#define mmGMCON_MISC3 0x0D51 599#define mmGMCON_PERF_MON_CNTL0 0x0D4A 600#define mmGMCON_PERF_MON_CNTL1 0x0D4B 601#define mmGMCON_PERF_MON_RSLT0 0x0D4C 602#define mmGMCON_PERF_MON_RSLT1 0x0D4D 603#define mmGMCON_PGFSM_CONFIG 0x0D4E 604#define mmGMCON_PGFSM_READ 0x0D50 605#define mmGMCON_PGFSM_WRITE 0x0D4F 606#define mmGMCON_RENG_EXECUTE 0x0D42 607#define mmGMCON_RENG_RAM_DATA 0x0D41 608#define mmGMCON_RENG_RAM_INDEX 0x0D40 609#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0D48 610#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0D49 611#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0x0D45 612#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0x0D46 613#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0x0D47 614#define mmMC_ARB_ADDR_HASH 0x09DC 615#define mmMC_ARB_AGE_RD 0x09E9 616#define mmMC_ARB_AGE_WR 0x09EA 617#define mmMC_ARB_BANKMAP 0x09D7 618#define mmMC_ARB_BURST_TIME 0x0A02 619#define mmMC_ARB_CAC_CNTL 0x09D4 620#define mmMC_ARB_CG 0x09FA 621#define mmMC_ARB_DRAM_TIMING 0x09DD 622#define mmMC_ARB_DRAM_TIMING_1 0x09FC 623#define mmMC_ARB_DRAM_TIMING2 0x09DE 624#define mmMC_ARB_DRAM_TIMING2_1 0x09FF 625#define mmMC_ARB_FED_CNTL 0x09C1 626#define mmMC_ARB_GDEC_RD_CNTL 0x09EE 627#define mmMC_ARB_GDEC_WR_CNTL 0x09EF 628#define mmMC_ARB_GECC2 0x09C9 629#define mmMC_ARB_GECC2_CLI 0x09CA 630#define mmMC_ARB_GECC2_DEBUG 0x09C4 631#define mmMC_ARB_GECC2_DEBUG2 0x09C5 632#define mmMC_ARB_GECC2_MISC 0x09C3 633#define mmMC_ARB_GECC2_STATUS 0x09C2 634#define mmMC_ARB_LAZY0_RD 0x09E5 635#define mmMC_ARB_LAZY0_WR 0x09E6 636#define mmMC_ARB_LAZY1_RD 0x09E7 637#define mmMC_ARB_LAZY1_WR 0x09E8 638#define mmMC_ARB_LM_RD 0x09F0 639#define mmMC_ARB_LM_WR 0x09F1 640#define mmMC_ARB_MINCLKS 0x09DA 641#define mmMC_ARB_MISC 0x09D6 642#define mmMC_ARB_MISC2 0x09D5 643#define mmMC_ARB_PM_CNTL 0x09ED 644#define mmMC_ARB_POP 0x09D9 645#define mmMC_ARB_RAMCFG 0x09D8 646#define mmMC_ARB_REMREQ 0x09F2 647#define mmMC_ARB_REPLAY 0x09F3 648#define mmMC_ARB_RET_CREDITS_RD 0x09F4 649#define mmMC_ARB_RET_CREDITS_WR 0x09F5 650#define mmMC_ARB_RFSH_CNTL 0x09EB 651#define mmMC_ARB_RFSH_RATE 0x09EC 652#define mmMC_ARB_RTT_CNTL0 0x09D0 653#define mmMC_ARB_RTT_CNTL1 0x09D1 654#define mmMC_ARB_RTT_CNTL2 0x09D2 655#define mmMC_ARB_RTT_DATA 0x09CF 656#define mmMC_ARB_RTT_DEBUG 0x09D3 657#define mmMC_ARB_SQM_CNTL 0x09DB 658#define mmMC_ARB_TM_CNTL_RD 0x09E3 659#define mmMC_ARB_TM_CNTL_WR 0x09E4 660#define mmMC_ARB_WCDR 0x09FB 661#define mmMC_ARB_WCDR_2 0x09CE 662#define mmMC_ARB_WTM_CNTL_RD 0x09DF 663#define mmMC_ARB_WTM_CNTL_WR 0x09E0 664#define mmMC_ARB_WTM_GRPWT_RD 0x09E1 665#define mmMC_ARB_WTM_GRPWT_WR 0x09E2 666#define mmMC_BIST_AUTO_CNTL 0x0A06 667#define mmMC_BIST_CMD_CNTL 0x0A8E 668#define mmMC_BIST_CMP_CNTL 0x0A8D 669#define mmMC_BIST_CMP_CNTL_2 0x0AB6 670#define mmMC_BIST_CNTL 0x0A05 671#define mmMC_BIST_DATA_MASK 0x0A12 672#define mmMC_BIST_DATA_WORD0 0x0A0A 673#define mmMC_BIST_DATA_WORD1 0x0A0B 674#define mmMC_BIST_DATA_WORD2 0x0A0C 675#define mmMC_BIST_DATA_WORD3 0x0A0D 676#define mmMC_BIST_DATA_WORD4 0x0A0E 677#define mmMC_BIST_DATA_WORD5 0x0A0F 678#define mmMC_BIST_DATA_WORD6 0x0A10 679#define mmMC_BIST_DATA_WORD7 0x0A11 680#define mmMC_BIST_DIR_CNTL 0x0A07 681#define mmMC_BIST_EADDR 0x0A09 682#define mmMC_BIST_MISMATCH_ADDR 0x0A13 683#define mmMC_BIST_RDATA_EDC 0x0A1D 684#define mmMC_BIST_RDATA_MASK 0x0A1C 685#define mmMC_BIST_RDATA_WORD0 0x0A14 686#define mmMC_BIST_RDATA_WORD1 0x0A15 687#define mmMC_BIST_RDATA_WORD2 0x0A16 688#define mmMC_BIST_RDATA_WORD3 0x0A17 689#define mmMC_BIST_RDATA_WORD4 0x0A18 690#define mmMC_BIST_RDATA_WORD5 0x0A19 691#define mmMC_BIST_RDATA_WORD6 0x0A1A 692#define mmMC_BIST_RDATA_WORD7 0x0A1B 693#define mmMC_BIST_SADDR 0x0A08 694#define mmMC_CG_CONFIG 0x096F 695#define mmMC_CG_CONFIG_MCD 0x0829 696#define mmMC_CG_DATAPORT 0x0A21 697#define mmMC_CITF_CNTL 0x0970 698#define mmMC_CITF_CREDITS_ARB_RD 0x0972 699#define mmMC_CITF_CREDITS_ARB_WR 0x0973 700#define mmMC_CITF_CREDITS_VM 0x0971 701#define mmMC_CITF_CREDITS_XBAR 0x0989 702#define mmMC_CITF_DAGB_CNTL 0x0974 703#define mmMC_CITF_DAGB_DLY 0x0977 704#define mmMC_CITF_INT_CREDITS 0x0975 705#define mmMC_CITF_INT_CREDITS_WR 0x097D 706#define mmMC_CITF_MISC_RD_CG 0x0992 707#define mmMC_CITF_MISC_VM_CG 0x0994 708#define mmMC_CITF_MISC_WR_CG 0x0993 709#define mmMC_CITF_PERF_MON_CNTL2 0x098E 710#define mmMC_CITF_PERF_MON_RSLT2 0x0991 711#define mmMC_CITF_REMREQ 0x097A 712#define mmMC_CITF_RET_MODE 0x0976 713#define mmMC_CITF_WTM_RD_CNTL 0x097F 714#define mmMC_CITF_WTM_WR_CNTL 0x0980 715#define mmMC_CITF_XTRA_ENABLE 0x096D 716#define mmMC_CONFIG 0x0800 717#define mmMC_CONFIG_MCD 0x0828 718#define mmMC_HUB_MISC_DBG 0x0831 719#define mmMC_HUB_MISC_FRAMING 0x0834 720#define mmMC_HUB_MISC_HUB_CG 0x082E 721#define mmMC_HUB_MISC_IDLE_STATUS 0x0847 722#define mmMC_HUB_MISC_OVERRIDE 0x0833 723#define mmMC_HUB_MISC_POWER 0x082D 724#define mmMC_HUB_MISC_SIP_CG 0x0830 725#define mmMC_HUB_MISC_STATUS 0x0832 726#define mmMC_HUB_MISC_VM_CG 0x082F 727#define mmMC_HUB_RDREQ_CNTL 0x083B 728#define mmMC_HUB_RDREQ_CREDITS 0x0844 729#define mmMC_HUB_RDREQ_CREDITS2 0x0845 730#define mmMC_HUB_RDREQ_DMIF 0x0863 731#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x0848 732#define mmMC_HUB_RDREQ_GBL0 0x0856 733#define mmMC_HUB_RDREQ_GBL1 0x0857 734#define mmMC_HUB_RDREQ_HDP 0x085B 735#define mmMC_HUB_RDREQ_MCDW 0x0851 736#define mmMC_HUB_RDREQ_MCDX 0x0852 737#define mmMC_HUB_RDREQ_MCDY 0x0853 738#define mmMC_HUB_RDREQ_MCDZ 0x0854 739#define mmMC_HUB_RDREQ_MCIF 0x0864 740#define mmMC_HUB_RDREQ_RLC 0x085D 741#define mmMC_HUB_RDREQ_SEM 0x085E 742#define mmMC_HUB_RDREQ_SIP 0x0855 743#define mmMC_HUB_RDREQ_SMU 0x0858 744#define mmMC_HUB_RDREQ_STATUS 0x0839 745#define mmMC_HUB_RDREQ_UMC 0x0860 746#define mmMC_HUB_RDREQ_UVD 0x0861 747#define mmMC_HUB_RDREQ_VCE 0x085F 748#define mmMC_HUB_RDREQ_VCEU 0x0866 749#define mmMC_HUB_RDREQ_VMC 0x0865 750#define mmMC_HUB_RDREQ_WTM_CNTL 0x083D 751#define mmMC_HUB_RDREQ_XDMAM 0x0882 752#define mmMC_HUB_SHARED_DAGB_DLY 0x0846 753#define mmMC_HUB_WDP_BP 0x0837 754#define mmMC_HUB_WDP_CNTL 0x0835 755#define mmMC_HUB_WDP_CREDITS 0x083F 756#define mmMC_HUB_WDP_ERR 0x0836 757#define mmMC_HUB_WDP_GBL0 0x0841 758#define mmMC_HUB_WDP_GBL1 0x0842 759#define mmMC_HUB_WDP_HDP 0x0879 760#define mmMC_HUB_WDP_IH 0x0872 761#define mmMC_HUB_WDP_MCDW 0x0867 762#define mmMC_HUB_WDP_MCDX 0x0868 763#define mmMC_HUB_WDP_MCDY 0x0869 764#define mmMC_HUB_WDP_MCDZ 0x086A 765#define mmMC_HUB_WDP_MCIF 0x086F 766#define mmMC_HUB_WDP_MGPU 0x0843 767#define mmMC_HUB_WDP_MGPU2 0x0840 768#define mmMC_HUB_WDP_RLC 0x0873 769#define mmMC_HUB_WDP_SEM 0x0874 770#define mmMC_HUB_WDP_SH0 0x086E 771#define mmMC_HUB_WDP_SH1 0x0876 772#define mmMC_HUB_WDP_SIP 0x086B 773#define mmMC_HUB_WDP_SMU 0x0875 774#define mmMC_HUB_WDP_STATUS 0x0838 775#define mmMC_HUB_WDP_UMC 0x0877 776#define mmMC_HUB_WDP_UVD 0x0878 777#define mmMC_HUB_WDP_VCE 0x0870 778#define mmMC_HUB_WDP_VCEU 0x087F 779#define mmMC_HUB_WDP_WTM_CNTL 0x083E 780#define mmMC_HUB_WDP_XDMA 0x0881 781#define mmMC_HUB_WDP_XDMAM 0x0880 782#define mmMC_HUB_WDP_XDP 0x0871 783#define mmMC_HUB_WRRET_CNTL 0x083C 784#define mmMC_HUB_WRRET_MCDW 0x087B 785#define mmMC_HUB_WRRET_MCDX 0x087C 786#define mmMC_HUB_WRRET_MCDY 0x087D 787#define mmMC_HUB_WRRET_MCDZ 0x087E 788#define mmMC_HUB_WRRET_STATUS 0x083A 789#define mmMC_IMP_CNTL 0x0A36 790#define mmMC_IMP_DEBUG 0x0A37 791#define mmMC_IMP_DQ_STATUS 0x0ABC 792#define mmMC_IMP_STATUS 0x0A38 793#define mmMC_IO_APHY_STR_CNTL_D0 0x0A97 794#define mmMC_IO_APHY_STR_CNTL_D1 0x0A98 795#define mmMC_IO_CDRCNTL1_D0 0x0ADD 796#define mmMC_IO_CDRCNTL1_D1 0x0ADE 797#define mmMC_IO_CDRCNTL2_D0 0x0AE4 798#define mmMC_IO_CDRCNTL2_D1 0x0AE5 799#define mmMC_IO_CDRCNTL_D0 0x0A55 800#define mmMC_IO_CDRCNTL_D1 0x0A56 801#define mmMC_IO_DPHY_STR_CNTL_D0 0x0A4E 802#define mmMC_IO_DPHY_STR_CNTL_D1 0x0A54 803#define mmMC_IO_PAD_CNTL 0x0A73 804#define mmMC_IO_PAD_CNTL_D0 0x0A74 805#define mmMC_IO_PAD_CNTL_D1 0x0A75 806#define mmMC_IO_RXCNTL1_DPHY0_D0 0x0ADF 807#define mmMC_IO_RXCNTL1_DPHY0_D1 0x0AE1 808#define mmMC_IO_RXCNTL1_DPHY1_D0 0x0AE0 809#define mmMC_IO_RXCNTL1_DPHY1_D1 0x0AE2 810#define mmMC_IO_RXCNTL_DPHY0_D0 0x0A4C 811#define mmMC_IO_RXCNTL_DPHY0_D1 0x0A52 812#define mmMC_IO_RXCNTL_DPHY1_D0 0x0A4D 813#define mmMC_IO_RXCNTL_DPHY1_D1 0x0A53 814#define mmMC_IO_TXCNTL_APHY_D0 0x0A4B 815#define mmMC_IO_TXCNTL_APHY_D1 0x0A51 816#define mmMC_IO_TXCNTL_DPHY0_D0 0x0A49 817#define mmMC_IO_TXCNTL_DPHY0_D1 0x0A4F 818#define mmMC_IO_TXCNTL_DPHY1_D0 0x0A4A 819#define mmMC_IO_TXCNTL_DPHY1_D1 0x0A50 820#define mmMCLK_PWRMGT_CNTL 0x0AE8 821#define mmMC_MEM_POWER_LS 0x082A 822#define mmMC_NPL_STATUS 0x0A76 823#define mmMC_PHY_TIMING_2 0x0ACE 824#define mmMC_PHY_TIMING_D0 0x0ACC 825#define mmMC_PHY_TIMING_D1 0x0ACD 826#define mmMC_PMG_AUTO_CFG 0x0A35 827#define mmMC_PMG_AUTO_CMD 0x0A34 828#define mmMC_PMG_CFG 0x0A84 829#define mmMC_PMG_CMD_EMRS 0x0A83 830#define mmMC_PMG_CMD_MRS 0x0AAB 831#define mmMC_PMG_CMD_MRS1 0x0AD1 832#define mmMC_PMG_CMD_MRS2 0x0AD7 833#define mmMC_RD_CB 0x0981 834#define mmMC_RD_DB 0x0982 835#define mmMC_RD_GRP_EXT 0x0978 836#define mmMC_RD_GRP_GFX 0x0803 837#define mmMC_RD_GRP_LCL 0x098A 838#define mmMC_RD_GRP_OTH 0x0807 839#define mmMC_RD_GRP_SYS 0x0805 840#define mmMC_RD_HUB 0x0985 841#define mmMC_RD_TC0 0x0983 842#define mmMC_RD_TC1 0x0984 843#define mmMC_RPB_ARB_CNTL 0x0951 844#define mmMC_RPB_BIF_CNTL 0x0952 845#define mmMC_RPB_CID_QUEUE_EX 0x095A 846#define mmMC_RPB_CID_QUEUE_EX_DATA 0x095B 847#define mmMC_RPB_CID_QUEUE_RD 0x0957 848#define mmMC_RPB_CID_QUEUE_WR 0x0956 849#define mmMC_RPB_CONF 0x094D 850#define mmMC_RPB_DBG1 0x094F 851#define mmMC_RPB_EFF_CNTL 0x0950 852#define mmMC_RPB_IF_CONF 0x094E 853#define mmMC_RPB_PERF_COUNTER_CNTL 0x0958 854#define mmMC_RPB_PERF_COUNTER_STATUS 0x0959 855#define mmMC_RPB_RD_SWITCH_CNTL 0x0955 856#define mmMC_RPB_WR_COMBINE_CNTL 0x0954 857#define mmMC_RPB_WR_SWITCH_CNTL 0x0953 858#define mmMC_SEQ_BIT_REMAP_B0_D0 0x0AA3 859#define mmMC_SEQ_BIT_REMAP_B0_D1 0x0AA7 860#define mmMC_SEQ_BIT_REMAP_B1_D0 0x0AA4 861#define mmMC_SEQ_BIT_REMAP_B1_D1 0x0AA8 862#define mmMC_SEQ_BIT_REMAP_B2_D0 0x0AA5 863#define mmMC_SEQ_BIT_REMAP_B2_D1 0x0AA9 864#define mmMC_SEQ_BIT_REMAP_B3_D0 0x0AA6 865#define mmMC_SEQ_BIT_REMAP_B3_D1 0x0AAA 866#define mmMC_SEQ_BYTE_REMAP_D0 0x0A93 867#define mmMC_SEQ_BYTE_REMAP_D1 0x0A94 868#define mmMC_SEQ_CAS_TIMING 0x0A29 869#define mmMC_SEQ_CAS_TIMING_LP 0x0A9C 870#define mmMC_SEQ_CG 0x0A9A 871#define mmMC_SEQ_CMD 0x0A31 872#define mmMC_SEQ_CNTL 0x0A25 873#define mmMC_SEQ_CNTL_2 0x0AD4 874#define mmMC_SEQ_DRAM 0x0A26 875#define mmMC_SEQ_DRAM_2 0x0A27 876#define mmMC_SEQ_DRAM_ERROR_INSERTION 0x0ACB 877#define mmMC_SEQ_FIFO_CTL 0x0A57 878#define mmMC_SEQ_IO_DEBUG_DATA 0x0A92 879#define mmMC_SEQ_IO_DEBUG_INDEX 0x0A91 880#define mmMC_SEQ_IO_RDBI 0x0AB4 881#define mmMC_SEQ_IO_REDC 0x0AB5 882#define mmMC_SEQ_IO_RESERVE_D0 0x0AB7 883#define mmMC_SEQ_IO_RESERVE_D1 0x0AB8 884#define mmMC_SEQ_IO_RWORD0 0x0AAC 885#define mmMC_SEQ_IO_RWORD1 0x0AAD 886#define mmMC_SEQ_IO_RWORD2 0x0AAE 887#define mmMC_SEQ_IO_RWORD3 0x0AAF 888#define mmMC_SEQ_IO_RWORD4 0x0AB0 889#define mmMC_SEQ_IO_RWORD5 0x0AB1 890#define mmMC_SEQ_IO_RWORD6 0x0AB2 891#define mmMC_SEQ_IO_RWORD7 0x0AB3 892#define mmMC_SEQ_MISC0 0x0A80 893#define mmMC_SEQ_MISC1 0x0A81 894#define mmMC_SEQ_MISC3 0x0A8B 895#define mmMC_SEQ_MISC4 0x0A8C 896#define mmMC_SEQ_MISC5 0x0A95 897#define mmMC_SEQ_MISC6 0x0A96 898#define mmMC_SEQ_MISC7 0x0A99 899#define mmMC_SEQ_MISC8 0x0A5F 900#define mmMC_SEQ_MISC9 0x0AE7 901#define mmMC_SEQ_MISC_TIMING 0x0A2A 902#define mmMC_SEQ_MISC_TIMING2 0x0A2B 903#define mmMC_SEQ_MISC_TIMING2_LP 0x0A9E 904#define mmMC_SEQ_MISC_TIMING_LP 0x0A9D 905#define mmMC_SEQ_MPLL_OVERRIDE 0x0A22 906#define mmMC_SEQ_PERF_CNTL 0x0A77 907#define mmMC_SEQ_PERF_CNTL_1 0x0AFD 908#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0x0A79 909#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0x0A7A 910#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0x0A7B 911#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0x0A7C 912#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0x0AD9 913#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0x0ADA 914#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0x0ADB 915#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0x0ADC 916#define mmMC_SEQ_PERF_SEQ_CTL 0x0A78 917#define mmMC_SEQ_PMG_CMD_EMRS_LP 0x0AA1 918#define mmMC_SEQ_PMG_CMD_MRS1_LP 0x0AD2 919#define mmMC_SEQ_PMG_CMD_MRS2_LP 0x0AD8 920#define mmMC_SEQ_PMG_CMD_MRS_LP 0x0AA2 921#define mmMC_SEQ_PMG_PG_HWCNTL 0x0AB9 922#define mmMC_SEQ_PMG_PG_SWCNTL_0 0x0ABA 923#define mmMC_SEQ_PMG_PG_SWCNTL_1 0x0ABB 924#define mmMC_SEQ_PMG_TIMING 0x0A2C 925#define mmMC_SEQ_PMG_TIMING_LP 0x0AD3 926#define mmMC_SEQ_RAS_TIMING 0x0A28 927#define mmMC_SEQ_RAS_TIMING_LP 0x0A9B 928#define mmMC_SEQ_RD_CTL_D0 0x0A2D 929#define mmMC_SEQ_RD_CTL_D0_LP 0x0AC7 930#define mmMC_SEQ_RD_CTL_D1 0x0A2E 931#define mmMC_SEQ_RD_CTL_D1_LP 0x0AC8 932#define mmMC_SEQ_RESERVE_0_S 0x0A1E 933#define mmMC_SEQ_RESERVE_1_S 0x0A1F 934#define mmMC_SEQ_RESERVE_M 0x0A82 935#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0x0A67 936#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0x0A6D 937#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0x0A68 938#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0x0A6E 939#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0x0A69 940#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0x0A6F 941#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0x0A6A 942#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0x0A70 943#define mmMC_SEQ_RXFRAMING_DBI_D0 0x0A6B 944#define mmMC_SEQ_RXFRAMING_DBI_D1 0x0A71 945#define mmMC_SEQ_RXFRAMING_EDC_D0 0x0A6C 946#define mmMC_SEQ_RXFRAMING_EDC_D1 0x0A72 947#define mmMC_SEQ_STATUS_M 0x0A7D 948#define mmMC_SEQ_STATUS_S 0x0A20 949#define mmMC_SEQ_SUP_CNTL 0x0A32 950#define mmMC_SEQ_SUP_DEC_STAT 0x0A88 951#define mmMC_SEQ_SUP_GP0_STAT 0x0A8F 952#define mmMC_SEQ_SUP_GP1_STAT 0x0A90 953#define mmMC_SEQ_SUP_GP2_STAT 0x0A85 954#define mmMC_SEQ_SUP_GP3_STAT 0x0A86 955#define mmMC_SEQ_SUP_IR_STAT 0x0A87 956#define mmMC_SEQ_SUP_PGM 0x0A33 957#define mmMC_SEQ_SUP_PGM_STAT 0x0A89 958#define mmMC_SEQ_SUP_R_PGM 0x0A8A 959#define mmMC_SEQ_TCG_CNTL 0x0ABD 960#define mmMC_SEQ_TIMER_RD 0x0ACA 961#define mmMC_SEQ_TIMER_WR 0x0AC9 962#define mmMC_SEQ_TRAIN_CAPTURE 0x0A3E 963#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0x0A3B 964#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0x0AFE 965#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0x0AFF 966#define mmMC_SEQ_TRAIN_TIMING 0x0A40 967#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0x0A3F 968#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0x0A3A 969#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0x0A3C 970#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0x0A3D 971#define mmMC_SEQ_TSM_BCNT 0x0AC2 972#define mmMC_SEQ_TSM_CTRL 0x0ABE 973#define mmMC_SEQ_TSM_DBI 0x0AC6 974#define mmMC_SEQ_TSM_DEBUG_DATA 0x0AD0 975#define mmMC_SEQ_TSM_DEBUG_INDEX 0x0ACF 976#define mmMC_SEQ_TSM_EDC 0x0AC5 977#define mmMC_SEQ_TSM_FLAG 0x0AC3 978#define mmMC_SEQ_TSM_GCNT 0x0ABF 979#define mmMC_SEQ_TSM_MISC 0x0AE6 980#define mmMC_SEQ_TSM_NCNT 0x0AC1 981#define mmMC_SEQ_TSM_OCNT 0x0AC0 982#define mmMC_SEQ_TSM_UPDATE 0x0AC4 983#define mmMC_SEQ_TSM_WCDR 0x0AE3 984#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0x0A58 985#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0x0A60 986#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0x0A59 987#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0x0A61 988#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0x0A5A 989#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0x0A62 990#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0x0A5B 991#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0x0A63 992#define mmMC_SEQ_TXFRAMING_DBI_D0 0x0A5C 993#define mmMC_SEQ_TXFRAMING_DBI_D1 0x0A64 994#define mmMC_SEQ_TXFRAMING_EDC_D0 0x0A5D 995#define mmMC_SEQ_TXFRAMING_EDC_D1 0x0A65 996#define mmMC_SEQ_TXFRAMING_FCK_D0 0x0A5E 997#define mmMC_SEQ_TXFRAMING_FCK_D1 0x0A66 998#define mmMC_SEQ_VENDOR_ID_I0 0x0A7E 999#define mmMC_SEQ_VENDOR_ID_I1 0x0A7F 1000#define mmMC_SEQ_WCDR_CTRL 0x0A39
1001#define mmMC_SEQ_WR_CTL_2 0x0AD5 1002#define mmMC_SEQ_WR_CTL_2_LP 0x0AD6 1003#define mmMC_SEQ_WR_CTL_D0 0x0A2F 1004#define mmMC_SEQ_WR_CTL_D0_LP 0x0A9F 1005#define mmMC_SEQ_WR_CTL_D1 0x0A30 1006#define mmMC_SEQ_WR_CTL_D1_LP 0x0AA0 1007#define mmMC_SHARED_BLACKOUT_CNTL 0x082B 1008#define mmMC_SHARED_CHMAP 0x0801 1009#define mmMC_SHARED_CHREMAP 0x0802 1010#define mmMC_TRAIN_EDCCDR_R_D0 0x0A41 1011#define mmMC_TRAIN_EDCCDR_R_D1 0x0A42 1012#define mmMC_TRAIN_EDC_STATUS_D0 0x0A45 1013#define mmMC_TRAIN_EDC_STATUS_D1 0x0A48 1014#define mmMC_TRAIN_PRBSERR_0_D0 0x0A43 1015#define mmMC_TRAIN_PRBSERR_0_D1 0x0A46 1016#define mmMC_TRAIN_PRBSERR_1_D0 0x0A44 1017#define mmMC_TRAIN_PRBSERR_1_D1 0x0A47 1018#define mmMC_TRAIN_PRBSERR_2_D0 0x0AFB 1019#define mmMC_TRAIN_PRBSERR_2_D1 0x0AFC 1020#define mmMC_VM_AGP_BASE 0x080C 1021#define mmMC_VM_AGP_BOT 0x080B 1022#define mmMC_VM_AGP_TOP 0x080A 1023#define mmMC_VM_DC_WRITE_CNTL 0x0810 1024#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x0815 1025#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x0811 1026#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x0816 1027#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x0812 1028#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x0817 1029#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x0813 1030#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x0818 1031#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x0814 1032#define mmMC_VM_FB_LOCATION 0x0809 1033#define mmMC_VM_FB_OFFSET 0x081A 1034#define mmMC_VM_MB_L1_TLB0_DEBUG 0x0891 1035#define mmMC_VM_MB_L1_TLB0_STATUS 0x0895 1036#define mmMC_VM_MB_L1_TLB1_STATUS 0x0896 1037#define mmMC_VM_MB_L1_TLB2_DEBUG 0x0893 1038#define mmMC_VM_MB_L1_TLB2_STATUS 0x0897 1039#define mmMC_VM_MB_L1_TLB3_DEBUG 0x08A5 1040#define mmMC_VM_MB_L1_TLB3_STATUS 0x08A6 1041#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x08A1 1042#define mmMC_VM_MD_L1_TLB0_DEBUG 0x0998 1043#define mmMC_VM_MD_L1_TLB0_STATUS 0x099B 1044#define mmMC_VM_MD_L1_TLB1_DEBUG 0x0999 1045#define mmMC_VM_MD_L1_TLB1_STATUS 0x099C 1046#define mmMC_VM_MD_L1_TLB2_DEBUG 0x099A 1047#define mmMC_VM_MD_L1_TLB2_STATUS 0x099D 1048#define mmMC_VM_MD_L1_TLB3_DEBUG 0x09A7 1049#define mmMC_VM_MD_L1_TLB3_STATUS 0x09A8 1050#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x09A4 1051#define mmMC_VM_MX_L1_TLB_CNTL 0x0819 1052#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x080F 1053#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x080E 1054#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x080D 1055#define mmMC_WR_CB 0x0986 1056#define mmMC_WR_DB 0x0987 1057#define mmMC_WR_GRP_EXT 0x0979 1058#define mmMC_WR_GRP_GFX 0x0804 1059#define mmMC_WR_GRP_LCL 0x098B 1060#define mmMC_WR_GRP_OTH 0x0808 1061#define mmMC_WR_GRP_SYS 0x0806 1062#define mmMC_WR_HUB 0x0988 1063#define mmMC_WR_TC0 0x097B 1064#define mmMC_WR_TC1 0x097C 1065#define mmMC_XBAR_ADDR_DEC 0x0C80 1066#define mmMC_XBAR_ARB 0x0C8D 1067#define mmMC_XBAR_ARB_MAX_BURST 0x0C8E 1068#define mmMC_XBAR_CHTRIREMAP 0x0C8B 1069#define mmMC_XBAR_PERF_MON_CNTL0 0x0C8F 1070#define mmMC_XBAR_PERF_MON_CNTL1 0x0C90 1071#define mmMC_XBAR_PERF_MON_CNTL2 0x0C91 1072#define mmMC_XBAR_PERF_MON_MAX_THSH 0x0C96 1073#define mmMC_XBAR_PERF_MON_RSLT0 0x0C92 1074#define mmMC_XBAR_PERF_MON_RSLT1 0x0C93 1075#define mmMC_XBAR_PERF_MON_RSLT2 0x0C94 1076#define mmMC_XBAR_PERF_MON_RSLT3 0x0C95 1077#define mmMC_XBAR_RDREQ_CREDIT 0x0C83 1078#define mmMC_XBAR_RDREQ_PRI_CREDIT 0x0C84 1079#define mmMC_XBAR_RDRET_CREDIT1 0x0C87 1080#define mmMC_XBAR_RDRET_CREDIT2 0x0C88 1081#define mmMC_XBAR_RDRET_PRI_CREDIT1 0x0C89 1082#define mmMC_XBAR_RDRET_PRI_CREDIT2 0x0C8A 1083#define mmMC_XBAR_REMOTE 0x0C81 1084#define mmMC_XBAR_SPARE0 0x0C97 1085#define mmMC_XBAR_SPARE1 0x0C98 1086#define mmMC_XBAR_TWOCHAN 0x0C8C 1087#define mmMC_XBAR_WRREQ_CREDIT 0x0C82 1088#define mmMC_XBAR_WRRET_CREDIT1 0x0C85 1089#define mmMC_XBAR_WRRET_CREDIT2 0x0C86 1090#define mmMC_XPB_CLG_CFG0 0x08E9 1091#define mmMC_XPB_CLG_CFG10 0x08F3 1092#define mmMC_XPB_CLG_CFG1 0x08EA 1093#define mmMC_XPB_CLG_CFG11 0x08F4 1094#define mmMC_XPB_CLG_CFG12 0x08F5 1095#define mmMC_XPB_CLG_CFG13 0x08F6 1096#define mmMC_XPB_CLG_CFG14 0x08F7 1097#define mmMC_XPB_CLG_CFG15 0x08F8 1098#define mmMC_XPB_CLG_CFG16 0x08F9 1099#define mmMC_XPB_CLG_CFG17 0x08FA 1100#define mmMC_XPB_CLG_CFG18 0x08FB 1101#define mmMC_XPB_CLG_CFG19 0x08FC 1102#define mmMC_XPB_CLG_CFG20 0x0928 1103#define mmMC_XPB_CLG_CFG2 0x08EB 1104#define mmMC_XPB_CLG_CFG21 0x0929 1105#define mmMC_XPB_CLG_CFG22 0x092A 1106#define mmMC_XPB_CLG_CFG23 0x092B 1107#define mmMC_XPB_CLG_CFG24 0x092C 1108#define mmMC_XPB_CLG_CFG25 0x092D 1109#define mmMC_XPB_CLG_CFG26 0x092E 1110#define mmMC_XPB_CLG_CFG27 0x092F 1111#define mmMC_XPB_CLG_CFG28 0x0930 1112#define mmMC_XPB_CLG_CFG29 0x0931 1113#define mmMC_XPB_CLG_CFG30 0x0932 1114#define mmMC_XPB_CLG_CFG3 0x08EC 1115#define mmMC_XPB_CLG_CFG31 0x0933 1116#define mmMC_XPB_CLG_CFG32 0x0936 1117#define mmMC_XPB_CLG_CFG33 0x0937 1118#define mmMC_XPB_CLG_CFG34 0x0938 1119#define mmMC_XPB_CLG_CFG35 0x0939 1120#define mmMC_XPB_CLG_CFG36 0x093A 1121#define mmMC_XPB_CLG_CFG4 0x08ED 1122#define mmMC_XPB_CLG_CFG5 0x08EE 1123#define mmMC_XPB_CLG_CFG6 0x08EF 1124#define mmMC_XPB_CLG_CFG7 0x08F0 1125#define mmMC_XPB_CLG_CFG8 0x08F1 1126#define mmMC_XPB_CLG_CFG9 0x08F2 1127#define mmMC_XPB_CLG_EXTRA 0x08FD 1128#define mmMC_XPB_CLG_EXTRA_RD 0x0935 1129#define mmMC_XPB_CLK_GAT 0x091E 1130#define mmMC_XPB_INTF_CFG 0x091F 1131#define mmMC_XPB_INTF_CFG2 0x0934 1132#define mmMC_XPB_INTF_STS 0x0920 1133#define mmMC_XPB_LB_ADDR 0x08FE 1134#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x0923 1135#define mmMC_XPB_MISC_CFG 0x0927 1136#define mmMC_XPB_P2P_BAR0 0x0904 1137#define mmMC_XPB_P2P_BAR1 0x0905 1138#define mmMC_XPB_P2P_BAR2 0x0906 1139#define mmMC_XPB_P2P_BAR3 0x0907 1140#define mmMC_XPB_P2P_BAR4 0x0908 1141#define mmMC_XPB_P2P_BAR5 0x0909 1142#define mmMC_XPB_P2P_BAR6 0x090A 1143#define mmMC_XPB_P2P_BAR7 0x090B 1144#define mmMC_XPB_P2P_BAR_CFG 0x0903 1145#define mmMC_XPB_P2P_BAR_DEBUG 0x090D 1146#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x090E 1147#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x090F 1148#define mmMC_XPB_P2P_BAR_SETUP 0x090C 1149#define mmMC_XPB_PEER_SYS_BAR0 0x0910 1150#define mmMC_XPB_PEER_SYS_BAR1 0x0911 1151#define mmMC_XPB_PEER_SYS_BAR2 0x0912 1152#define mmMC_XPB_PEER_SYS_BAR3 0x0913 1153#define mmMC_XPB_PEER_SYS_BAR4 0x0914 1154#define mmMC_XPB_PEER_SYS_BAR5 0x0915 1155#define mmMC_XPB_PEER_SYS_BAR6 0x0916 1156#define mmMC_XPB_PEER_SYS_BAR7 0x0917 1157#define mmMC_XPB_PEER_SYS_BAR8 0x0918 1158#define mmMC_XPB_PEER_SYS_BAR9 0x0919 1159#define mmMC_XPB_PERF_KNOBS 0x0924 1160#define mmMC_XPB_PIPE_STS 0x0921 1161#define mmMC_XPB_RTR_DEST_MAP0 0x08DB 1162#define mmMC_XPB_RTR_DEST_MAP1 0x08DC 1163#define mmMC_XPB_RTR_DEST_MAP2 0x08DD 1164#define mmMC_XPB_RTR_DEST_MAP3 0x08DE 1165#define mmMC_XPB_RTR_DEST_MAP4 0x08DF 1166#define mmMC_XPB_RTR_DEST_MAP5 0x08E0 1167#define mmMC_XPB_RTR_DEST_MAP6 0x08E1 1168#define mmMC_XPB_RTR_DEST_MAP7 0x08E2 1169#define mmMC_XPB_RTR_DEST_MAP8 0x08E3 1170#define mmMC_XPB_RTR_DEST_MAP9 0x08E4 1171#define mmMC_XPB_RTR_SRC_APRTR0 0x08CD 1172#define mmMC_XPB_RTR_SRC_APRTR1 0x08CE 1173#define mmMC_XPB_RTR_SRC_APRTR2 0x08CF 1174#define mmMC_XPB_RTR_SRC_APRTR3 0x08D0 1175#define mmMC_XPB_RTR_SRC_APRTR4 0x08D1 1176#define mmMC_XPB_RTR_SRC_APRTR5 0x08D2 1177#define mmMC_XPB_RTR_SRC_APRTR6 0x08D3 1178#define mmMC_XPB_RTR_SRC_APRTR7 0x08D4 1179#define mmMC_XPB_RTR_SRC_APRTR8 0x08D5 1180#define mmMC_XPB_RTR_SRC_APRTR9 0x08D6 1181#define mmMC_XPB_STICKY 0x0925 1182#define mmMC_XPB_STICKY_W1C 0x0926 1183#define mmMC_XPB_SUB_CTRL 0x0922 1184#define mmMC_XPB_UNC_THRESH_HST 0x08FF 1185#define mmMC_XPB_UNC_THRESH_SID 0x0900 1186#define mmMC_XPB_WCB_CFG 0x0902 1187#define mmMC_XPB_WCB_STS 0x0901 1188#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x091A 1189#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x091B 1190#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x091C 1191#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x091D 1192#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x08E5 1193#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x08E6 1194#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x08E7 1195#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x08E8 1196#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x08D7 1197#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x08D8 1198#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x08D9 1199#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x08DA 1200#define mmMPLL_AD_FUNC_CNTL 0x0AF0 1201#define mmMPLL_AD_STATUS 0x0AF6 1202#define mmMPLL_CNTL_MODE 0x0AEC 1203#define mmMPLL_CONTROL 0x0AF5 1204#define mmMPLL_DQ_0_0_STATUS 0x0AF7 1205#define mmMPLL_DQ_0_1_STATUS 0x0AF8 1206#define mmMPLL_DQ_1_0_STATUS 0x0AF9 1207#define mmMPLL_DQ_1_1_STATUS 0x0AFA 1208#define mmMPLL_DQ_FUNC_CNTL 0x0AF1 1209#define mmMPLL_FUNC_CNTL 0x0AED 1210#define mmMPLL_FUNC_CNTL_1 0x0AEE 1211#define mmMPLL_FUNC_CNTL_2 0x0AEF 1212#define mmMPLL_SEQ_UCODE_1 0x0AEA 1213#define mmMPLL_SEQ_UCODE_2 0x0AEB 1214#define mmMPLL_SS1 0x0AF3 1215#define mmMPLL_SS2 0x0AF4 1216#define mmMPLL_TIME 0x0AF2 1217#define mmVM_CONTEXT0_CNTL 0x0504 1218#define mmVM_CONTEXT0_CNTL2 0x050C 1219#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x054F 1220#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x055F 1221#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x0557 1222#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x053E 1223#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x0546 1224#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x0536 1225#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x0510 1226#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x0511 1227#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x0512 1228#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x0513 1229#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x0514 1230#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x0515 1231#define mmVM_CONTEXT1_CNTL 0x0505 1232#define mmVM_CONTEXT1_CNTL2 0x050D 1233#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x0550 1234#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x0560 1235#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x0558 1236#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x053F 1237#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x0547 1238#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x0537 1239#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x0551 1240#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x0552 1241#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x0553 1242#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x0554 1243#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x0555 1244#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x0556 1245#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x050E 1246#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x050F 1247#define mmVM_CONTEXTS_DISABLE 0x0535 1248#define mmVM_DEBUG 0x056F 1249#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x0507 1250#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x0506 1251#define mmVM_FAULT_CLIENT_ID 0x054E 1252#define mmVM_INVALIDATE_REQUEST 0x051E 1253#define mmVM_INVALIDATE_RESPONSE 0x051F 1254#define mmVM_L2_BANK_SELECT_MASKA 0x0572 1255#define mmVM_L2_BANK_SELECT_MASKB 0x0573 1256#define mmVM_L2_CG 0x0570 1257#define mmVM_L2_CNTL 0x0500 1258#define mmVM_L2_CNTL2 0x0501 1259#define mmVM_L2_CNTL3 0x0502 1260#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x0576 1261#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x0575 1262#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x0577 1263#define mmVM_L2_STATUS 0x0503 1264#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x0530 1265#define mmVM_PRT_APERTURE0_LOW_ADDR 0x052C 1266#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x0531 1267#define mmVM_PRT_APERTURE1_LOW_ADDR 0x052D 1268#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x0532 1269#define mmVM_PRT_APERTURE2_LOW_ADDR 0x052E 1270#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x0533 1271#define mmVM_PRT_APERTURE3_LOW_ADDR 0x052F 1272#define mmVM_PRT_CNTL 0x0534 1273 1274#endif 1275