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10#include <linux/clk.h>
11#include <linux/component.h>
12#include <linux/iopoll.h>
13#include <linux/irq.h>
14#include <linux/mfd/syscon.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/regmap.h>
19
20#include <drm/drm_fourcc.h>
21#include <drm/drm_vblank.h>
22
23#include "exynos_drm_crtc.h"
24#include "exynos_drm_drv.h"
25#include "exynos_drm_fb.h"
26#include "exynos_drm_plane.h"
27#include "regs-decon5433.h"
28
29#define DSD_CFG_MUX 0x1004
30#define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
31
32#define WINDOWS_NR 5
33#define PRIMARY_WIN 2
34#define CURSON_WIN 4
35
36#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
37
38#define I80_HW_TRG (1 << 0)
39#define IFTYPE_HDMI (1 << 1)
40
41static const char * const decon_clks_name[] = {
42 "pclk",
43 "aclk_decon",
44 "aclk_smmu_decon0x",
45 "aclk_xiu_decon0x",
46 "pclk_smmu_decon0x",
47 "aclk_smmu_decon1x",
48 "aclk_xiu_decon1x",
49 "pclk_smmu_decon1x",
50 "sclk_decon_vclk",
51 "sclk_decon_eclk",
52};
53
54struct decon_context {
55 struct device *dev;
56 struct drm_device *drm_dev;
57 void *dma_priv;
58 struct exynos_drm_crtc *crtc;
59 struct exynos_drm_plane planes[WINDOWS_NR];
60 struct exynos_drm_plane_config configs[WINDOWS_NR];
61 void __iomem *addr;
62 struct regmap *sysreg;
63 struct clk *clks[ARRAY_SIZE(decon_clks_name)];
64 unsigned int irq;
65 unsigned int irq_vsync;
66 unsigned int irq_lcd_sys;
67 unsigned int te_irq;
68 unsigned long out_type;
69 int first_win;
70 spinlock_t vblank_lock;
71 u32 frame_id;
72};
73
74static const uint32_t decon_formats[] = {
75 DRM_FORMAT_XRGB1555,
76 DRM_FORMAT_RGB565,
77 DRM_FORMAT_XRGB8888,
78 DRM_FORMAT_ARGB8888,
79};
80
81static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
82 [PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY,
83 [CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,
84};
85
86static const unsigned int capabilities[WINDOWS_NR] = {
87 0,
88 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
89 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
90 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
91 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
92};
93
94static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
95 u32 val)
96{
97 val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
98 writel(val, ctx->addr + reg);
99}
100
101static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
102{
103 struct decon_context *ctx = crtc->ctx;
104 u32 val;
105
106 val = VIDINTCON0_INTEN;
107 if (crtc->i80_mode)
108 val |= VIDINTCON0_FRAMEDONE;
109 else
110 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
111
112 writel(val, ctx->addr + DECON_VIDINTCON0);
113
114 enable_irq(ctx->irq);
115 if (!(ctx->out_type & I80_HW_TRG))
116 enable_irq(ctx->te_irq);
117
118 return 0;
119}
120
121static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
122{
123 struct decon_context *ctx = crtc->ctx;
124
125 if (!(ctx->out_type & I80_HW_TRG))
126 disable_irq_nosync(ctx->te_irq);
127 disable_irq_nosync(ctx->irq);
128
129 writel(0, ctx->addr + DECON_VIDINTCON0);
130}
131
132
133static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
134{
135 u32 frm, pfrm, status, cnt = 2;
136
137
138
139
140
141 frm = readl(ctx->addr + DECON_CRFMID);
142 do {
143 status = readl(ctx->addr + DECON_VIDCON1);
144 pfrm = frm;
145 frm = readl(ctx->addr + DECON_CRFMID);
146 } while (frm != pfrm && --cnt);
147
148
149
150
151 if (!frm)
152 return 0;
153
154 switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
155 case VIDCON1_VSTATUS_VS:
156 if (!(ctx->crtc->i80_mode))
157 --frm;
158 break;
159 case VIDCON1_VSTATUS_BP:
160 --frm;
161 break;
162 case VIDCON1_I80_ACTIVE:
163 case VIDCON1_VSTATUS_AC:
164 if (end)
165 --frm;
166 break;
167 default:
168 break;
169 }
170
171 return frm;
172}
173
174static void decon_setup_trigger(struct decon_context *ctx)
175{
176 if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
177 return;
178
179 if (!(ctx->out_type & I80_HW_TRG)) {
180 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
181 TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
182 ctx->addr + DECON_TRIGCON);
183 return;
184 }
185
186 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
187 | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
188
189 if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
190 DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
191 DRM_DEV_ERROR(ctx->dev, "Cannot update sysreg.\n");
192}
193
194static void decon_commit(struct exynos_drm_crtc *crtc)
195{
196 struct decon_context *ctx = crtc->ctx;
197 struct drm_display_mode *m = &crtc->base.mode;
198 bool interlaced = false;
199 u32 val;
200
201 if (ctx->out_type & IFTYPE_HDMI) {
202 m->crtc_hsync_start = m->crtc_hdisplay + 10;
203 m->crtc_hsync_end = m->crtc_htotal - 92;
204 m->crtc_vsync_start = m->crtc_vdisplay + 1;
205 m->crtc_vsync_end = m->crtc_vsync_start + 1;
206 if (m->flags & DRM_MODE_FLAG_INTERLACE)
207 interlaced = true;
208 }
209
210 decon_setup_trigger(ctx);
211
212
213 val = VIDOUT_LCD_ON;
214 if (interlaced)
215 val |= VIDOUT_INTERLACE_EN_F;
216 if (crtc->i80_mode) {
217 val |= VIDOUT_COMMAND_IF;
218 } else {
219 val |= VIDOUT_RGB_IF;
220 }
221
222 writel(val, ctx->addr + DECON_VIDOUTCON0);
223
224 if (interlaced)
225 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
226 VIDTCON2_HOZVAL(m->hdisplay - 1);
227 else
228 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
229 VIDTCON2_HOZVAL(m->hdisplay - 1);
230 writel(val, ctx->addr + DECON_VIDTCON2);
231
232 if (!crtc->i80_mode) {
233 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
234 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
235
236 if (interlaced)
237 vbp = vbp / 2 - 1;
238 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
239 writel(val, ctx->addr + DECON_VIDTCON00);
240
241 val = VIDTCON01_VSPW_F(
242 m->crtc_vsync_end - m->crtc_vsync_start - 1);
243 writel(val, ctx->addr + DECON_VIDTCON01);
244
245 val = VIDTCON10_HBPD_F(
246 m->crtc_htotal - m->crtc_hsync_end - 1) |
247 VIDTCON10_HFPD_F(
248 m->crtc_hsync_start - m->crtc_hdisplay - 1);
249 writel(val, ctx->addr + DECON_VIDTCON10);
250
251 val = VIDTCON11_HSPW_F(
252 m->crtc_hsync_end - m->crtc_hsync_start - 1);
253 writel(val, ctx->addr + DECON_VIDTCON11);
254 }
255
256
257 decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
258
259 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
260}
261
262static void decon_win_set_bldeq(struct decon_context *ctx, unsigned int win,
263 unsigned int alpha, unsigned int pixel_alpha)
264{
265 u32 mask = BLENDERQ_A_FUNC_F(0xf) | BLENDERQ_B_FUNC_F(0xf);
266 u32 val = 0;
267
268 switch (pixel_alpha) {
269 case DRM_MODE_BLEND_PIXEL_NONE:
270 case DRM_MODE_BLEND_COVERAGE:
271 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA_A);
272 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
273 break;
274 case DRM_MODE_BLEND_PREMULTI:
275 default:
276 if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
277 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ALPHA0);
278 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
279 } else {
280 val |= BLENDERQ_A_FUNC_F(BLENDERQ_ONE);
281 val |= BLENDERQ_B_FUNC_F(BLENDERQ_ONE_MINUS_ALPHA_A);
282 }
283 break;
284 }
285 decon_set_bits(ctx, DECON_BLENDERQx(win), mask, val);
286}
287
288static void decon_win_set_bldmod(struct decon_context *ctx, unsigned int win,
289 unsigned int alpha, unsigned int pixel_alpha)
290{
291 u32 win_alpha = alpha >> 8;
292 u32 val = 0;
293
294 switch (pixel_alpha) {
295 case DRM_MODE_BLEND_PIXEL_NONE:
296 break;
297 case DRM_MODE_BLEND_COVERAGE:
298 case DRM_MODE_BLEND_PREMULTI:
299 default:
300 val |= WINCONx_ALPHA_SEL_F;
301 val |= WINCONx_BLD_PIX_F;
302 val |= WINCONx_ALPHA_MUL_F;
303 break;
304 }
305 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_BLEND_MODE_MASK, val);
306
307 if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
308 val = VIDOSD_Wx_ALPHA_R_F(win_alpha) |
309 VIDOSD_Wx_ALPHA_G_F(win_alpha) |
310 VIDOSD_Wx_ALPHA_B_F(win_alpha);
311 decon_set_bits(ctx, DECON_VIDOSDxC(win),
312 VIDOSDxC_ALPHA0_RGB_MASK, val);
313 decon_set_bits(ctx, DECON_BLENDCON, BLEND_NEW, BLEND_NEW);
314 }
315}
316
317static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
318 struct drm_framebuffer *fb)
319{
320 struct exynos_drm_plane plane = ctx->planes[win];
321 struct exynos_drm_plane_state *state =
322 to_exynos_plane_state(plane.base.state);
323 unsigned int alpha = state->base.alpha;
324 unsigned int pixel_alpha;
325 unsigned long val;
326
327 if (fb->format->has_alpha)
328 pixel_alpha = state->base.pixel_blend_mode;
329 else
330 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
331
332 val = readl(ctx->addr + DECON_WINCONx(win));
333 val &= WINCONx_ENWIN_F;
334
335 switch (fb->format->format) {
336 case DRM_FORMAT_XRGB1555:
337 val |= WINCONx_BPPMODE_16BPP_I1555;
338 val |= WINCONx_HAWSWP_F;
339 val |= WINCONx_BURSTLEN_16WORD;
340 break;
341 case DRM_FORMAT_RGB565:
342 val |= WINCONx_BPPMODE_16BPP_565;
343 val |= WINCONx_HAWSWP_F;
344 val |= WINCONx_BURSTLEN_16WORD;
345 break;
346 case DRM_FORMAT_XRGB8888:
347 val |= WINCONx_BPPMODE_24BPP_888;
348 val |= WINCONx_WSWP_F;
349 val |= WINCONx_BURSTLEN_16WORD;
350 break;
351 case DRM_FORMAT_ARGB8888:
352 default:
353 val |= WINCONx_BPPMODE_32BPP_A8888;
354 val |= WINCONx_WSWP_F;
355 val |= WINCONx_BURSTLEN_16WORD;
356 break;
357 }
358
359 DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %u\n", fb->format->cpp[0]);
360
361
362
363
364
365
366
367
368
369 if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
370 val &= ~WINCONx_BURSTLEN_MASK;
371 val |= WINCONx_BURSTLEN_8WORD;
372 }
373 decon_set_bits(ctx, DECON_WINCONx(win), ~WINCONx_BLEND_MODE_MASK, val);
374
375 if (win > 0) {
376 decon_win_set_bldmod(ctx, win, alpha, pixel_alpha);
377 decon_win_set_bldeq(ctx, win, alpha, pixel_alpha);
378 }
379}
380
381static void decon_shadow_protect(struct decon_context *ctx, bool protect)
382{
383 decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
384 protect ? ~0 : 0);
385}
386
387static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
388{
389 struct decon_context *ctx = crtc->ctx;
390
391 decon_shadow_protect(ctx, true);
392}
393
394#define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
395#define COORDINATE_X(x) BIT_VAL((x), 23, 12)
396#define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
397
398static void decon_update_plane(struct exynos_drm_crtc *crtc,
399 struct exynos_drm_plane *plane)
400{
401 struct exynos_drm_plane_state *state =
402 to_exynos_plane_state(plane->base.state);
403 struct decon_context *ctx = crtc->ctx;
404 struct drm_framebuffer *fb = state->base.fb;
405 unsigned int win = plane->index;
406 unsigned int cpp = fb->format->cpp[0];
407 unsigned int pitch = fb->pitches[0];
408 dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
409 u32 val;
410
411 if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
412 val = COORDINATE_X(state->crtc.x) |
413 COORDINATE_Y(state->crtc.y / 2);
414 writel(val, ctx->addr + DECON_VIDOSDxA(win));
415
416 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
417 COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
418 writel(val, ctx->addr + DECON_VIDOSDxB(win));
419 } else {
420 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
421 writel(val, ctx->addr + DECON_VIDOSDxA(win));
422
423 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
424 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
425 writel(val, ctx->addr + DECON_VIDOSDxB(win));
426 }
427
428 val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) |
429 VIDOSD_Wx_ALPHA_B_F(0xff);
430 writel(val, ctx->addr + DECON_VIDOSDxC(win));
431
432 val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
433 VIDOSD_Wx_ALPHA_B_F(0x0);
434 writel(val, ctx->addr + DECON_VIDOSDxD(win));
435
436 writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
437
438 val = dma_addr + pitch * state->src.h;
439 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
440
441 if (!(ctx->out_type & IFTYPE_HDMI))
442 val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14)
443 | BIT_VAL(state->crtc.w * cpp, 13, 0);
444 else
445 val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15)
446 | BIT_VAL(state->crtc.w * cpp, 14, 0);
447 writel(val, ctx->addr + DECON_VIDW0xADD2(win));
448
449 decon_win_set_pixfmt(ctx, win, fb);
450
451
452 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
453}
454
455static void decon_disable_plane(struct exynos_drm_crtc *crtc,
456 struct exynos_drm_plane *plane)
457{
458 struct decon_context *ctx = crtc->ctx;
459 unsigned int win = plane->index;
460
461 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
462}
463
464static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
465{
466 struct decon_context *ctx = crtc->ctx;
467 unsigned long flags;
468
469 spin_lock_irqsave(&ctx->vblank_lock, flags);
470
471 decon_shadow_protect(ctx, false);
472
473 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
474
475 ctx->frame_id = decon_get_frame_count(ctx, true);
476
477 exynos_crtc_handle_event(crtc);
478
479 spin_unlock_irqrestore(&ctx->vblank_lock, flags);
480}
481
482static void decon_swreset(struct decon_context *ctx)
483{
484 unsigned long flags;
485 u32 val;
486 int ret;
487
488 writel(0, ctx->addr + DECON_VIDCON0);
489 readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
490 ~val & VIDCON0_STOP_STATUS, 12, 20000);
491
492 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
493 ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
494 ~val & VIDCON0_SWRESET, 12, 20000);
495
496 WARN(ret < 0, "failed to software reset DECON\n");
497
498 spin_lock_irqsave(&ctx->vblank_lock, flags);
499 ctx->frame_id = 0;
500 spin_unlock_irqrestore(&ctx->vblank_lock, flags);
501
502 if (!(ctx->out_type & IFTYPE_HDMI))
503 return;
504
505 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
506 decon_set_bits(ctx, DECON_CMU,
507 CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
508 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
509 writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
510 ctx->addr + DECON_CRCCTRL);
511}
512
513static void decon_atomic_enable(struct exynos_drm_crtc *crtc)
514{
515 struct decon_context *ctx = crtc->ctx;
516 int ret;
517
518 ret = pm_runtime_resume_and_get(ctx->dev);
519 if (ret < 0) {
520 DRM_DEV_ERROR(ctx->dev, "failed to enable DECON device.\n");
521 return;
522 }
523
524 exynos_drm_pipe_clk_enable(crtc, true);
525
526 decon_swreset(ctx);
527
528 decon_commit(ctx->crtc);
529}
530
531static void decon_atomic_disable(struct exynos_drm_crtc *crtc)
532{
533 struct decon_context *ctx = crtc->ctx;
534 int i;
535
536 if (!(ctx->out_type & I80_HW_TRG))
537 synchronize_irq(ctx->te_irq);
538 synchronize_irq(ctx->irq);
539
540
541
542
543
544
545 for (i = ctx->first_win; i < WINDOWS_NR; i++)
546 decon_disable_plane(crtc, &ctx->planes[i]);
547
548 decon_swreset(ctx);
549
550 exynos_drm_pipe_clk_enable(crtc, false);
551
552 pm_runtime_put_sync(ctx->dev);
553}
554
555static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)
556{
557 struct decon_context *ctx = dev_id;
558
559 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
560
561 return IRQ_HANDLED;
562}
563
564static void decon_clear_channels(struct exynos_drm_crtc *crtc)
565{
566 struct decon_context *ctx = crtc->ctx;
567 int win, i, ret;
568
569 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
570 ret = clk_prepare_enable(ctx->clks[i]);
571 if (ret < 0)
572 goto err;
573 }
574
575 decon_shadow_protect(ctx, true);
576 for (win = 0; win < WINDOWS_NR; win++)
577 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
578 decon_shadow_protect(ctx, false);
579
580 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
581
582
583 msleep(50);
584
585err:
586 while (--i >= 0)
587 clk_disable_unprepare(ctx->clks[i]);
588}
589
590static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc,
591 const struct drm_display_mode *mode)
592{
593 struct decon_context *ctx = crtc->ctx;
594
595 ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync;
596
597 if (ctx->irq)
598 return MODE_OK;
599
600 dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n",
601 crtc->i80_mode ? "command" : "video");
602
603 return MODE_BAD;
604}
605
606static const struct exynos_drm_crtc_ops decon_crtc_ops = {
607 .atomic_enable = decon_atomic_enable,
608 .atomic_disable = decon_atomic_disable,
609 .enable_vblank = decon_enable_vblank,
610 .disable_vblank = decon_disable_vblank,
611 .atomic_begin = decon_atomic_begin,
612 .update_plane = decon_update_plane,
613 .disable_plane = decon_disable_plane,
614 .mode_valid = decon_mode_valid,
615 .atomic_flush = decon_atomic_flush,
616};
617
618static int decon_bind(struct device *dev, struct device *master, void *data)
619{
620 struct decon_context *ctx = dev_get_drvdata(dev);
621 struct drm_device *drm_dev = data;
622 struct exynos_drm_plane *exynos_plane;
623 enum exynos_drm_output_type out_type;
624 unsigned int win;
625 int ret;
626
627 ctx->drm_dev = drm_dev;
628
629 for (win = ctx->first_win; win < WINDOWS_NR; win++) {
630 ctx->configs[win].pixel_formats = decon_formats;
631 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
632 ctx->configs[win].zpos = win - ctx->first_win;
633 ctx->configs[win].type = decon_win_types[win];
634 ctx->configs[win].capabilities = capabilities[win];
635
636 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
637 &ctx->configs[win]);
638 if (ret)
639 return ret;
640 }
641
642 exynos_plane = &ctx->planes[PRIMARY_WIN];
643 out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
644 : EXYNOS_DISPLAY_TYPE_LCD;
645 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
646 out_type, &decon_crtc_ops, ctx);
647 if (IS_ERR(ctx->crtc))
648 return PTR_ERR(ctx->crtc);
649
650 decon_clear_channels(ctx->crtc);
651
652 return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
653}
654
655static void decon_unbind(struct device *dev, struct device *master, void *data)
656{
657 struct decon_context *ctx = dev_get_drvdata(dev);
658
659 decon_atomic_disable(ctx->crtc);
660
661
662 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
663}
664
665static const struct component_ops decon_component_ops = {
666 .bind = decon_bind,
667 .unbind = decon_unbind,
668};
669
670static void decon_handle_vblank(struct decon_context *ctx)
671{
672 u32 frm;
673
674 spin_lock(&ctx->vblank_lock);
675
676 frm = decon_get_frame_count(ctx, true);
677
678 if (frm != ctx->frame_id) {
679
680 if ((s32)(frm - ctx->frame_id) > 0)
681 drm_crtc_handle_vblank(&ctx->crtc->base);
682 ctx->frame_id = frm;
683 }
684
685 spin_unlock(&ctx->vblank_lock);
686}
687
688static irqreturn_t decon_irq_handler(int irq, void *dev_id)
689{
690 struct decon_context *ctx = dev_id;
691 u32 val;
692
693 val = readl(ctx->addr + DECON_VIDINTCON1);
694 val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
695
696 if (val) {
697 writel(val, ctx->addr + DECON_VIDINTCON1);
698 if (ctx->out_type & IFTYPE_HDMI) {
699 val = readl(ctx->addr + DECON_VIDOUTCON0);
700 val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
701 if (val ==
702 (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
703 return IRQ_HANDLED;
704 }
705 decon_handle_vblank(ctx);
706 }
707
708 return IRQ_HANDLED;
709}
710
711#ifdef CONFIG_PM
712static int exynos5433_decon_suspend(struct device *dev)
713{
714 struct decon_context *ctx = dev_get_drvdata(dev);
715 int i = ARRAY_SIZE(decon_clks_name);
716
717 while (--i >= 0)
718 clk_disable_unprepare(ctx->clks[i]);
719
720 return 0;
721}
722
723static int exynos5433_decon_resume(struct device *dev)
724{
725 struct decon_context *ctx = dev_get_drvdata(dev);
726 int i, ret;
727
728 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
729 ret = clk_prepare_enable(ctx->clks[i]);
730 if (ret < 0)
731 goto err;
732 }
733
734 return 0;
735
736err:
737 while (--i >= 0)
738 clk_disable_unprepare(ctx->clks[i]);
739
740 return ret;
741}
742#endif
743
744static const struct dev_pm_ops exynos5433_decon_pm_ops = {
745 SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
746 NULL)
747 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
748 pm_runtime_force_resume)
749};
750
751static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
752 {
753 .compatible = "samsung,exynos5433-decon",
754 .data = (void *)I80_HW_TRG
755 },
756 {
757 .compatible = "samsung,exynos5433-decon-tv",
758 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
759 },
760 {},
761};
762MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
763
764static int decon_conf_irq(struct decon_context *ctx, const char *name,
765 irq_handler_t handler, unsigned long int flags)
766{
767 struct platform_device *pdev = to_platform_device(ctx->dev);
768 int ret, irq = platform_get_irq_byname(pdev, name);
769
770 if (irq < 0) {
771 switch (irq) {
772 case -EPROBE_DEFER:
773 return irq;
774 case -ENODATA:
775 case -ENXIO:
776 return 0;
777 default:
778 dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq);
779 return irq;
780 }
781 }
782 ret = devm_request_irq(ctx->dev, irq, handler,
783 flags | IRQF_NO_AUTOEN, "drm_decon", ctx);
784 if (ret < 0) {
785 dev_err(ctx->dev, "IRQ %s request failed\n", name);
786 return ret;
787 }
788
789 return irq;
790}
791
792static int exynos5433_decon_probe(struct platform_device *pdev)
793{
794 struct device *dev = &pdev->dev;
795 struct decon_context *ctx;
796 int ret;
797 int i;
798
799 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
800 if (!ctx)
801 return -ENOMEM;
802
803 ctx->dev = dev;
804 ctx->out_type = (unsigned long)of_device_get_match_data(dev);
805 spin_lock_init(&ctx->vblank_lock);
806
807 if (ctx->out_type & IFTYPE_HDMI)
808 ctx->first_win = 1;
809
810 for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
811 struct clk *clk;
812
813 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
814 if (IS_ERR(clk))
815 return PTR_ERR(clk);
816
817 ctx->clks[i] = clk;
818 }
819
820 ctx->addr = devm_platform_ioremap_resource(pdev, 0);
821 if (IS_ERR(ctx->addr))
822 return PTR_ERR(ctx->addr);
823
824 ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0);
825 if (ret < 0)
826 return ret;
827 ctx->irq_vsync = ret;
828
829 ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0);
830 if (ret < 0)
831 return ret;
832 ctx->irq_lcd_sys = ret;
833
834 ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
835 IRQF_TRIGGER_RISING);
836 if (ret < 0)
837 return ret;
838 if (ret) {
839 ctx->te_irq = ret;
840 ctx->out_type &= ~I80_HW_TRG;
841 }
842
843 if (ctx->out_type & I80_HW_TRG) {
844 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
845 "samsung,disp-sysreg");
846 if (IS_ERR(ctx->sysreg)) {
847 dev_err(dev, "failed to get system register\n");
848 return PTR_ERR(ctx->sysreg);
849 }
850 }
851
852 platform_set_drvdata(pdev, ctx);
853
854 pm_runtime_enable(dev);
855
856 ret = component_add(dev, &decon_component_ops);
857 if (ret)
858 goto err_disable_pm_runtime;
859
860 return 0;
861
862err_disable_pm_runtime:
863 pm_runtime_disable(dev);
864
865 return ret;
866}
867
868static int exynos5433_decon_remove(struct platform_device *pdev)
869{
870 pm_runtime_disable(&pdev->dev);
871
872 component_del(&pdev->dev, &decon_component_ops);
873
874 return 0;
875}
876
877struct platform_driver exynos5433_decon_driver = {
878 .probe = exynos5433_decon_probe,
879 .remove = exynos5433_decon_remove,
880 .driver = {
881 .name = "exynos5433-decon",
882 .pm = &exynos5433_decon_pm_ops,
883 .of_match_table = exynos5433_decon_driver_dt_match,
884 },
885};
886
