LXR linux/drivers/gpu/drm/msm/disp/mdp5/mdp5

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   4 * Copyright (C) 2013 Red Hat
   5 * Author: Rob Clark <robdclark@gmail.com>
   6 */
   7
   8#include <drm/drm_crtc.h>
   9#include <drm/drm_probe_helper.h>
  10
  11#include "mdp5_kms.h"
  12
  13static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
  14{
  15        struct msm_drm_private *priv = encoder->dev->dev_private;
  16        return to_mdp5_kms(to_mdp_kms(priv->kms));
  17}
  18
  19static void mdp5_encoder_destroy(struct drm_encoder *encoder)
  20{
  21        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
  22        drm_encoder_cleanup(encoder);
  23        kfree(mdp5_encoder);
  24}
  25
  26static const struct drm_encoder_funcs mdp5_encoder_funcs = {
  27        .destroy = mdp5_encoder_destroy,
  28};
  29
  30static void mdp5_vid_encoder_mode_set(struct drm_encoder *encoder,
  31                                      struct drm_display_mode *mode,
  32                                      struct drm_display_mode *adjusted_mode)
  33{
  34        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
  35        struct mdp5_kms *mdp5_kms = get_kms(encoder);
  36        struct drm_device *dev = encoder->dev;
  37        struct drm_connector *connector;
  38        int intf = mdp5_encoder->intf->num;
  39        uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
  40        uint32_t display_v_start, display_v_end;
  41        uint32_t hsync_start_x, hsync_end_x;
  42        uint32_t format = 0x2100;
  43        unsigned long flags;
  44
  45        mode = adjusted_mode;
  46
  47        DBG("set mode: " DRM_MODE_FMT, DRM_MODE_ARG(mode));
  48
  49        ctrl_pol = 0;
  50
  51        /* DSI controller cannot handle active-low sync signals. */
  52        if (mdp5_encoder->intf->type != INTF_DSI) {
  53                if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  54                        ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW;
  55                if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  56                        ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW;
  57        }
  58        /* probably need to get DATA_EN polarity from panel.. */
  59
  60        dtv_hsync_skew = 0;  /* get this from panel? */
  61
  62        /* Get color format from panel, default is 8bpc */
  63        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  64                if (connector->encoder == encoder) {
  65                        switch (connector->display_info.bpc) {
  66                        case 4:
  67                                format |= 0;
  68                                break;
  69                        case 5:
  70                                format |= 0x15;
  71                                break;
  72                        case 6:
  73                                format |= 0x2A;
  74                                break;
  75                        case 8:
  76                        default:
  77                                format |= 0x3F;
  78                                break;
  79                        }
  80                        break;
  81                }
  82        }
  83
  84        hsync_start_x = (mode->htotal - mode->hsync_start);
  85        hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
  86
  87        vsync_period = mode->vtotal * mode->htotal;
  88        vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
  89        display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
  90        display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
  91
  92        /*
  93         * For edp only:
  94         * DISPLAY_V_START = (VBP * HCYCLE) + HBP
  95         * DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP
  96         */
  97        if (mdp5_encoder->intf->type == INTF_eDP) {
  98                display_v_start += mode->htotal - mode->hsync_start;
  99                display_v_end -= mode->hsync_start - mode->hdisplay;
 100        }
 101
 102        spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
 103
 104        mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf),
 105                        MDP5_INTF_HSYNC_CTL_PULSEW(mode->hsync_end - mode->hsync_start) |
 106                        MDP5_INTF_HSYNC_CTL_PERIOD(mode->htotal));
 107        mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period);
 108        mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len);
 109        mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf),
 110                        MDP5_INTF_DISPLAY_HCTL_START(hsync_start_x) |
 111                        MDP5_INTF_DISPLAY_HCTL_END(hsync_end_x));
 112        mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start);
 113        mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end);
 114        mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0);
 115        mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff);
 116        mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew);
 117        mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol);
 118        mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_HCTL(intf),
 119                        MDP5_INTF_ACTIVE_HCTL_START(0) |
 120                        MDP5_INTF_ACTIVE_HCTL_END(0));
 121        mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VSTART_F0(intf), 0);
 122        mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VEND_F0(intf), 0);
 123        mdp5_write(mdp5_kms, REG_MDP5_INTF_PANEL_FORMAT(intf), format);
 124        mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(intf), 0x3);  /* frame+line? */
 125
 126        spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
 127
 128        mdp5_crtc_set_pipeline(encoder->crtc);
 129}
 130
 131static void mdp5_vid_encoder_disable(struct drm_encoder *encoder)
 132{
 133        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
 134        struct mdp5_kms *mdp5_kms = get_kms(encoder);
 135        struct mdp5_ctl *ctl = mdp5_encoder->ctl;
 136        struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
 137        struct mdp5_hw_mixer *mixer = mdp5_crtc_get_mixer(encoder->crtc);
 138        struct mdp5_interface *intf = mdp5_encoder->intf;
 139        int intfn = mdp5_encoder->intf->num;
 140        unsigned long flags;
 141
 142        if (WARN_ON(!mdp5_encoder->enabled))
 143                return;
 144
 145        mdp5_ctl_set_encoder_state(ctl, pipeline, false);
 146
 147        spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
 148        mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 0);
 149        spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
 150        mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
 151
 152        /*
 153         * Wait for a vsync so we know the ENABLE=0 latched before
 154         * the (connector) source of the vsync's gets disabled,
 155         * otherwise we end up in a funny state if we re-enable
 156         * before the disable latches, which results that some of
 157         * the settings changes for the new modeset (like new
 158         * scanout buffer) don't latch properly..
 159         */
 160        mdp_irq_wait(&mdp5_kms->base, intf2vblank(mixer, intf));
 161
 162        mdp5_encoder->enabled = false;
 163}
 164
 165static void mdp5_vid_encoder_enable(struct drm_encoder *encoder)
 166{
 167        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
 168        struct mdp5_kms *mdp5_kms = get_kms(encoder);
 169        struct mdp5_ctl *ctl = mdp5_encoder->ctl;
 170        struct mdp5_interface *intf = mdp5_encoder->intf;
 171        struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
 172        int intfn = intf->num;
 173        unsigned long flags;
 174
 175        if (WARN_ON(mdp5_encoder->enabled))
 176                return;
 177
 178        spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
 179        mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 1);
 180        spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
 181        mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf), true);
 182
 183        mdp5_ctl_set_encoder_state(ctl, pipeline, true);
 184
 185        mdp5_encoder->enabled = true;
 186}
 187
 188static void mdp5_encoder_mode_set(struct drm_encoder *encoder,
 189                                  struct drm_display_mode *mode,
 190                                  struct drm_display_mode *adjusted_mode)
 191{
 192        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
 193        struct mdp5_interface *intf = mdp5_encoder->intf;
 194
 195        if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)
 196                mdp5_cmd_encoder_mode_set(encoder, mode, adjusted_mode);
 197        else
 198                mdp5_vid_encoder_mode_set(encoder, mode, adjusted_mode);
 199}
 200
 201static void mdp5_encoder_disable(struct drm_encoder *encoder)
 202{
 203        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
 204        struct mdp5_interface *intf = mdp5_encoder->intf;
 205
 206        if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)
 207                mdp5_cmd_encoder_disable(encoder);
 208        else
 209                mdp5_vid_encoder_disable(encoder);
 210}
 211
 212static void mdp5_encoder_enable(struct drm_encoder *encoder)
 213{
 214        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
 215        struct mdp5_interface *intf = mdp5_encoder->intf;
 216        /* this isn't right I think */
 217        struct drm_crtc_state *cstate = encoder->crtc->state;
 218
 219        mdp5_encoder_mode_set(encoder, &cstate->mode, &cstate->adjusted_mode);
 220
 221        if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)
 222                mdp5_cmd_encoder_enable(encoder);
 223        else
 224                mdp5_vid_encoder_enable(encoder);
 225}
 226
 227static int mdp5_encoder_atomic_check(struct drm_encoder *encoder,
 228                                     struct drm_crtc_state *crtc_state,
 229                                     struct drm_connector_state *conn_state)
 230{
 231        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
 232        struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state);
 233        struct mdp5_interface *intf = mdp5_encoder->intf;
 234        struct mdp5_ctl *ctl = mdp5_encoder->ctl;
 235
 236        mdp5_cstate->ctl = ctl;
 237        mdp5_cstate->pipeline.intf = intf;
 238
 239        /*
 240         * This is a bit awkward, but we want to flush the CTL and hit the
 241         * START bit at most once for an atomic update.  In the non-full-
 242         * modeset case, this is done from crtc->atomic_flush(), but that
 243         * is too early in the case of full modeset, in which case we
 244         * defer to encoder->enable().  But we need to *know* whether
 245         * encoder->enable() will be called to do this:
 246         */
 247        if (drm_atomic_crtc_needs_modeset(crtc_state))
 248                mdp5_cstate->defer_start = true;
 249
 250        return 0;
 251}
 252
 253static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = {
 254        .disable = mdp5_encoder_disable,
 255        .enable = mdp5_encoder_enable,
 256        .atomic_check = mdp5_encoder_atomic_check,
 257};
 258
 259int mdp5_encoder_get_linecount(struct drm_encoder *encoder)
 260{
 261        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
 262        struct mdp5_kms *mdp5_kms = get_kms(encoder);
 263        int intf = mdp5_encoder->intf->num;
 264
 265        return mdp5_read(mdp5_kms, REG_MDP5_INTF_LINE_COUNT(intf));
 266}
 267
 268u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder)
 269{
 270        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
 271        struct mdp5_kms *mdp5_kms = get_kms(encoder);
 272        int intf = mdp5_encoder->intf->num;
 273
 274        return mdp5_read(mdp5_kms, REG_MDP5_INTF_FRAME_COUNT(intf));
 275}
 276
 277int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder,
 278                                       struct drm_encoder *slave_encoder)
 279{
 280        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
 281        struct mdp5_encoder *mdp5_slave_enc = to_mdp5_encoder(slave_encoder);
 282        struct mdp5_kms *mdp5_kms;
 283        struct device *dev;
 284        int intf_num;
 285        u32 data = 0;
 286
 287        if (!encoder || !slave_encoder)
 288                return -EINVAL;
 289
 290        mdp5_kms = get_kms(encoder);
 291        intf_num = mdp5_encoder->intf->num;
 292
 293        /* Switch slave encoder's TimingGen Sync mode,
 294         * to use the master's enable signal for the slave encoder.
 295         */
 296        if (intf_num == 1)
 297                data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC;
 298        else if (intf_num == 2)
 299                data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC;
 300        else
 301                return -EINVAL;
 302
 303        dev = &mdp5_kms->pdev->dev;
 304        /* Make sure clocks are on when connectors calling this function. */
 305        pm_runtime_get_sync(dev);
 306
 307        /* Dumb Panel, Sync mode */
 308        mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0);
 309        mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data);
 310        mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
 311
 312        mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true);
 313
 314        pm_runtime_put_sync(dev);
 315
 316        return 0;
 317}
 318
 319void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode)
 320{
 321        struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
 322        struct mdp5_interface *intf = mdp5_encoder->intf;
 323
 324        /* TODO: Expand this to set writeback modes too */
 325        if (cmd_mode) {
 326                WARN_ON(intf->type != INTF_DSI);
 327                intf->mode = MDP5_INTF_DSI_MODE_COMMAND;
 328        } else {
 329                if (intf->type == INTF_DSI)
 330                        intf->mode = MDP5_INTF_DSI_MODE_VIDEO;
 331                else
 332                        intf->mode = MDP5_INTF_MODE_NONE;
 333        }
 334}
 335
 336/* initialize encoder */
 337struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
 338                                      struct mdp5_interface *intf,
 339                                      struct mdp5_ctl *ctl)
 340{
 341        struct drm_encoder *encoder = NULL;
 342        struct mdp5_encoder *mdp5_encoder;
 343        int enc_type = (intf->type == INTF_DSI) ?
 344                DRM_MODE_ENCODER_DSI : DRM_MODE_ENCODER_TMDS;
 345        int ret;
 346
 347        mdp5_encoder = kzalloc(sizeof(*mdp5_encoder), GFP_KERNEL);
 348        if (!mdp5_encoder) {
 349                ret = -ENOMEM;
 350                goto fail;
 351        }
 352
 353        encoder = &mdp5_encoder->base;
 354        mdp5_encoder->ctl = ctl;
 355        mdp5_encoder->intf = intf;
 356
 357        spin_lock_init(&mdp5_encoder->intf_lock);
 358
 359        drm_encoder_init(dev, encoder, &mdp5_encoder_funcs, enc_type, NULL);
 360
 361        drm_encoder_helper_add(encoder, &mdp5_encoder_helper_funcs);
 362
 363        return encoder;
 364
 365fail:
 366        if (encoder)
 367                mdp5_encoder_destroy(encoder);
 368
 369        return ERR_PTR(ret);
 370}
 371