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8#include <linux/delay.h>
9#include <linux/i2c.h>
10#include <linux/interrupt.h>
11#include <linux/iopoll.h>
12#include <linux/module.h>
13#include <linux/pci.h>
14#include <linux/platform_device.h>
15#include <linux/pm.h>
16#include <linux/pm_runtime.h>
17
18#include <asm/unaligned.h>
19
20
21#define I2C_MST_CNTL 0x00
22#define I2C_MST_CNTL_GEN_START BIT(0)
23#define I2C_MST_CNTL_GEN_STOP BIT(1)
24#define I2C_MST_CNTL_CMD_READ (1 << 2)
25#define I2C_MST_CNTL_CMD_WRITE (2 << 2)
26#define I2C_MST_CNTL_BURST_SIZE_SHIFT 6
27#define I2C_MST_CNTL_GEN_NACK BIT(28)
28#define I2C_MST_CNTL_STATUS GENMASK(30, 29)
29#define I2C_MST_CNTL_STATUS_OKAY (0 << 29)
30#define I2C_MST_CNTL_STATUS_NO_ACK (1 << 29)
31#define I2C_MST_CNTL_STATUS_TIMEOUT (2 << 29)
32#define I2C_MST_CNTL_STATUS_BUS_BUSY (3 << 29)
33#define I2C_MST_CNTL_CYCLE_TRIGGER BIT(31)
34
35#define I2C_MST_ADDR 0x04
36
37#define I2C_MST_I2C0_TIMING 0x08
38#define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ 0x10e
39#define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT 16
40#define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX 255
41#define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK BIT(24)
42
43#define I2C_MST_DATA 0x0c
44
45#define I2C_MST_HYBRID_PADCTL 0x20
46#define I2C_MST_HYBRID_PADCTL_MODE_I2C BIT(0)
47#define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV BIT(14)
48#define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV BIT(15)
49
50struct gpu_i2c_dev {
51 struct device *dev;
52 void __iomem *regs;
53 struct i2c_adapter adapter;
54 struct i2c_board_info *gpu_ccgx_ucsi;
55 struct i2c_client *ccgx_client;
56};
57
58static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd)
59{
60 u32 val;
61
62
63 val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL);
64 val |= I2C_MST_HYBRID_PADCTL_MODE_I2C |
65 I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
66 I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV;
67 writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL);
68
69
70 val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ;
71 val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
72 << I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT);
73 val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK;
74 writel(val, i2cd->regs + I2C_MST_I2C0_TIMING);
75}
76
77static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd)
78{
79 u32 val;
80 int ret;
81
82 ret = readl_poll_timeout(i2cd->regs + I2C_MST_CNTL, val,
83 !(val & I2C_MST_CNTL_CYCLE_TRIGGER) ||
84 (val & I2C_MST_CNTL_STATUS) != I2C_MST_CNTL_STATUS_BUS_BUSY,
85 500, 1000 * USEC_PER_MSEC);
86
87 if (ret) {
88 dev_err(i2cd->dev, "i2c timeout error %x\n", val);
89 return -ETIMEDOUT;
90 }
91
92 val = readl(i2cd->regs + I2C_MST_CNTL);
93 switch (val & I2C_MST_CNTL_STATUS) {
94 case I2C_MST_CNTL_STATUS_OKAY:
95 return 0;
96 case I2C_MST_CNTL_STATUS_NO_ACK:
97 return -ENXIO;
98 case I2C_MST_CNTL_STATUS_TIMEOUT:
99 return -ETIMEDOUT;
100 default:
101 return 0;
102 }
103}
104
105static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len)
106{
107 int status;
108 u32 val;
109
110 val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ |
111 (len << I2C_MST_CNTL_BURST_SIZE_SHIFT) |
112 I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK;
113 writel(val, i2cd->regs + I2C_MST_CNTL);
114
115 status = gpu_i2c_check_status(i2cd);
116 if (status < 0)
117 return status;
118
119 val = readl(i2cd->regs + I2C_MST_DATA);
120 switch (len) {
121 case 1:
122 data[0] = val;
123 break;
124 case 2:
125 put_unaligned_be16(val, data);
126 break;
127 case 3:
128 put_unaligned_be24(val, data);
129 break;
130 case 4:
131 put_unaligned_be32(val, data);
132 break;
133 default:
134 break;
135 }
136 return status;
137}
138
139static int gpu_i2c_start(struct gpu_i2c_dev *i2cd)
140{
141 writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL);
142 return gpu_i2c_check_status(i2cd);
143}
144
145static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd)
146{
147 writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL);
148 return gpu_i2c_check_status(i2cd);
149}
150
151static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data)
152{
153 u32 val;
154
155 writel(data, i2cd->regs + I2C_MST_DATA);
156
157 val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT);
158 writel(val, i2cd->regs + I2C_MST_CNTL);
159
160 return gpu_i2c_check_status(i2cd);
161}
162
163static int gpu_i2c_master_xfer(struct i2c_adapter *adap,
164 struct i2c_msg *msgs, int num)
165{
166 struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap);
167 int status, status2;
168 bool send_stop = true;
169 int i, j;
170
171
172
173
174
175 pm_runtime_get_sync(i2cd->dev);
176 for (i = 0; i < num; i++) {
177 if (msgs[i].flags & I2C_M_RD) {
178
179 writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR);
180
181 status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len);
182 if (status < 0)
183 goto exit;
184 } else {
185 u8 addr = i2c_8bit_addr_from_msg(msgs + i);
186
187 status = gpu_i2c_start(i2cd);
188 if (status < 0) {
189 if (i == 0)
190 send_stop = false;
191 goto exit;
192 }
193
194 status = gpu_i2c_write(i2cd, addr);
195 if (status < 0)
196 goto exit;
197
198 for (j = 0; j < msgs[i].len; j++) {
199 status = gpu_i2c_write(i2cd, msgs[i].buf[j]);
200 if (status < 0)
201 goto exit;
202 }
203 }
204 }
205 send_stop = false;
206 status = gpu_i2c_stop(i2cd);
207 if (status < 0)
208 goto exit;
209
210 status = i;
211exit:
212 if (send_stop) {
213 status2 = gpu_i2c_stop(i2cd);
214 if (status2 < 0)
215 dev_err(i2cd->dev, "i2c stop failed %d\n", status2);
216 }
217 pm_runtime_mark_last_busy(i2cd->dev);
218 pm_runtime_put_autosuspend(i2cd->dev);
219 return status;
220}
221
222static const struct i2c_adapter_quirks gpu_i2c_quirks = {
223 .max_read_len = 4,
224 .max_comb_2nd_msg_len = 4,
225 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
226};
227
228static u32 gpu_i2c_functionality(struct i2c_adapter *adap)
229{
230 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
231}
232
233static const struct i2c_algorithm gpu_i2c_algorithm = {
234 .master_xfer = gpu_i2c_master_xfer,
235 .functionality = gpu_i2c_functionality,
236};
237
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243
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245
246
247
248
249
250
251#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80
252static const struct pci_device_id gpu_i2c_ids[] = {
253 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
254 PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00},
255 { }
256};
257MODULE_DEVICE_TABLE(pci, gpu_i2c_ids);
258
259static const struct property_entry ccgx_props[] = {
260
261 PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'),
262 { }
263};
264
265static const struct software_node ccgx_node = {
266 .properties = ccgx_props,
267};
268
269static int gpu_populate_client(struct gpu_i2c_dev *i2cd, int irq)
270{
271 i2cd->gpu_ccgx_ucsi = devm_kzalloc(i2cd->dev,
272 sizeof(*i2cd->gpu_ccgx_ucsi),
273 GFP_KERNEL);
274 if (!i2cd->gpu_ccgx_ucsi)
275 return -ENOMEM;
276
277 strlcpy(i2cd->gpu_ccgx_ucsi->type, "ccgx-ucsi",
278 sizeof(i2cd->gpu_ccgx_ucsi->type));
279 i2cd->gpu_ccgx_ucsi->addr = 0x8;
280 i2cd->gpu_ccgx_ucsi->irq = irq;
281 i2cd->gpu_ccgx_ucsi->swnode = &ccgx_node;
282 i2cd->ccgx_client = i2c_new_client_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi);
283 return PTR_ERR_OR_ZERO(i2cd->ccgx_client);
284}
285
286static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
287{
288 struct gpu_i2c_dev *i2cd;
289 int status;
290
291 i2cd = devm_kzalloc(&pdev->dev, sizeof(*i2cd), GFP_KERNEL);
292 if (!i2cd)
293 return -ENOMEM;
294
295 i2cd->dev = &pdev->dev;
296 dev_set_drvdata(&pdev->dev, i2cd);
297
298 status = pcim_enable_device(pdev);
299 if (status < 0) {
300 dev_err(&pdev->dev, "pcim_enable_device failed %d\n", status);
301 return status;
302 }
303
304 pci_set_master(pdev);
305
306 i2cd->regs = pcim_iomap(pdev, 0, 0);
307 if (!i2cd->regs) {
308 dev_err(&pdev->dev, "pcim_iomap failed\n");
309 return -ENOMEM;
310 }
311
312 status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
313 if (status < 0) {
314 dev_err(&pdev->dev, "pci_alloc_irq_vectors err %d\n", status);
315 return status;
316 }
317
318 gpu_enable_i2c_bus(i2cd);
319
320 i2c_set_adapdata(&i2cd->adapter, i2cd);
321 i2cd->adapter.owner = THIS_MODULE;
322 strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
323 sizeof(i2cd->adapter.name));
324 i2cd->adapter.algo = &gpu_i2c_algorithm;
325 i2cd->adapter.quirks = &gpu_i2c_quirks;
326 i2cd->adapter.dev.parent = &pdev->dev;
327 status = i2c_add_adapter(&i2cd->adapter);
328 if (status < 0)
329 goto free_irq_vectors;
330
331 status = gpu_populate_client(i2cd, pdev->irq);
332 if (status < 0) {
333 dev_err(&pdev->dev, "gpu_populate_client failed %d\n", status);
334 goto del_adapter;
335 }
336
337 pm_runtime_set_autosuspend_delay(&pdev->dev, 3000);
338 pm_runtime_use_autosuspend(&pdev->dev);
339 pm_runtime_put_autosuspend(&pdev->dev);
340 pm_runtime_allow(&pdev->dev);
341
342 return 0;
343
344del_adapter:
345 i2c_del_adapter(&i2cd->adapter);
346free_irq_vectors:
347 pci_free_irq_vectors(pdev);
348 return status;
349}
350
351static void gpu_i2c_remove(struct pci_dev *pdev)
352{
353 struct gpu_i2c_dev *i2cd = dev_get_drvdata(&pdev->dev);
354
355 pm_runtime_get_noresume(i2cd->dev);
356 i2c_del_adapter(&i2cd->adapter);
357 pci_free_irq_vectors(pdev);
358}
359
360#define gpu_i2c_suspend NULL
361
362static __maybe_unused int gpu_i2c_resume(struct device *dev)
363{
364 struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev);
365
366 gpu_enable_i2c_bus(i2cd);
367
368
369
370
371
372
373 pm_request_resume(&i2cd->ccgx_client->dev);
374 return 0;
375}
376
377static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, gpu_i2c_suspend, gpu_i2c_resume,
378 NULL);
379
380static struct pci_driver gpu_i2c_driver = {
381 .name = "nvidia-gpu",
382 .id_table = gpu_i2c_ids,
383 .probe = gpu_i2c_probe,
384 .remove = gpu_i2c_remove,
385 .driver = {
386 .pm = &gpu_i2c_driver_pm,
387 },
388};
389
390module_pci_driver(gpu_i2c_driver);
391
392MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
393MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver");
394MODULE_LICENSE("GPL v2");
395
