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10#include <linux/bitfield.h>
11#include <linux/clk.h>
12#include <linux/completion.h>
13#include <linux/delay.h>
14#include <linux/iio/iio.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/mod_devicetable.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/reset.h>
22
23#define DRIVER_NAME "rzg2l-adc"
24
25#define RZG2L_ADM(n) ((n) * 0x4)
26#define RZG2L_ADM0_ADCE BIT(0)
27#define RZG2L_ADM0_ADBSY BIT(1)
28#define RZG2L_ADM0_PWDWNB BIT(2)
29#define RZG2L_ADM0_SRESB BIT(15)
30#define RZG2L_ADM1_TRG BIT(0)
31#define RZG2L_ADM1_MS BIT(2)
32#define RZG2L_ADM1_BS BIT(4)
33#define RZG2L_ADM1_EGA_MASK GENMASK(13, 12)
34#define RZG2L_ADM2_CHSEL_MASK GENMASK(7, 0)
35#define RZG2L_ADM3_ADIL_MASK GENMASK(31, 24)
36#define RZG2L_ADM3_ADCMP_MASK GENMASK(23, 16)
37#define RZG2L_ADM3_ADCMP_E FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, 0xe)
38#define RZG2L_ADM3_ADSMP_MASK GENMASK(15, 0)
39
40#define RZG2L_ADINT 0x20
41#define RZG2L_ADINT_INTEN_MASK GENMASK(7, 0)
42#define RZG2L_ADINT_CSEEN BIT(16)
43#define RZG2L_ADINT_INTS BIT(31)
44
45#define RZG2L_ADSTS 0x24
46#define RZG2L_ADSTS_CSEST BIT(16)
47#define RZG2L_ADSTS_INTST_MASK GENMASK(7, 0)
48
49#define RZG2L_ADIVC 0x28
50#define RZG2L_ADIVC_DIVADC_MASK GENMASK(8, 0)
51#define RZG2L_ADIVC_DIVADC_4 FIELD_PREP(RZG2L_ADIVC_DIVADC_MASK, 0x4)
52
53#define RZG2L_ADFIL 0x2c
54
55#define RZG2L_ADCR(n) (0x30 + ((n) * 0x4))
56#define RZG2L_ADCR_AD_MASK GENMASK(11, 0)
57
58#define RZG2L_ADSMP_DEFUALT_SAMPLING 0x578
59
60#define RZG2L_ADC_MAX_CHANNELS 8
61#define RZG2L_ADC_CHN_MASK 0x7
62#define RZG2L_ADC_TIMEOUT usecs_to_jiffies(1 * 4)
63
64struct rzg2l_adc_data {
65 const struct iio_chan_spec *channels;
66 u8 num_channels;
67};
68
69struct rzg2l_adc {
70 void __iomem *base;
71 struct clk *pclk;
72 struct clk *adclk;
73 struct reset_control *presetn;
74 struct reset_control *adrstn;
75 struct completion completion;
76 const struct rzg2l_adc_data *data;
77 struct mutex lock;
78 u16 last_val[RZG2L_ADC_MAX_CHANNELS];
79};
80
81static const char * const rzg2l_adc_channel_name[] = {
82 "adc0",
83 "adc1",
84 "adc2",
85 "adc3",
86 "adc4",
87 "adc5",
88 "adc6",
89 "adc7",
90};
91
92static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg)
93{
94 return readl(adc->base + reg);
95}
96
97static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val)
98{
99 writel(val, adc->base + reg);
100}
101
102static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on)
103{
104 u32 reg;
105
106 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
107 if (on)
108 reg |= RZG2L_ADM0_PWDWNB;
109 else
110 reg &= ~RZG2L_ADM0_PWDWNB;
111 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
112 udelay(2);
113}
114
115static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start)
116{
117 int timeout = 5;
118 u32 reg;
119
120 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
121 if (start)
122 reg |= RZG2L_ADM0_ADCE;
123 else
124 reg &= ~RZG2L_ADM0_ADCE;
125 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
126
127 if (start)
128 return;
129
130 do {
131 usleep_range(100, 200);
132 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
133 timeout--;
134 if (!timeout) {
135 pr_err("%s stopping ADC timed out\n", __func__);
136 break;
137 }
138 } while (((reg & RZG2L_ADM0_ADBSY) || (reg & RZG2L_ADM0_ADCE)));
139}
140
141static void rzg2l_set_trigger(struct rzg2l_adc *adc)
142{
143 u32 reg;
144
145
146
147
148
149
150
151
152 reg = rzg2l_adc_readl(adc, RZG2L_ADM(1));
153 reg &= ~RZG2L_ADM1_EGA_MASK;
154 reg &= ~RZG2L_ADM1_BS;
155 reg &= ~RZG2L_ADM1_TRG;
156 reg |= RZG2L_ADM1_MS;
157 rzg2l_adc_writel(adc, RZG2L_ADM(1), reg);
158}
159
160static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
161{
162 u32 reg;
163
164 if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY)
165 return -EBUSY;
166
167 rzg2l_set_trigger(adc);
168
169
170 reg = rzg2l_adc_readl(adc, RZG2L_ADM(2));
171 reg &= ~RZG2L_ADM2_CHSEL_MASK;
172 reg |= BIT(ch);
173 rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);
174
175
176
177
178
179
180
181 reg = rzg2l_adc_readl(adc, RZG2L_ADINT);
182 reg &= ~RZG2L_ADINT_INTS;
183 reg &= ~RZG2L_ADINT_INTEN_MASK;
184 reg |= (RZG2L_ADINT_CSEEN | BIT(ch));
185 rzg2l_adc_writel(adc, RZG2L_ADINT, reg);
186
187 return 0;
188}
189
190static int rzg2l_adc_set_power(struct iio_dev *indio_dev, bool on)
191{
192 struct device *dev = indio_dev->dev.parent;
193
194 if (on)
195 return pm_runtime_resume_and_get(dev);
196
197 return pm_runtime_put_sync(dev);
198}
199
200static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch)
201{
202 int ret;
203
204 ret = rzg2l_adc_set_power(indio_dev, true);
205 if (ret)
206 return ret;
207
208 ret = rzg2l_adc_conversion_setup(adc, ch);
209 if (ret) {
210 rzg2l_adc_set_power(indio_dev, false);
211 return ret;
212 }
213
214 reinit_completion(&adc->completion);
215
216 rzg2l_adc_start_stop(adc, true);
217
218 if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) {
219 rzg2l_adc_writel(adc, RZG2L_ADINT,
220 rzg2l_adc_readl(adc, RZG2L_ADINT) & ~RZG2L_ADINT_INTEN_MASK);
221 rzg2l_adc_start_stop(adc, false);
222 rzg2l_adc_set_power(indio_dev, false);
223 return -ETIMEDOUT;
224 }
225
226 return rzg2l_adc_set_power(indio_dev, false);
227}
228
229static int rzg2l_adc_read_raw(struct iio_dev *indio_dev,
230 struct iio_chan_spec const *chan,
231 int *val, int *val2, long mask)
232{
233 struct rzg2l_adc *adc = iio_priv(indio_dev);
234 int ret;
235 u8 ch;
236
237 switch (mask) {
238 case IIO_CHAN_INFO_RAW:
239 if (chan->type != IIO_VOLTAGE)
240 return -EINVAL;
241
242 mutex_lock(&adc->lock);
243 ch = chan->channel & RZG2L_ADC_CHN_MASK;
244 ret = rzg2l_adc_conversion(indio_dev, adc, ch);
245 if (ret) {
246 mutex_unlock(&adc->lock);
247 return ret;
248 }
249 *val = adc->last_val[ch];
250 mutex_unlock(&adc->lock);
251
252 return IIO_VAL_INT;
253
254 default:
255 return -EINVAL;
256 }
257}
258
259static int rzg2l_adc_read_label(struct iio_dev *iio_dev,
260 const struct iio_chan_spec *chan,
261 char *label)
262{
263 if (chan->channel >= RZG2L_ADC_MAX_CHANNELS)
264 return -EINVAL;
265
266 return sysfs_emit(label, "%s\n", rzg2l_adc_channel_name[chan->channel]);
267}
268
269static const struct iio_info rzg2l_adc_iio_info = {
270 .read_raw = rzg2l_adc_read_raw,
271 .read_label = rzg2l_adc_read_label,
272};
273
274static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id)
275{
276 struct rzg2l_adc *adc = dev_id;
277 unsigned long intst;
278 u32 reg;
279 int ch;
280
281 reg = rzg2l_adc_readl(adc, RZG2L_ADSTS);
282
283
284 if (reg & RZG2L_ADSTS_CSEST) {
285 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
286 return IRQ_HANDLED;
287 }
288
289 intst = reg & RZG2L_ADSTS_INTST_MASK;
290 if (!intst)
291 return IRQ_NONE;
292
293 for_each_set_bit(ch, &intst, RZG2L_ADC_MAX_CHANNELS)
294 adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;
295
296
297 rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
298
299 complete(&adc->completion);
300
301 return IRQ_HANDLED;
302}
303
304static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc)
305{
306 struct iio_chan_spec *chan_array;
307 struct fwnode_handle *fwnode;
308 struct rzg2l_adc_data *data;
309 unsigned int channel;
310 int num_channels;
311 int ret;
312 u8 i;
313
314 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
315 if (!data)
316 return -ENOMEM;
317
318 num_channels = device_get_child_node_count(&pdev->dev);
319 if (!num_channels) {
320 dev_err(&pdev->dev, "no channel children\n");
321 return -ENODEV;
322 }
323
324 if (num_channels > RZG2L_ADC_MAX_CHANNELS) {
325 dev_err(&pdev->dev, "num of channel children out of range\n");
326 return -EINVAL;
327 }
328
329 chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array),
330 GFP_KERNEL);
331 if (!chan_array)
332 return -ENOMEM;
333
334 i = 0;
335 device_for_each_child_node(&pdev->dev, fwnode) {
336 ret = fwnode_property_read_u32(fwnode, "reg", &channel);
337 if (ret)
338 return ret;
339
340 if (channel >= RZG2L_ADC_MAX_CHANNELS)
341 return -EINVAL;
342
343 chan_array[i].type = IIO_VOLTAGE;
344 chan_array[i].indexed = 1;
345 chan_array[i].channel = channel;
346 chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
347 chan_array[i].datasheet_name = rzg2l_adc_channel_name[channel];
348 i++;
349 }
350
351 data->num_channels = num_channels;
352 data->channels = chan_array;
353 adc->data = data;
354
355 return 0;
356}
357
358static int rzg2l_adc_hw_init(struct rzg2l_adc *adc)
359{
360 int timeout = 5;
361 u32 reg;
362 int ret;
363
364 ret = clk_prepare_enable(adc->pclk);
365 if (ret)
366 return ret;
367
368
369 reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
370 reg |= RZG2L_ADM0_SRESB;
371 rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
372
373 while (!(rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_SRESB)) {
374 if (!timeout) {
375 ret = -EBUSY;
376 goto exit_hw_init;
377 }
378 timeout--;
379 usleep_range(100, 200);
380 }
381
382
383 reg = rzg2l_adc_readl(adc, RZG2L_ADIVC);
384 reg &= ~RZG2L_ADIVC_DIVADC_MASK;
385 reg |= RZG2L_ADIVC_DIVADC_4;
386 rzg2l_adc_writel(adc, RZG2L_ADIVC, reg);
387
388
389
390
391
392
393
394 reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
395 reg &= ~RZG2L_ADM3_ADIL_MASK;
396 reg &= ~RZG2L_ADM3_ADCMP_MASK;
397 reg &= ~RZG2L_ADM3_ADSMP_MASK;
398 reg |= (RZG2L_ADM3_ADCMP_E | RZG2L_ADSMP_DEFUALT_SAMPLING);
399 rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
400
401exit_hw_init:
402 clk_disable_unprepare(adc->pclk);
403
404 return ret;
405}
406
407static void rzg2l_adc_pm_runtime_disable(void *data)
408{
409 struct device *dev = data;
410
411 pm_runtime_disable(dev->parent);
412}
413
414static void rzg2l_adc_pm_runtime_set_suspended(void *data)
415{
416 struct device *dev = data;
417
418 pm_runtime_set_suspended(dev->parent);
419}
420
421static void rzg2l_adc_reset_assert(void *data)
422{
423 reset_control_assert(data);
424}
425
426static int rzg2l_adc_probe(struct platform_device *pdev)
427{
428 struct device *dev = &pdev->dev;
429 struct iio_dev *indio_dev;
430 struct rzg2l_adc *adc;
431 int ret;
432 int irq;
433
434 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
435 if (!indio_dev)
436 return -ENOMEM;
437
438 adc = iio_priv(indio_dev);
439
440 ret = rzg2l_adc_parse_properties(pdev, adc);
441 if (ret)
442 return ret;
443
444 mutex_init(&adc->lock);
445
446 adc->base = devm_platform_ioremap_resource(pdev, 0);
447 if (IS_ERR(adc->base))
448 return PTR_ERR(adc->base);
449
450 adc->pclk = devm_clk_get(dev, "pclk");
451 if (IS_ERR(adc->pclk)) {
452 dev_err(dev, "Failed to get pclk");
453 return PTR_ERR(adc->pclk);
454 }
455
456 adc->adclk = devm_clk_get(dev, "adclk");
457 if (IS_ERR(adc->adclk)) {
458 dev_err(dev, "Failed to get adclk");
459 return PTR_ERR(adc->adclk);
460 }
461
462 adc->adrstn = devm_reset_control_get_exclusive(dev, "adrst-n");
463 if (IS_ERR(adc->adrstn)) {
464 dev_err(dev, "failed to get adrstn\n");
465 return PTR_ERR(adc->adrstn);
466 }
467
468 adc->presetn = devm_reset_control_get_exclusive(dev, "presetn");
469 if (IS_ERR(adc->presetn)) {
470 dev_err(dev, "failed to get presetn\n");
471 return PTR_ERR(adc->presetn);
472 }
473
474 ret = reset_control_deassert(adc->adrstn);
475 if (ret) {
476 dev_err(&pdev->dev, "failed to deassert adrstn pin, %d\n", ret);
477 return ret;
478 }
479
480 ret = devm_add_action_or_reset(&pdev->dev,
481 rzg2l_adc_reset_assert, adc->adrstn);
482 if (ret) {
483 dev_err(&pdev->dev, "failed to register adrstn assert devm action, %d\n",
484 ret);
485 return ret;
486 }
487
488 ret = reset_control_deassert(adc->presetn);
489 if (ret) {
490 dev_err(&pdev->dev, "failed to deassert presetn pin, %d\n", ret);
491 return ret;
492 }
493
494 ret = devm_add_action_or_reset(&pdev->dev,
495 rzg2l_adc_reset_assert, adc->presetn);
496 if (ret) {
497 dev_err(&pdev->dev, "failed to register presetn assert devm action, %d\n",
498 ret);
499 return ret;
500 }
501
502 ret = rzg2l_adc_hw_init(adc);
503 if (ret) {
504 dev_err(&pdev->dev, "failed to initialize ADC HW, %d\n", ret);
505 return ret;
506 }
507
508 irq = platform_get_irq(pdev, 0);
509 if (irq < 0) {
510 dev_err(dev, "no irq resource\n");
511 return irq;
512 }
513
514 ret = devm_request_irq(dev, irq, rzg2l_adc_isr,
515 0, dev_name(dev), adc);
516 if (ret < 0)
517 return ret;
518
519 init_completion(&adc->completion);
520
521 platform_set_drvdata(pdev, indio_dev);
522
523 indio_dev->name = DRIVER_NAME;
524 indio_dev->info = &rzg2l_adc_iio_info;
525 indio_dev->modes = INDIO_DIRECT_MODE;
526 indio_dev->channels = adc->data->channels;
527 indio_dev->num_channels = adc->data->num_channels;
528
529 pm_runtime_set_suspended(dev);
530 ret = devm_add_action_or_reset(&pdev->dev,
531 rzg2l_adc_pm_runtime_set_suspended, &indio_dev->dev);
532 if (ret)
533 return ret;
534
535 pm_runtime_enable(dev);
536 ret = devm_add_action_or_reset(&pdev->dev,
537 rzg2l_adc_pm_runtime_disable, &indio_dev->dev);
538 if (ret)
539 return ret;
540
541 return devm_iio_device_register(dev, indio_dev);
542}
543
544static const struct of_device_id rzg2l_adc_match[] = {
545 { .compatible = "renesas,rzg2l-adc",},
546 { }
547};
548MODULE_DEVICE_TABLE(of, rzg2l_adc_match);
549
550static int __maybe_unused rzg2l_adc_pm_runtime_suspend(struct device *dev)
551{
552 struct iio_dev *indio_dev = dev_get_drvdata(dev);
553 struct rzg2l_adc *adc = iio_priv(indio_dev);
554
555 rzg2l_adc_pwr(adc, false);
556 clk_disable_unprepare(adc->adclk);
557 clk_disable_unprepare(adc->pclk);
558
559 return 0;
560}
561
562static int __maybe_unused rzg2l_adc_pm_runtime_resume(struct device *dev)
563{
564 struct iio_dev *indio_dev = dev_get_drvdata(dev);
565 struct rzg2l_adc *adc = iio_priv(indio_dev);
566 int ret;
567
568 ret = clk_prepare_enable(adc->pclk);
569 if (ret)
570 return ret;
571
572 ret = clk_prepare_enable(adc->adclk);
573 if (ret) {
574 clk_disable_unprepare(adc->pclk);
575 return ret;
576 }
577
578 rzg2l_adc_pwr(adc, true);
579
580 return 0;
581}
582
583static const struct dev_pm_ops rzg2l_adc_pm_ops = {
584 SET_RUNTIME_PM_OPS(rzg2l_adc_pm_runtime_suspend,
585 rzg2l_adc_pm_runtime_resume,
586 NULL)
587};
588
589static struct platform_driver rzg2l_adc_driver = {
590 .probe = rzg2l_adc_probe,
591 .driver = {
592 .name = DRIVER_NAME,
593 .of_match_table = rzg2l_adc_match,
594 .pm = &rzg2l_adc_pm_ops,
595 },
596};
597
598module_platform_driver(rzg2l_adc_driver);
599
600MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
601MODULE_DESCRIPTION("Renesas RZ/G2L ADC driver");
602MODULE_LICENSE("GPL v2");
603
