linux/drivers/infiniband/hw/bnxt_re/ib_verbs.c
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   1/*
   2 * Broadcom NetXtreme-E RoCE driver.
   3 *
   4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6 *
   7 * This software is available to you under a choice of one of two
   8 * licenses.  You may choose to be licensed under the terms of the GNU
   9 * General Public License (GPL) Version 2, available from the file
  10 * COPYING in the main directory of this source tree, or the
  11 * BSD license below:
  12 *
  13 * Redistribution and use in source and binary forms, with or without
  14 * modification, are permitted provided that the following conditions
  15 * are met:
  16 *
  17 * 1. Redistributions of source code must retain the above copyright
  18 *    notice, this list of conditions and the following disclaimer.
  19 * 2. Redistributions in binary form must reproduce the above copyright
  20 *    notice, this list of conditions and the following disclaimer in
  21 *    the documentation and/or other materials provided with the
  22 *    distribution.
  23 *
  24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 *
  36 * Description: IB Verbs interpreter
  37 */
  38
  39#include <linux/interrupt.h>
  40#include <linux/types.h>
  41#include <linux/pci.h>
  42#include <linux/netdevice.h>
  43#include <linux/if_ether.h>
  44#include <net/addrconf.h>
  45
  46#include <rdma/ib_verbs.h>
  47#include <rdma/ib_user_verbs.h>
  48#include <rdma/ib_umem.h>
  49#include <rdma/ib_addr.h>
  50#include <rdma/ib_mad.h>
  51#include <rdma/ib_cache.h>
  52#include <rdma/uverbs_ioctl.h>
  53
  54#include "bnxt_ulp.h"
  55
  56#include "roce_hsi.h"
  57#include "qplib_res.h"
  58#include "qplib_sp.h"
  59#include "qplib_fp.h"
  60#include "qplib_rcfw.h"
  61
  62#include "bnxt_re.h"
  63#include "ib_verbs.h"
  64#include <rdma/bnxt_re-abi.h>
  65
  66static int __from_ib_access_flags(int iflags)
  67{
  68        int qflags = 0;
  69
  70        if (iflags & IB_ACCESS_LOCAL_WRITE)
  71                qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
  72        if (iflags & IB_ACCESS_REMOTE_READ)
  73                qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
  74        if (iflags & IB_ACCESS_REMOTE_WRITE)
  75                qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
  76        if (iflags & IB_ACCESS_REMOTE_ATOMIC)
  77                qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
  78        if (iflags & IB_ACCESS_MW_BIND)
  79                qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
  80        if (iflags & IB_ZERO_BASED)
  81                qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
  82        if (iflags & IB_ACCESS_ON_DEMAND)
  83                qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
  84        return qflags;
  85};
  86
  87static enum ib_access_flags __to_ib_access_flags(int qflags)
  88{
  89        enum ib_access_flags iflags = 0;
  90
  91        if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
  92                iflags |= IB_ACCESS_LOCAL_WRITE;
  93        if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
  94                iflags |= IB_ACCESS_REMOTE_WRITE;
  95        if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
  96                iflags |= IB_ACCESS_REMOTE_READ;
  97        if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
  98                iflags |= IB_ACCESS_REMOTE_ATOMIC;
  99        if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
 100                iflags |= IB_ACCESS_MW_BIND;
 101        if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
 102                iflags |= IB_ZERO_BASED;
 103        if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
 104                iflags |= IB_ACCESS_ON_DEMAND;
 105        return iflags;
 106};
 107
 108static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
 109                             struct bnxt_qplib_sge *sg_list, int num)
 110{
 111        int i, total = 0;
 112
 113        for (i = 0; i < num; i++) {
 114                sg_list[i].addr = ib_sg_list[i].addr;
 115                sg_list[i].lkey = ib_sg_list[i].lkey;
 116                sg_list[i].size = ib_sg_list[i].length;
 117                total += sg_list[i].size;
 118        }
 119        return total;
 120}
 121
 122/* Device */
 123int bnxt_re_query_device(struct ib_device *ibdev,
 124                         struct ib_device_attr *ib_attr,
 125                         struct ib_udata *udata)
 126{
 127        struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 128        struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
 129
 130        memset(ib_attr, 0, sizeof(*ib_attr));
 131        memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
 132               min(sizeof(dev_attr->fw_ver),
 133                   sizeof(ib_attr->fw_ver)));
 134        addrconf_addr_eui48((u8 *)&ib_attr->sys_image_guid,
 135                            rdev->netdev->dev_addr);
 136        ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
 137        ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_SUPPORTED;
 138
 139        ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
 140        ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
 141        ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
 142        ib_attr->max_qp = dev_attr->max_qp;
 143        ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
 144        ib_attr->device_cap_flags =
 145                                    IB_DEVICE_CURR_QP_STATE_MOD
 146                                    | IB_DEVICE_RC_RNR_NAK_GEN
 147                                    | IB_DEVICE_SHUTDOWN_PORT
 148                                    | IB_DEVICE_SYS_IMAGE_GUID
 149                                    | IB_DEVICE_LOCAL_DMA_LKEY
 150                                    | IB_DEVICE_RESIZE_MAX_WR
 151                                    | IB_DEVICE_PORT_ACTIVE_EVENT
 152                                    | IB_DEVICE_N_NOTIFY_CQ
 153                                    | IB_DEVICE_MEM_WINDOW
 154                                    | IB_DEVICE_MEM_WINDOW_TYPE_2B
 155                                    | IB_DEVICE_MEM_MGT_EXTENSIONS;
 156        ib_attr->max_send_sge = dev_attr->max_qp_sges;
 157        ib_attr->max_recv_sge = dev_attr->max_qp_sges;
 158        ib_attr->max_sge_rd = dev_attr->max_qp_sges;
 159        ib_attr->max_cq = dev_attr->max_cq;
 160        ib_attr->max_cqe = dev_attr->max_cq_wqes;
 161        ib_attr->max_mr = dev_attr->max_mr;
 162        ib_attr->max_pd = dev_attr->max_pd;
 163        ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
 164        ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
 165        ib_attr->atomic_cap = IB_ATOMIC_NONE;
 166        ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
 167        if (dev_attr->is_atomic) {
 168                ib_attr->atomic_cap = IB_ATOMIC_GLOB;
 169                ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB;
 170        }
 171
 172        ib_attr->max_ee_rd_atom = 0;
 173        ib_attr->max_res_rd_atom = 0;
 174        ib_attr->max_ee_init_rd_atom = 0;
 175        ib_attr->max_ee = 0;
 176        ib_attr->max_rdd = 0;
 177        ib_attr->max_mw = dev_attr->max_mw;
 178        ib_attr->max_raw_ipv6_qp = 0;
 179        ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
 180        ib_attr->max_mcast_grp = 0;
 181        ib_attr->max_mcast_qp_attach = 0;
 182        ib_attr->max_total_mcast_qp_attach = 0;
 183        ib_attr->max_ah = dev_attr->max_ah;
 184
 185        ib_attr->max_srq = dev_attr->max_srq;
 186        ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
 187        ib_attr->max_srq_sge = dev_attr->max_srq_sges;
 188
 189        ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
 190
 191        ib_attr->max_pkeys = 1;
 192        ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
 193        return 0;
 194}
 195
 196/* Port */
 197int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num,
 198                       struct ib_port_attr *port_attr)
 199{
 200        struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 201        struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
 202
 203        memset(port_attr, 0, sizeof(*port_attr));
 204
 205        if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
 206                port_attr->state = IB_PORT_ACTIVE;
 207                port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
 208        } else {
 209                port_attr->state = IB_PORT_DOWN;
 210                port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED;
 211        }
 212        port_attr->max_mtu = IB_MTU_4096;
 213        port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
 214        port_attr->gid_tbl_len = dev_attr->max_sgid;
 215        port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
 216                                    IB_PORT_DEVICE_MGMT_SUP |
 217                                    IB_PORT_VENDOR_CLASS_SUP;
 218        port_attr->ip_gids = true;
 219
 220        port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
 221        port_attr->bad_pkey_cntr = 0;
 222        port_attr->qkey_viol_cntr = 0;
 223        port_attr->pkey_tbl_len = dev_attr->max_pkey;
 224        port_attr->lid = 0;
 225        port_attr->sm_lid = 0;
 226        port_attr->lmc = 0;
 227        port_attr->max_vl_num = 4;
 228        port_attr->sm_sl = 0;
 229        port_attr->subnet_timeout = 0;
 230        port_attr->init_type_reply = 0;
 231        port_attr->active_speed = rdev->active_speed;
 232        port_attr->active_width = rdev->active_width;
 233
 234        return 0;
 235}
 236
 237int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num,
 238                               struct ib_port_immutable *immutable)
 239{
 240        struct ib_port_attr port_attr;
 241
 242        if (bnxt_re_query_port(ibdev, port_num, &port_attr))
 243                return -EINVAL;
 244
 245        immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
 246        immutable->gid_tbl_len = port_attr.gid_tbl_len;
 247        immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
 248        immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
 249        immutable->max_mad_size = IB_MGMT_MAD_SIZE;
 250        return 0;
 251}
 252
 253void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
 254{
 255        struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 256
 257        snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
 258                 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1],
 259                 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]);
 260}
 261
 262int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num,
 263                       u16 index, u16 *pkey)
 264{
 265        struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 266
 267        /* Ignore port_num */
 268
 269        memset(pkey, 0, sizeof(*pkey));
 270        return bnxt_qplib_get_pkey(&rdev->qplib_res,
 271                                   &rdev->qplib_res.pkey_tbl, index, pkey);
 272}
 273
 274int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num,
 275                      int index, union ib_gid *gid)
 276{
 277        struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 278        int rc = 0;
 279
 280        /* Ignore port_num */
 281        memset(gid, 0, sizeof(*gid));
 282        rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
 283                                 &rdev->qplib_res.sgid_tbl, index,
 284                                 (struct bnxt_qplib_gid *)gid);
 285        return rc;
 286}
 287
 288int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
 289{
 290        int rc = 0;
 291        struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
 292        struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
 293        struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
 294        struct bnxt_qplib_gid *gid_to_del;
 295        u16 vlan_id = 0xFFFF;
 296
 297        /* Delete the entry from the hardware */
 298        ctx = *context;
 299        if (!ctx)
 300                return -EINVAL;
 301
 302        if (sgid_tbl && sgid_tbl->active) {
 303                if (ctx->idx >= sgid_tbl->max)
 304                        return -EINVAL;
 305                gid_to_del = &sgid_tbl->tbl[ctx->idx].gid;
 306                vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id;
 307                /* DEL_GID is called in WQ context(netdevice_event_work_handler)
 308                 * or via the ib_unregister_device path. In the former case QP1
 309                 * may not be destroyed yet, in which case just return as FW
 310                 * needs that entry to be present and will fail it's deletion.
 311                 * We could get invoked again after QP1 is destroyed OR get an
 312                 * ADD_GID call with a different GID value for the same index
 313                 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
 314                 */
 315                if (ctx->idx == 0 &&
 316                    rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
 317                    ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) {
 318                        ibdev_dbg(&rdev->ibdev,
 319                                  "Trying to delete GID0 while QP1 is alive\n");
 320                        return -EFAULT;
 321                }
 322                ctx->refcnt--;
 323                if (!ctx->refcnt) {
 324                        rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del,
 325                                                 vlan_id,  true);
 326                        if (rc) {
 327                                ibdev_err(&rdev->ibdev,
 328                                          "Failed to remove GID: %#x", rc);
 329                        } else {
 330                                ctx_tbl = sgid_tbl->ctx;
 331                                ctx_tbl[ctx->idx] = NULL;
 332                                kfree(ctx);
 333                        }
 334                }
 335        } else {
 336                return -EINVAL;
 337        }
 338        return rc;
 339}
 340
 341int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
 342{
 343        int rc;
 344        u32 tbl_idx = 0;
 345        u16 vlan_id = 0xFFFF;
 346        struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
 347        struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
 348        struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
 349
 350        rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL);
 351        if (rc)
 352                return rc;
 353
 354        rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
 355                                 rdev->qplib_res.netdev->dev_addr,
 356                                 vlan_id, true, &tbl_idx);
 357        if (rc == -EALREADY) {
 358                ctx_tbl = sgid_tbl->ctx;
 359                ctx_tbl[tbl_idx]->refcnt++;
 360                *context = ctx_tbl[tbl_idx];
 361                return 0;
 362        }
 363
 364        if (rc < 0) {
 365                ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc);
 366                return rc;
 367        }
 368
 369        ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
 370        if (!ctx)
 371                return -ENOMEM;
 372        ctx_tbl = sgid_tbl->ctx;
 373        ctx->idx = tbl_idx;
 374        ctx->refcnt = 1;
 375        ctx_tbl[tbl_idx] = ctx;
 376        *context = ctx;
 377
 378        return rc;
 379}
 380
 381enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
 382                                            u32 port_num)
 383{
 384        return IB_LINK_LAYER_ETHERNET;
 385}
 386
 387#define BNXT_RE_FENCE_PBL_SIZE  DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
 388
 389static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
 390{
 391        struct bnxt_re_fence_data *fence = &pd->fence;
 392        struct ib_mr *ib_mr = &fence->mr->ib_mr;
 393        struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
 394
 395        memset(wqe, 0, sizeof(*wqe));
 396        wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
 397        wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
 398        wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
 399        wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
 400        wqe->bind.zero_based = false;
 401        wqe->bind.parent_l_key = ib_mr->lkey;
 402        wqe->bind.va = (u64)(unsigned long)fence->va;
 403        wqe->bind.length = fence->size;
 404        wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
 405        wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
 406
 407        /* Save the initial rkey in fence structure for now;
 408         * wqe->bind.r_key will be set at (re)bind time.
 409         */
 410        fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
 411}
 412
 413static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
 414{
 415        struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
 416                                             qplib_qp);
 417        struct ib_pd *ib_pd = qp->ib_qp.pd;
 418        struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
 419        struct bnxt_re_fence_data *fence = &pd->fence;
 420        struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
 421        struct bnxt_qplib_swqe wqe;
 422        int rc;
 423
 424        memcpy(&wqe, fence_wqe, sizeof(wqe));
 425        wqe.bind.r_key = fence->bind_rkey;
 426        fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
 427
 428        ibdev_dbg(&qp->rdev->ibdev,
 429                  "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
 430                wqe.bind.r_key, qp->qplib_qp.id, pd);
 431        rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
 432        if (rc) {
 433                ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n");
 434                return rc;
 435        }
 436        bnxt_qplib_post_send_db(&qp->qplib_qp);
 437
 438        return rc;
 439}
 440
 441static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
 442{
 443        struct bnxt_re_fence_data *fence = &pd->fence;
 444        struct bnxt_re_dev *rdev = pd->rdev;
 445        struct device *dev = &rdev->en_dev->pdev->dev;
 446        struct bnxt_re_mr *mr = fence->mr;
 447
 448        if (fence->mw) {
 449                bnxt_re_dealloc_mw(fence->mw);
 450                fence->mw = NULL;
 451        }
 452        if (mr) {
 453                if (mr->ib_mr.rkey)
 454                        bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
 455                                             true);
 456                if (mr->ib_mr.lkey)
 457                        bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
 458                kfree(mr);
 459                fence->mr = NULL;
 460        }
 461        if (fence->dma_addr) {
 462                dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
 463                                 DMA_BIDIRECTIONAL);
 464                fence->dma_addr = 0;
 465        }
 466}
 467
 468static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
 469{
 470        int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
 471        struct bnxt_re_fence_data *fence = &pd->fence;
 472        struct bnxt_re_dev *rdev = pd->rdev;
 473        struct device *dev = &rdev->en_dev->pdev->dev;
 474        struct bnxt_re_mr *mr = NULL;
 475        dma_addr_t dma_addr = 0;
 476        struct ib_mw *mw;
 477        int rc;
 478
 479        dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
 480                                  DMA_BIDIRECTIONAL);
 481        rc = dma_mapping_error(dev, dma_addr);
 482        if (rc) {
 483                ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n");
 484                rc = -EIO;
 485                fence->dma_addr = 0;
 486                goto fail;
 487        }
 488        fence->dma_addr = dma_addr;
 489
 490        /* Allocate a MR */
 491        mr = kzalloc(sizeof(*mr), GFP_KERNEL);
 492        if (!mr) {
 493                rc = -ENOMEM;
 494                goto fail;
 495        }
 496        fence->mr = mr;
 497        mr->rdev = rdev;
 498        mr->qplib_mr.pd = &pd->qplib_pd;
 499        mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
 500        mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
 501        rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
 502        if (rc) {
 503                ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n");
 504                goto fail;
 505        }
 506
 507        /* Register MR */
 508        mr->ib_mr.lkey = mr->qplib_mr.lkey;
 509        mr->qplib_mr.va = (u64)(unsigned long)fence->va;
 510        mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
 511        rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL,
 512                               BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE);
 513        if (rc) {
 514                ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n");
 515                goto fail;
 516        }
 517        mr->ib_mr.rkey = mr->qplib_mr.rkey;
 518
 519        /* Create a fence MW only for kernel consumers */
 520        mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
 521        if (IS_ERR(mw)) {
 522                ibdev_err(&rdev->ibdev,
 523                          "Failed to create fence-MW for PD: %p\n", pd);
 524                rc = PTR_ERR(mw);
 525                goto fail;
 526        }
 527        fence->mw = mw;
 528
 529        bnxt_re_create_fence_wqe(pd);
 530        return 0;
 531
 532fail:
 533        bnxt_re_destroy_fence_mr(pd);
 534        return rc;
 535}
 536
 537/* Protection Domains */
 538int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata)
 539{
 540        struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
 541        struct bnxt_re_dev *rdev = pd->rdev;
 542
 543        bnxt_re_destroy_fence_mr(pd);
 544
 545        if (pd->qplib_pd.id) {
 546                if (!bnxt_qplib_dealloc_pd(&rdev->qplib_res,
 547                                           &rdev->qplib_res.pd_tbl,
 548                                           &pd->qplib_pd))
 549                        atomic_dec(&rdev->pd_count);
 550        }
 551        return 0;
 552}
 553
 554int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
 555{
 556        struct ib_device *ibdev = ibpd->device;
 557        struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
 558        struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context(
 559                udata, struct bnxt_re_ucontext, ib_uctx);
 560        struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd);
 561        int rc;
 562
 563        pd->rdev = rdev;
 564        if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
 565                ibdev_err(&rdev->ibdev, "Failed to allocate HW PD");
 566                rc = -ENOMEM;
 567                goto fail;
 568        }
 569
 570        if (udata) {
 571                struct bnxt_re_pd_resp resp;
 572
 573                if (!ucntx->dpi.dbr) {
 574                        /* Allocate DPI in alloc_pd to avoid failing of
 575                         * ibv_devinfo and family of application when DPIs
 576                         * are depleted.
 577                         */
 578                        if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
 579                                                 &ucntx->dpi, ucntx)) {
 580                                rc = -ENOMEM;
 581                                goto dbfail;
 582                        }
 583                }
 584
 585                resp.pdid = pd->qplib_pd.id;
 586                /* Still allow mapping this DBR to the new user PD. */
 587                resp.dpi = ucntx->dpi.dpi;
 588                resp.dbr = (u64)ucntx->dpi.umdbr;
 589
 590                rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
 591                if (rc) {
 592                        ibdev_err(&rdev->ibdev,
 593                                  "Failed to copy user response\n");
 594                        goto dbfail;
 595                }
 596        }
 597
 598        if (!udata)
 599                if (bnxt_re_create_fence_mr(pd))
 600                        ibdev_warn(&rdev->ibdev,
 601                                   "Failed to create Fence-MR\n");
 602        atomic_inc(&rdev->pd_count);
 603
 604        return 0;
 605dbfail:
 606        bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
 607                              &pd->qplib_pd);
 608fail:
 609        return rc;
 610}
 611
 612/* Address Handles */
 613int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags)
 614{
 615        struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
 616        struct bnxt_re_dev *rdev = ah->rdev;
 617
 618        bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah,
 619                              !(flags & RDMA_DESTROY_AH_SLEEPABLE));
 620        atomic_dec(&rdev->ah_count);
 621
 622        return 0;
 623}
 624
 625static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
 626{
 627        u8 nw_type;
 628
 629        switch (ntype) {
 630        case RDMA_NETWORK_IPV4:
 631                nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
 632                break;
 633        case RDMA_NETWORK_IPV6:
 634                nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
 635                break;
 636        default:
 637                nw_type = CMDQ_CREATE_AH_TYPE_V1;
 638                break;
 639        }
 640        return nw_type;
 641}
 642
 643int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr,
 644                      struct ib_udata *udata)
 645{
 646        struct ib_pd *ib_pd = ib_ah->pd;
 647        struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
 648        struct rdma_ah_attr *ah_attr = init_attr->ah_attr;
 649        const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
 650        struct bnxt_re_dev *rdev = pd->rdev;
 651        const struct ib_gid_attr *sgid_attr;
 652        struct bnxt_re_gid_ctx *ctx;
 653        struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
 654        u8 nw_type;
 655        int rc;
 656
 657        if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
 658                ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set");
 659                return -EINVAL;
 660        }
 661
 662        ah->rdev = rdev;
 663        ah->qplib_ah.pd = &pd->qplib_pd;
 664
 665        /* Supply the configuration for the HW */
 666        memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
 667               sizeof(union ib_gid));
 668        sgid_attr = grh->sgid_attr;
 669        /* Get the HW context of the GID. The reference
 670         * of GID table entry is already taken by the caller.
 671         */
 672        ctx = rdma_read_gid_hw_context(sgid_attr);
 673        ah->qplib_ah.sgid_index = ctx->idx;
 674        ah->qplib_ah.host_sgid_index = grh->sgid_index;
 675        ah->qplib_ah.traffic_class = grh->traffic_class;
 676        ah->qplib_ah.flow_label = grh->flow_label;
 677        ah->qplib_ah.hop_limit = grh->hop_limit;
 678        ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
 679
 680        /* Get network header type for this GID */
 681        nw_type = rdma_gid_attr_network_type(sgid_attr);
 682        ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
 683
 684        memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
 685        rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah,
 686                                  !(init_attr->flags &
 687                                    RDMA_CREATE_AH_SLEEPABLE));
 688        if (rc) {
 689                ibdev_err(&rdev->ibdev, "Failed to allocate HW AH");
 690                return rc;
 691        }
 692
 693        /* Write AVID to shared page. */
 694        if (udata) {
 695                struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
 696                        udata, struct bnxt_re_ucontext, ib_uctx);
 697                unsigned long flag;
 698                u32 *wrptr;
 699
 700                spin_lock_irqsave(&uctx->sh_lock, flag);
 701                wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
 702                *wrptr = ah->qplib_ah.id;
 703                wmb(); /* make sure cache is updated. */
 704                spin_unlock_irqrestore(&uctx->sh_lock, flag);
 705        }
 706        atomic_inc(&rdev->ah_count);
 707
 708        return 0;
 709}
 710
 711int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
 712{
 713        struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
 714
 715        ah_attr->type = ib_ah->type;
 716        rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
 717        memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
 718        rdma_ah_set_grh(ah_attr, NULL, 0,
 719                        ah->qplib_ah.host_sgid_index,
 720                        0, ah->qplib_ah.traffic_class);
 721        rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
 722        rdma_ah_set_port_num(ah_attr, 1);
 723        rdma_ah_set_static_rate(ah_attr, 0);
 724        return 0;
 725}
 726
 727unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
 728        __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
 729{
 730        unsigned long flags;
 731
 732        spin_lock_irqsave(&qp->scq->cq_lock, flags);
 733        if (qp->rcq != qp->scq)
 734                spin_lock(&qp->rcq->cq_lock);
 735        else
 736                __acquire(&qp->rcq->cq_lock);
 737
 738        return flags;
 739}
 740
 741void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
 742                        unsigned long flags)
 743        __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
 744{
 745        if (qp->rcq != qp->scq)
 746                spin_unlock(&qp->rcq->cq_lock);
 747        else
 748                __release(&qp->rcq->cq_lock);
 749        spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
 750}
 751
 752static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp)
 753{
 754        struct bnxt_re_qp *gsi_sqp;
 755        struct bnxt_re_ah *gsi_sah;
 756        struct bnxt_re_dev *rdev;
 757        int rc = 0;
 758
 759        rdev = qp->rdev;
 760        gsi_sqp = rdev->gsi_ctx.gsi_sqp;
 761        gsi_sah = rdev->gsi_ctx.gsi_sah;
 762
 763        ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n");
 764        bnxt_qplib_destroy_ah(&rdev->qplib_res,
 765                              &gsi_sah->qplib_ah,
 766                              true);
 767        atomic_dec(&rdev->ah_count);
 768        bnxt_qplib_clean_qp(&qp->qplib_qp);
 769
 770        ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n");
 771        rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp);
 772        if (rc) {
 773                ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed");
 774                goto fail;
 775        }
 776        bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp);
 777
 778        /* remove from active qp list */
 779        mutex_lock(&rdev->qp_lock);
 780        list_del(&gsi_sqp->list);
 781        mutex_unlock(&rdev->qp_lock);
 782        atomic_dec(&rdev->qp_count);
 783
 784        kfree(rdev->gsi_ctx.sqp_tbl);
 785        kfree(gsi_sah);
 786        kfree(gsi_sqp);
 787        rdev->gsi_ctx.gsi_sqp = NULL;
 788        rdev->gsi_ctx.gsi_sah = NULL;
 789        rdev->gsi_ctx.sqp_tbl = NULL;
 790
 791        return 0;
 792fail:
 793        return rc;
 794}
 795
 796/* Queue Pairs */
 797int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
 798{
 799        struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
 800        struct bnxt_re_dev *rdev = qp->rdev;
 801        unsigned int flags;
 802        int rc;
 803
 804        bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
 805
 806        rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
 807        if (rc) {
 808                ibdev_err(&rdev->ibdev, "Failed to destroy HW QP");
 809                return rc;
 810        }
 811
 812        if (rdma_is_kernel_res(&qp->ib_qp.res)) {
 813                flags = bnxt_re_lock_cqs(qp);
 814                bnxt_qplib_clean_qp(&qp->qplib_qp);
 815                bnxt_re_unlock_cqs(qp, flags);
 816        }
 817
 818        bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
 819
 820        if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) {
 821                rc = bnxt_re_destroy_gsi_sqp(qp);
 822                if (rc)
 823                        return rc;
 824        }
 825
 826        mutex_lock(&rdev->qp_lock);
 827        list_del(&qp->list);
 828        mutex_unlock(&rdev->qp_lock);
 829        atomic_dec(&rdev->qp_count);
 830
 831        ib_umem_release(qp->rumem);
 832        ib_umem_release(qp->sumem);
 833
 834        return 0;
 835}
 836
 837static u8 __from_ib_qp_type(enum ib_qp_type type)
 838{
 839        switch (type) {
 840        case IB_QPT_GSI:
 841                return CMDQ_CREATE_QP1_TYPE_GSI;
 842        case IB_QPT_RC:
 843                return CMDQ_CREATE_QP_TYPE_RC;
 844        case IB_QPT_UD:
 845                return CMDQ_CREATE_QP_TYPE_UD;
 846        default:
 847                return IB_QPT_MAX;
 848        }
 849}
 850
 851static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp,
 852                                   int rsge, int max)
 853{
 854        if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
 855                rsge = max;
 856        return bnxt_re_get_rwqe_size(rsge);
 857}
 858
 859static u16 bnxt_re_get_wqe_size(int ilsize, int nsge)
 860{
 861        u16 wqe_size, calc_ils;
 862
 863        wqe_size = bnxt_re_get_swqe_size(nsge);
 864        if (ilsize) {
 865                calc_ils = sizeof(struct sq_send_hdr) + ilsize;
 866                wqe_size = max_t(u16, calc_ils, wqe_size);
 867                wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr));
 868        }
 869        return wqe_size;
 870}
 871
 872static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp,
 873                                   struct ib_qp_init_attr *init_attr)
 874{
 875        struct bnxt_qplib_dev_attr *dev_attr;
 876        struct bnxt_qplib_qp *qplqp;
 877        struct bnxt_re_dev *rdev;
 878        struct bnxt_qplib_q *sq;
 879        int align, ilsize;
 880
 881        rdev = qp->rdev;
 882        qplqp = &qp->qplib_qp;
 883        sq = &qplqp->sq;
 884        dev_attr = &rdev->dev_attr;
 885
 886        align = sizeof(struct sq_send_hdr);
 887        ilsize = ALIGN(init_attr->cap.max_inline_data, align);
 888
 889        sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge);
 890        if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges))
 891                return -EINVAL;
 892        /* For gen p4 and gen p5 backward compatibility mode
 893         * wqe size is fixed to 128 bytes
 894         */
 895        if (sq->wqe_size < bnxt_re_get_swqe_size(dev_attr->max_qp_sges) &&
 896                        qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
 897                sq->wqe_size = bnxt_re_get_swqe_size(dev_attr->max_qp_sges);
 898
 899        if (init_attr->cap.max_inline_data) {
 900                qplqp->max_inline_data = sq->wqe_size -
 901                        sizeof(struct sq_send_hdr);
 902                init_attr->cap.max_inline_data = qplqp->max_inline_data;
 903                if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
 904                        sq->max_sge = qplqp->max_inline_data /
 905                                sizeof(struct sq_sge);
 906        }
 907
 908        return 0;
 909}
 910
 911static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
 912                                struct bnxt_re_qp *qp, struct ib_udata *udata)
 913{
 914        struct bnxt_qplib_qp *qplib_qp;
 915        struct bnxt_re_ucontext *cntx;
 916        struct bnxt_re_qp_req ureq;
 917        int bytes = 0, psn_sz;
 918        struct ib_umem *umem;
 919        int psn_nume;
 920
 921        qplib_qp = &qp->qplib_qp;
 922        cntx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext,
 923                                         ib_uctx);
 924        if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
 925                return -EFAULT;
 926
 927        bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size);
 928        /* Consider mapping PSN search memory only for RC QPs. */
 929        if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
 930                psn_sz = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?
 931                                                   sizeof(struct sq_psn_search_ext) :
 932                                                   sizeof(struct sq_psn_search);
 933                psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
 934                            qplib_qp->sq.max_wqe :
 935                            ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) /
 936                              sizeof(struct bnxt_qplib_sge));
 937                bytes += (psn_nume * psn_sz);
 938        }
 939
 940        bytes = PAGE_ALIGN(bytes);
 941        umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes,
 942                           IB_ACCESS_LOCAL_WRITE);
 943        if (IS_ERR(umem))
 944                return PTR_ERR(umem);
 945
 946        qp->sumem = umem;
 947        qplib_qp->sq.sg_info.umem = umem;
 948        qplib_qp->sq.sg_info.pgsize = PAGE_SIZE;
 949        qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT;
 950        qplib_qp->qp_handle = ureq.qp_handle;
 951
 952        if (!qp->qplib_qp.srq) {
 953                bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size);
 954                bytes = PAGE_ALIGN(bytes);
 955                umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes,
 956                                   IB_ACCESS_LOCAL_WRITE);
 957                if (IS_ERR(umem))
 958                        goto rqfail;
 959                qp->rumem = umem;
 960                qplib_qp->rq.sg_info.umem = umem;
 961                qplib_qp->rq.sg_info.pgsize = PAGE_SIZE;
 962                qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT;
 963        }
 964
 965        qplib_qp->dpi = &cntx->dpi;
 966        return 0;
 967rqfail:
 968        ib_umem_release(qp->sumem);
 969        qp->sumem = NULL;
 970        memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info));
 971
 972        return PTR_ERR(umem);
 973}
 974
 975static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
 976                                (struct bnxt_re_pd *pd,
 977                                 struct bnxt_qplib_res *qp1_res,
 978                                 struct bnxt_qplib_qp *qp1_qp)
 979{
 980        struct bnxt_re_dev *rdev = pd->rdev;
 981        struct bnxt_re_ah *ah;
 982        union ib_gid sgid;
 983        int rc;
 984
 985        ah = kzalloc(sizeof(*ah), GFP_KERNEL);
 986        if (!ah)
 987                return NULL;
 988
 989        ah->rdev = rdev;
 990        ah->qplib_ah.pd = &pd->qplib_pd;
 991
 992        rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
 993        if (rc)
 994                goto fail;
 995
 996        /* supply the dgid data same as sgid */
 997        memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
 998               sizeof(union ib_gid));
 999        ah->qplib_ah.sgid_index = 0;
1000
1001        ah->qplib_ah.traffic_class = 0;
1002        ah->qplib_ah.flow_label = 0;
1003        ah->qplib_ah.hop_limit = 1;
1004        ah->qplib_ah.sl = 0;
1005        /* Have DMAC same as SMAC */
1006        ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
1007
1008        rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false);
1009        if (rc) {
1010                ibdev_err(&rdev->ibdev,
1011                          "Failed to allocate HW AH for Shadow QP");
1012                goto fail;
1013        }
1014        atomic_inc(&rdev->ah_count);
1015
1016        return ah;
1017
1018fail:
1019        kfree(ah);
1020        return NULL;
1021}
1022
1023static struct bnxt_re_qp *bnxt_re_create_shadow_qp
1024                                (struct bnxt_re_pd *pd,
1025                                 struct bnxt_qplib_res *qp1_res,
1026                                 struct bnxt_qplib_qp *qp1_qp)
1027{
1028        struct bnxt_re_dev *rdev = pd->rdev;
1029        struct bnxt_re_qp *qp;
1030        int rc;
1031
1032        qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1033        if (!qp)
1034                return NULL;
1035
1036        qp->rdev = rdev;
1037
1038        /* Initialize the shadow QP structure from the QP1 values */
1039        ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1040
1041        qp->qplib_qp.pd = &pd->qplib_pd;
1042        qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1043        qp->qplib_qp.type = IB_QPT_UD;
1044
1045        qp->qplib_qp.max_inline_data = 0;
1046        qp->qplib_qp.sig_type = true;
1047
1048        /* Shadow QP SQ depth should be same as QP1 RQ depth */
1049        qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6);
1050        qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
1051        qp->qplib_qp.sq.max_sge = 2;
1052        /* Q full delta can be 1 since it is internal QP */
1053        qp->qplib_qp.sq.q_full_delta = 1;
1054        qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE;
1055        qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT;
1056
1057        qp->qplib_qp.scq = qp1_qp->scq;
1058        qp->qplib_qp.rcq = qp1_qp->rcq;
1059
1060        qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6);
1061        qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
1062        qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
1063        /* Q full delta can be 1 since it is internal QP */
1064        qp->qplib_qp.rq.q_full_delta = 1;
1065        qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE;
1066        qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT;
1067
1068        qp->qplib_qp.mtu = qp1_qp->mtu;
1069
1070        qp->qplib_qp.sq_hdr_buf_size = 0;
1071        qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1072        qp->qplib_qp.dpi = &rdev->dpi_privileged;
1073
1074        rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1075        if (rc)
1076                goto fail;
1077
1078        spin_lock_init(&qp->sq_lock);
1079        INIT_LIST_HEAD(&qp->list);
1080        mutex_lock(&rdev->qp_lock);
1081        list_add_tail(&qp->list, &rdev->qp_list);
1082        atomic_inc(&rdev->qp_count);
1083        mutex_unlock(&rdev->qp_lock);
1084        return qp;
1085fail:
1086        kfree(qp);
1087        return NULL;
1088}
1089
1090static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,
1091                                struct ib_qp_init_attr *init_attr)
1092{
1093        struct bnxt_qplib_dev_attr *dev_attr;
1094        struct bnxt_qplib_qp *qplqp;
1095        struct bnxt_re_dev *rdev;
1096        struct bnxt_qplib_q *rq;
1097        int entries;
1098
1099        rdev = qp->rdev;
1100        qplqp = &qp->qplib_qp;
1101        rq = &qplqp->rq;
1102        dev_attr = &rdev->dev_attr;
1103
1104        if (init_attr->srq) {
1105                struct bnxt_re_srq *srq;
1106
1107                srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq);
1108                qplqp->srq = &srq->qplib_srq;
1109                rq->max_wqe = 0;
1110        } else {
1111                rq->max_sge = init_attr->cap.max_recv_sge;
1112                if (rq->max_sge > dev_attr->max_qp_sges)
1113                        rq->max_sge = dev_attr->max_qp_sges;
1114                init_attr->cap.max_recv_sge = rq->max_sge;
1115                rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge,
1116                                                       dev_attr->max_qp_sges);
1117                /* Allocate 1 more than what's provided so posting max doesn't
1118                 * mean empty.
1119                 */
1120                entries = roundup_pow_of_two(init_attr->cap.max_recv_wr + 1);
1121                rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1122                rq->q_full_delta = 0;
1123                rq->sg_info.pgsize = PAGE_SIZE;
1124                rq->sg_info.pgshft = PAGE_SHIFT;
1125        }
1126
1127        return 0;
1128}
1129
1130static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)
1131{
1132        struct bnxt_qplib_dev_attr *dev_attr;
1133        struct bnxt_qplib_qp *qplqp;
1134        struct bnxt_re_dev *rdev;
1135
1136        rdev = qp->rdev;
1137        qplqp = &qp->qplib_qp;
1138        dev_attr = &rdev->dev_attr;
1139
1140        if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {
1141                qplqp->rq.max_sge = dev_attr->max_qp_sges;
1142                if (qplqp->rq.max_sge > dev_attr->max_qp_sges)
1143                        qplqp->rq.max_sge = dev_attr->max_qp_sges;
1144                qplqp->rq.max_sge = 6;
1145        }
1146}
1147
1148static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,
1149                                struct ib_qp_init_attr *init_attr,
1150                                struct ib_udata *udata)
1151{
1152        struct bnxt_qplib_dev_attr *dev_attr;
1153        struct bnxt_qplib_qp *qplqp;
1154        struct bnxt_re_dev *rdev;
1155        struct bnxt_qplib_q *sq;
1156        int entries;
1157        int diff;
1158        int rc;
1159
1160        rdev = qp->rdev;
1161        qplqp = &qp->qplib_qp;
1162        sq = &qplqp->sq;
1163        dev_attr = &rdev->dev_attr;
1164
1165        sq->max_sge = init_attr->cap.max_send_sge;
1166        if (sq->max_sge > dev_attr->max_qp_sges) {
1167                sq->max_sge = dev_attr->max_qp_sges;
1168                init_attr->cap.max_send_sge = sq->max_sge;
1169        }
1170
1171        rc = bnxt_re_setup_swqe_size(qp, init_attr);
1172        if (rc)
1173                return rc;
1174
1175        entries = init_attr->cap.max_send_wr;
1176        /* Allocate 128 + 1 more than what's provided */
1177        diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ?
1178                0 : BNXT_QPLIB_RESERVED_QP_WRS;
1179        entries = roundup_pow_of_two(entries + diff + 1);
1180        sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1);
1181        sq->q_full_delta = diff + 1;
1182        /*
1183         * Reserving one slot for Phantom WQE. Application can
1184         * post one extra entry in this case. But allowing this to avoid
1185         * unexpected Queue full condition
1186         */
1187        qplqp->sq.q_full_delta -= 1;
1188        qplqp->sq.sg_info.pgsize = PAGE_SIZE;
1189        qplqp->sq.sg_info.pgshft = PAGE_SHIFT;
1190
1191        return 0;
1192}
1193
1194static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,
1195                                       struct ib_qp_init_attr *init_attr)
1196{
1197        struct bnxt_qplib_dev_attr *dev_attr;
1198        struct bnxt_qplib_qp *qplqp;
1199        struct bnxt_re_dev *rdev;
1200        int entries;
1201
1202        rdev = qp->rdev;
1203        qplqp = &qp->qplib_qp;
1204        dev_attr = &rdev->dev_attr;
1205
1206        if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {
1207                entries = roundup_pow_of_two(init_attr->cap.max_send_wr + 1);
1208                qplqp->sq.max_wqe = min_t(u32, entries,
1209                                          dev_attr->max_qp_wqes + 1);
1210                qplqp->sq.q_full_delta = qplqp->sq.max_wqe -
1211                        init_attr->cap.max_send_wr;
1212                qplqp->sq.max_sge++; /* Need one extra sge to put UD header */
1213                if (qplqp->sq.max_sge > dev_attr->max_qp_sges)
1214                        qplqp->sq.max_sge = dev_attr->max_qp_sges;
1215        }
1216}
1217
1218static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev,
1219                                struct ib_qp_init_attr *init_attr)
1220{
1221        struct bnxt_qplib_chip_ctx *chip_ctx;
1222        int qptype;
1223
1224        chip_ctx = rdev->chip_ctx;
1225
1226        qptype = __from_ib_qp_type(init_attr->qp_type);
1227        if (qptype == IB_QPT_MAX) {
1228                ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype);
1229                qptype = -EOPNOTSUPP;
1230                goto out;
1231        }
1232
1233        if (bnxt_qplib_is_chip_gen_p5(chip_ctx) &&
1234            init_attr->qp_type == IB_QPT_GSI)
1235                qptype = CMDQ_CREATE_QP_TYPE_GSI;
1236out:
1237        return qptype;
1238}
1239
1240static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1241                                struct ib_qp_init_attr *init_attr,
1242                                struct ib_udata *udata)
1243{
1244        struct bnxt_qplib_dev_attr *dev_attr;
1245        struct bnxt_qplib_qp *qplqp;
1246        struct bnxt_re_dev *rdev;
1247        struct bnxt_re_cq *cq;
1248        int rc = 0, qptype;
1249
1250        rdev = qp->rdev;
1251        qplqp = &qp->qplib_qp;
1252        dev_attr = &rdev->dev_attr;
1253
1254        /* Setup misc params */
1255        ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr);
1256        qplqp->pd = &pd->qplib_pd;
1257        qplqp->qp_handle = (u64)qplqp;
1258        qplqp->max_inline_data = init_attr->cap.max_inline_data;
1259        qplqp->sig_type = ((init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ?
1260                            true : false);
1261        qptype = bnxt_re_init_qp_type(rdev, init_attr);
1262        if (qptype < 0) {
1263                rc = qptype;
1264                goto out;
1265        }
1266        qplqp->type = (u8)qptype;
1267        qplqp->wqe_mode = rdev->chip_ctx->modes.wqe_mode;
1268
1269        if (init_attr->qp_type == IB_QPT_RC) {
1270                qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom;
1271                qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1272        }
1273        qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1274        qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */
1275        if (init_attr->create_flags) {
1276                ibdev_dbg(&rdev->ibdev,
1277                          "QP create flags 0x%x not supported",
1278                          init_attr->create_flags);
1279                return -EOPNOTSUPP;
1280        }
1281
1282        /* Setup CQs */
1283        if (init_attr->send_cq) {
1284                cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq);
1285                qplqp->scq = &cq->qplib_cq;
1286                qp->scq = cq;
1287        }
1288
1289        if (init_attr->recv_cq) {
1290                cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq);
1291                qplqp->rcq = &cq->qplib_cq;
1292                qp->rcq = cq;
1293        }
1294
1295        /* Setup RQ/SRQ */
1296        rc = bnxt_re_init_rq_attr(qp, init_attr);
1297        if (rc)
1298                goto out;
1299        if (init_attr->qp_type == IB_QPT_GSI)
1300                bnxt_re_adjust_gsi_rq_attr(qp);
1301
1302        /* Setup SQ */
1303        rc = bnxt_re_init_sq_attr(qp, init_attr, udata);
1304        if (rc)
1305                goto out;
1306        if (init_attr->qp_type == IB_QPT_GSI)
1307                bnxt_re_adjust_gsi_sq_attr(qp, init_attr);
1308
1309        if (udata) /* This will update DPI and qp_handle */
1310                rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
1311out:
1312        return rc;
1313}
1314
1315static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp,
1316                                     struct bnxt_re_pd *pd)
1317{
1318        struct bnxt_re_sqp_entries *sqp_tbl;
1319        struct bnxt_re_dev *rdev;
1320        struct bnxt_re_qp *sqp;
1321        struct bnxt_re_ah *sah;
1322        int rc = 0;
1323
1324        rdev = qp->rdev;
1325        /* Create a shadow QP to handle the QP1 traffic */
1326        sqp_tbl = kcalloc(BNXT_RE_MAX_GSI_SQP_ENTRIES, sizeof(*sqp_tbl),
1327                          GFP_KERNEL);
1328        if (!sqp_tbl)
1329                return -ENOMEM;
1330        rdev->gsi_ctx.sqp_tbl = sqp_tbl;
1331
1332        sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp);
1333        if (!sqp) {
1334                rc = -ENODEV;
1335                ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1");
1336                goto out;
1337        }
1338        rdev->gsi_ctx.gsi_sqp = sqp;
1339
1340        sqp->rcq = qp->rcq;
1341        sqp->scq = qp->scq;
1342        sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1343                                          &qp->qplib_qp);
1344        if (!sah) {
1345                bnxt_qplib_destroy_qp(&rdev->qplib_res,
1346                                      &sqp->qplib_qp);
1347                rc = -ENODEV;
1348                ibdev_err(&rdev->ibdev,
1349                          "Failed to create AH entry for ShadowQP");
1350                goto out;
1351        }
1352        rdev->gsi_ctx.gsi_sah = sah;
1353
1354        return 0;
1355out:
1356        kfree(sqp_tbl);
1357        return rc;
1358}
1359
1360static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1361                                 struct ib_qp_init_attr *init_attr)
1362{
1363        struct bnxt_re_dev *rdev;
1364        struct bnxt_qplib_qp *qplqp;
1365        int rc = 0;
1366
1367        rdev = qp->rdev;
1368        qplqp = &qp->qplib_qp;
1369
1370        qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1371        qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1372
1373        rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp);
1374        if (rc) {
1375                ibdev_err(&rdev->ibdev, "create HW QP1 failed!");
1376                goto out;
1377        }
1378
1379        rc = bnxt_re_create_shadow_gsi(qp, pd);
1380out:
1381        return rc;
1382}
1383
1384static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev,
1385                                   struct ib_qp_init_attr *init_attr,
1386                                   struct bnxt_qplib_dev_attr *dev_attr)
1387{
1388        bool rc = true;
1389
1390        if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes ||
1391            init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes ||
1392            init_attr->cap.max_send_sge > dev_attr->max_qp_sges ||
1393            init_attr->cap.max_recv_sge > dev_attr->max_qp_sges ||
1394            init_attr->cap.max_inline_data > dev_attr->max_inline_data) {
1395                ibdev_err(&rdev->ibdev,
1396                          "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x",
1397                          init_attr->cap.max_send_wr, dev_attr->max_qp_wqes,
1398                          init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes,
1399                          init_attr->cap.max_send_sge, dev_attr->max_qp_sges,
1400                          init_attr->cap.max_recv_sge, dev_attr->max_qp_sges,
1401                          init_attr->cap.max_inline_data,
1402                          dev_attr->max_inline_data);
1403                rc = false;
1404        }
1405        return rc;
1406}
1407
1408int bnxt_re_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *qp_init_attr,
1409                      struct ib_udata *udata)
1410{
1411        struct ib_pd *ib_pd = ib_qp->pd;
1412        struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1413        struct bnxt_re_dev *rdev = pd->rdev;
1414        struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1415        struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1416        int rc;
1417
1418        rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr);
1419        if (!rc) {
1420                rc = -EINVAL;
1421                goto fail;
1422        }
1423
1424        qp->rdev = rdev;
1425        rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, udata);
1426        if (rc)
1427                goto fail;
1428
1429        if (qp_init_attr->qp_type == IB_QPT_GSI &&
1430            !(bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))) {
1431                rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);
1432                if (rc == -ENODEV)
1433                        goto qp_destroy;
1434                if (rc)
1435                        goto fail;
1436        } else {
1437                rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1438                if (rc) {
1439                        ibdev_err(&rdev->ibdev, "Failed to create HW QP");
1440                        goto free_umem;
1441                }
1442                if (udata) {
1443                        struct bnxt_re_qp_resp resp;
1444
1445                        resp.qpid = qp->qplib_qp.id;
1446                        resp.rsvd = 0;
1447                        rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1448                        if (rc) {
1449                                ibdev_err(&rdev->ibdev, "Failed to copy QP udata");
1450                                goto qp_destroy;
1451                        }
1452                }
1453        }
1454
1455        qp->ib_qp.qp_num = qp->qplib_qp.id;
1456        if (qp_init_attr->qp_type == IB_QPT_GSI)
1457                rdev->gsi_ctx.gsi_qp = qp;
1458        spin_lock_init(&qp->sq_lock);
1459        spin_lock_init(&qp->rq_lock);
1460        INIT_LIST_HEAD(&qp->list);
1461        mutex_lock(&rdev->qp_lock);
1462        list_add_tail(&qp->list, &rdev->qp_list);
1463        mutex_unlock(&rdev->qp_lock);
1464        atomic_inc(&rdev->qp_count);
1465
1466        return 0;
1467qp_destroy:
1468        bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1469free_umem:
1470        ib_umem_release(qp->rumem);
1471        ib_umem_release(qp->sumem);
1472fail:
1473        return rc;
1474}
1475
1476static u8 __from_ib_qp_state(enum ib_qp_state state)
1477{
1478        switch (state) {
1479        case IB_QPS_RESET:
1480                return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1481        case IB_QPS_INIT:
1482                return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1483        case IB_QPS_RTR:
1484                return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1485        case IB_QPS_RTS:
1486                return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1487        case IB_QPS_SQD:
1488                return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1489        case IB_QPS_SQE:
1490                return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1491        case IB_QPS_ERR:
1492        default:
1493                return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1494        }
1495}
1496
1497static enum ib_qp_state __to_ib_qp_state(u8 state)
1498{
1499        switch (state) {
1500        case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1501                return IB_QPS_RESET;
1502        case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1503                return IB_QPS_INIT;
1504        case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1505                return IB_QPS_RTR;
1506        case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1507                return IB_QPS_RTS;
1508        case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1509                return IB_QPS_SQD;
1510        case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1511                return IB_QPS_SQE;
1512        case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1513        default:
1514                return IB_QPS_ERR;
1515        }
1516}
1517
1518static u32 __from_ib_mtu(enum ib_mtu mtu)
1519{
1520        switch (mtu) {
1521        case IB_MTU_256:
1522                return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1523        case IB_MTU_512:
1524                return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1525        case IB_MTU_1024:
1526                return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1527        case IB_MTU_2048:
1528                return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1529        case IB_MTU_4096:
1530                return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1531        default:
1532                return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1533        }
1534}
1535
1536static enum ib_mtu __to_ib_mtu(u32 mtu)
1537{
1538        switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1539        case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1540                return IB_MTU_256;
1541        case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1542                return IB_MTU_512;
1543        case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1544                return IB_MTU_1024;
1545        case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1546                return IB_MTU_2048;
1547        case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1548                return IB_MTU_4096;
1549        default:
1550                return IB_MTU_2048;
1551        }
1552}
1553
1554/* Shared Receive Queues */
1555int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata)
1556{
1557        struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1558                                               ib_srq);
1559        struct bnxt_re_dev *rdev = srq->rdev;
1560        struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1561        struct bnxt_qplib_nq *nq = NULL;
1562
1563        if (qplib_srq->cq)
1564                nq = qplib_srq->cq->nq;
1565        bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1566        ib_umem_release(srq->umem);
1567        atomic_dec(&rdev->srq_count);
1568        if (nq)
1569                nq->budget--;
1570        return 0;
1571}
1572
1573static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1574                                 struct bnxt_re_pd *pd,
1575                                 struct bnxt_re_srq *srq,
1576                                 struct ib_udata *udata)
1577{
1578        struct bnxt_re_srq_req ureq;
1579        struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1580        struct ib_umem *umem;
1581        int bytes = 0;
1582        struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
1583                udata, struct bnxt_re_ucontext, ib_uctx);
1584
1585        if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1586                return -EFAULT;
1587
1588        bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size);
1589        bytes = PAGE_ALIGN(bytes);
1590        umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes,
1591                           IB_ACCESS_LOCAL_WRITE);
1592        if (IS_ERR(umem))
1593                return PTR_ERR(umem);
1594
1595        srq->umem = umem;
1596        qplib_srq->sg_info.umem = umem;
1597        qplib_srq->sg_info.pgsize = PAGE_SIZE;
1598        qplib_srq->sg_info.pgshft = PAGE_SHIFT;
1599        qplib_srq->srq_handle = ureq.srq_handle;
1600        qplib_srq->dpi = &cntx->dpi;
1601
1602        return 0;
1603}
1604
1605int bnxt_re_create_srq(struct ib_srq *ib_srq,
1606                       struct ib_srq_init_attr *srq_init_attr,
1607                       struct ib_udata *udata)
1608{
1609        struct bnxt_qplib_dev_attr *dev_attr;
1610        struct bnxt_qplib_nq *nq = NULL;
1611        struct bnxt_re_dev *rdev;
1612        struct bnxt_re_srq *srq;
1613        struct bnxt_re_pd *pd;
1614        struct ib_pd *ib_pd;
1615        int rc, entries;
1616
1617        ib_pd = ib_srq->pd;
1618        pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1619        rdev = pd->rdev;
1620        dev_attr = &rdev->dev_attr;
1621        srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1622
1623        if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1624                ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded");
1625                rc = -EINVAL;
1626                goto exit;
1627        }
1628
1629        if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1630                rc = -EOPNOTSUPP;
1631                goto exit;
1632        }
1633
1634        srq->rdev = rdev;
1635        srq->qplib_srq.pd = &pd->qplib_pd;
1636        srq->qplib_srq.dpi = &rdev->dpi_privileged;
1637        /* Allocate 1 more than what's provided so posting max doesn't
1638         * mean empty
1639         */
1640        entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1);
1641        if (entries > dev_attr->max_srq_wqes + 1)
1642                entries = dev_attr->max_srq_wqes + 1;
1643        srq->qplib_srq.max_wqe = entries;
1644
1645        srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1646         /* 128 byte wqe size for SRQ . So use max sges */
1647        srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges);
1648        srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1649        srq->srq_limit = srq_init_attr->attr.srq_limit;
1650        srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id;
1651        nq = &rdev->nq[0];
1652
1653        if (udata) {
1654                rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1655                if (rc)
1656                        goto fail;
1657        }
1658
1659        rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1660        if (rc) {
1661                ibdev_err(&rdev->ibdev, "Create HW SRQ failed!");
1662                goto fail;
1663        }
1664
1665        if (udata) {
1666                struct bnxt_re_srq_resp resp;
1667
1668                resp.srqid = srq->qplib_srq.id;
1669                rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1670                if (rc) {
1671                        ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!");
1672                        bnxt_qplib_destroy_srq(&rdev->qplib_res,
1673                                               &srq->qplib_srq);
1674                        goto fail;
1675                }
1676        }
1677        if (nq)
1678                nq->budget++;
1679        atomic_inc(&rdev->srq_count);
1680        spin_lock_init(&srq->lock);
1681
1682        return 0;
1683
1684fail:
1685        ib_umem_release(srq->umem);
1686exit:
1687        return rc;
1688}
1689
1690int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1691                       enum ib_srq_attr_mask srq_attr_mask,
1692                       struct ib_udata *udata)
1693{
1694        struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1695                                               ib_srq);
1696        struct bnxt_re_dev *rdev = srq->rdev;
1697        int rc;
1698
1699        switch (srq_attr_mask) {
1700        case IB_SRQ_MAX_WR:
1701                /* SRQ resize is not supported */
1702                break;
1703        case IB_SRQ_LIMIT:
1704                /* Change the SRQ threshold */
1705                if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1706                        return -EINVAL;
1707
1708                srq->qplib_srq.threshold = srq_attr->srq_limit;
1709                rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq);
1710                if (rc) {
1711                        ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!");
1712                        return rc;
1713                }
1714                /* On success, update the shadow */
1715                srq->srq_limit = srq_attr->srq_limit;
1716                /* No need to Build and send response back to udata */
1717                break;
1718        default:
1719                ibdev_err(&rdev->ibdev,
1720                          "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
1721                return -EINVAL;
1722        }
1723        return 0;
1724}
1725
1726int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
1727{
1728        struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1729                                               ib_srq);
1730        struct bnxt_re_srq tsrq;
1731        struct bnxt_re_dev *rdev = srq->rdev;
1732        int rc;
1733
1734        /* Get live SRQ attr */
1735        tsrq.qplib_srq.id = srq->qplib_srq.id;
1736        rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
1737        if (rc) {
1738                ibdev_err(&rdev->ibdev, "Query HW SRQ failed!");
1739                return rc;
1740        }
1741        srq_attr->max_wr = srq->qplib_srq.max_wqe;
1742        srq_attr->max_sge = srq->qplib_srq.max_sge;
1743        srq_attr->srq_limit = tsrq.qplib_srq.threshold;
1744
1745        return 0;
1746}
1747
1748int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
1749                          const struct ib_recv_wr **bad_wr)
1750{
1751        struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1752                                               ib_srq);
1753        struct bnxt_qplib_swqe wqe;
1754        unsigned long flags;
1755        int rc = 0;
1756
1757        spin_lock_irqsave(&srq->lock, flags);
1758        while (wr) {
1759                /* Transcribe each ib_recv_wr to qplib_swqe */
1760                wqe.num_sge = wr->num_sge;
1761                bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
1762                wqe.wr_id = wr->wr_id;
1763                wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
1764
1765                rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
1766                if (rc) {
1767                        *bad_wr = wr;
1768                        break;
1769                }
1770                wr = wr->next;
1771        }
1772        spin_unlock_irqrestore(&srq->lock, flags);
1773
1774        return rc;
1775}
1776static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1777                                    struct bnxt_re_qp *qp1_qp,
1778                                    int qp_attr_mask)
1779{
1780        struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp;
1781        int rc = 0;
1782
1783        if (qp_attr_mask & IB_QP_STATE) {
1784                qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1785                qp->qplib_qp.state = qp1_qp->qplib_qp.state;
1786        }
1787        if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1788                qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1789                qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
1790        }
1791
1792        if (qp_attr_mask & IB_QP_QKEY) {
1793                qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1794                /* Using a Random  QKEY */
1795                qp->qplib_qp.qkey = 0x81818181;
1796        }
1797        if (qp_attr_mask & IB_QP_SQ_PSN) {
1798                qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1799                qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
1800        }
1801
1802        rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1803        if (rc)
1804                ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1");
1805        return rc;
1806}
1807
1808int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1809                      int qp_attr_mask, struct ib_udata *udata)
1810{
1811        struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1812        struct bnxt_re_dev *rdev = qp->rdev;
1813        struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1814        enum ib_qp_state curr_qp_state, new_qp_state;
1815        int rc, entries;
1816        unsigned int flags;
1817        u8 nw_type;
1818
1819        if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
1820                return -EOPNOTSUPP;
1821
1822        qp->qplib_qp.modify_flags = 0;
1823        if (qp_attr_mask & IB_QP_STATE) {
1824                curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
1825                new_qp_state = qp_attr->qp_state;
1826                if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
1827                                        ib_qp->qp_type, qp_attr_mask)) {
1828                        ibdev_err(&rdev->ibdev,
1829                                  "Invalid attribute mask: %#x specified ",
1830                                  qp_attr_mask);
1831                        ibdev_err(&rdev->ibdev,
1832                                  "for qpn: %#x type: %#x",
1833                                  ib_qp->qp_num, ib_qp->qp_type);
1834                        ibdev_err(&rdev->ibdev,
1835                                  "curr_qp_state=0x%x, new_qp_state=0x%x\n",
1836                                  curr_qp_state, new_qp_state);
1837                        return -EINVAL;
1838                }
1839                qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1840                qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
1841
1842                if (!qp->sumem &&
1843                    qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1844                        ibdev_dbg(&rdev->ibdev,
1845                                  "Move QP = %p to flush list\n", qp);
1846                        flags = bnxt_re_lock_cqs(qp);
1847                        bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1848                        bnxt_re_unlock_cqs(qp, flags);
1849                }
1850                if (!qp->sumem &&
1851                    qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
1852                        ibdev_dbg(&rdev->ibdev,
1853                                  "Move QP = %p out of flush list\n", qp);
1854                        flags = bnxt_re_lock_cqs(qp);
1855                        bnxt_qplib_clean_qp(&qp->qplib_qp);
1856                        bnxt_re_unlock_cqs(qp, flags);
1857                }
1858        }
1859        if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
1860                qp->qplib_qp.modify_flags |=
1861                                CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
1862                qp->qplib_qp.en_sqd_async_notify = true;
1863        }
1864        if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
1865                qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
1866                qp->qplib_qp.access =
1867                        __from_ib_access_flags(qp_attr->qp_access_flags);
1868                /* LOCAL_WRITE access must be set to allow RC receive */
1869                qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1870                /* Temp: Set all params on QP as of now */
1871                qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
1872                qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
1873        }
1874        if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1875                qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1876                qp->qplib_qp.pkey_index = qp_attr->pkey_index;
1877        }
1878        if (qp_attr_mask & IB_QP_QKEY) {
1879                qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1880                qp->qplib_qp.qkey = qp_attr->qkey;
1881        }
1882        if (qp_attr_mask & IB_QP_AV) {
1883                const struct ib_global_route *grh =
1884                        rdma_ah_read_grh(&qp_attr->ah_attr);
1885                const struct ib_gid_attr *sgid_attr;
1886                struct bnxt_re_gid_ctx *ctx;
1887
1888                qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
1889                                     CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
1890                                     CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
1891                                     CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
1892                                     CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
1893                                     CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
1894                                     CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
1895                memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
1896                       sizeof(qp->qplib_qp.ah.dgid.data));
1897                qp->qplib_qp.ah.flow_label = grh->flow_label;
1898                sgid_attr = grh->sgid_attr;
1899                /* Get the HW context of the GID. The reference
1900                 * of GID table entry is already taken by the caller.
1901                 */
1902                ctx = rdma_read_gid_hw_context(sgid_attr);
1903                qp->qplib_qp.ah.sgid_index = ctx->idx;
1904                qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
1905                qp->qplib_qp.ah.hop_limit = grh->hop_limit;
1906                qp->qplib_qp.ah.traffic_class = grh->traffic_class;
1907                qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
1908                ether_addr_copy(qp->qplib_qp.ah.dmac,
1909                                qp_attr->ah_attr.roce.dmac);
1910
1911                rc = rdma_read_gid_l2_fields(sgid_attr, NULL,
1912                                             &qp->qplib_qp.smac[0]);
1913                if (rc)
1914                        return rc;
1915
1916                nw_type = rdma_gid_attr_network_type(sgid_attr);
1917                switch (nw_type) {
1918                case RDMA_NETWORK_IPV4:
1919                        qp->qplib_qp.nw_type =
1920                                CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
1921                        break;
1922                case RDMA_NETWORK_IPV6:
1923                        qp->qplib_qp.nw_type =
1924                                CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
1925                        break;
1926                default:
1927                        qp->qplib_qp.nw_type =
1928                                CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
1929                        break;
1930                }
1931        }
1932
1933        if (qp_attr_mask & IB_QP_PATH_MTU) {
1934                qp->qplib_qp.modify_flags |=
1935                                CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1936                qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
1937                qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
1938        } else if (qp_attr->qp_state == IB_QPS_RTR) {
1939                qp->qplib_qp.modify_flags |=
1940                        CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1941                qp->qplib_qp.path_mtu =
1942                        __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
1943                qp->qplib_qp.mtu =
1944                        ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1945        }
1946
1947        if (qp_attr_mask & IB_QP_TIMEOUT) {
1948                qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
1949                qp->qplib_qp.timeout = qp_attr->timeout;
1950        }
1951        if (qp_attr_mask & IB_QP_RETRY_CNT) {
1952                qp->qplib_qp.modify_flags |=
1953                                CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
1954                qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
1955        }
1956        if (qp_attr_mask & IB_QP_RNR_RETRY) {
1957                qp->qplib_qp.modify_flags |=
1958                                CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
1959                qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
1960        }
1961        if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
1962                qp->qplib_qp.modify_flags |=
1963                                CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
1964                qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
1965        }
1966        if (qp_attr_mask & IB_QP_RQ_PSN) {
1967                qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
1968                qp->qplib_qp.rq.psn = qp_attr->rq_psn;
1969        }
1970        if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1971                qp->qplib_qp.modify_flags |=
1972                                CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
1973                /* Cap the max_rd_atomic to device max */
1974                qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
1975                                                   dev_attr->max_qp_rd_atom);
1976        }
1977        if (qp_attr_mask & IB_QP_SQ_PSN) {
1978                qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1979                qp->qplib_qp.sq.psn = qp_attr->sq_psn;
1980        }
1981        if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1982                if (qp_attr->max_dest_rd_atomic >
1983                    dev_attr->max_qp_init_rd_atom) {
1984                        ibdev_err(&rdev->ibdev,
1985                                  "max_dest_rd_atomic requested%d is > dev_max%d",
1986                                  qp_attr->max_dest_rd_atomic,
1987                                  dev_attr->max_qp_init_rd_atom);
1988                        return -EINVAL;
1989                }
1990
1991                qp->qplib_qp.modify_flags |=
1992                                CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
1993                qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
1994        }
1995        if (qp_attr_mask & IB_QP_CAP) {
1996                qp->qplib_qp.modify_flags |=
1997                                CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
1998                                CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
1999                                CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
2000                                CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
2001                                CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
2002                if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
2003                    (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
2004                    (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
2005                    (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
2006                    (qp_attr->cap.max_inline_data >=
2007                                                dev_attr->max_inline_data)) {
2008                        ibdev_err(&rdev->ibdev,
2009                                  "Create QP failed - max exceeded");
2010                        return -EINVAL;
2011                }
2012                entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
2013                qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
2014                                                dev_attr->max_qp_wqes + 1);
2015                qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
2016                                                qp_attr->cap.max_send_wr;
2017                /*
2018                 * Reserving one slot for Phantom WQE. Some application can
2019                 * post one extra entry in this case. Allowing this to avoid
2020                 * unexpected Queue full condition
2021                 */
2022                qp->qplib_qp.sq.q_full_delta -= 1;
2023                qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
2024                if (qp->qplib_qp.rq.max_wqe) {
2025                        entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
2026                        qp->qplib_qp.rq.max_wqe =
2027                                min_t(u32, entries, dev_attr->max_qp_wqes + 1);
2028                        qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
2029                                                       qp_attr->cap.max_recv_wr;
2030                        qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
2031                } else {
2032                        /* SRQ was used prior, just ignore the RQ caps */
2033                }
2034        }
2035        if (qp_attr_mask & IB_QP_DEST_QPN) {
2036                qp->qplib_qp.modify_flags |=
2037                                CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
2038                qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
2039        }
2040        rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2041        if (rc) {
2042                ibdev_err(&rdev->ibdev, "Failed to modify HW QP");
2043                return rc;
2044        }
2045        if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
2046                rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
2047        return rc;
2048}
2049
2050int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2051                     int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
2052{
2053        struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2054        struct bnxt_re_dev *rdev = qp->rdev;
2055        struct bnxt_qplib_qp *qplib_qp;
2056        int rc;
2057
2058        qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
2059        if (!qplib_qp)
2060                return -ENOMEM;
2061
2062        qplib_qp->id = qp->qplib_qp.id;
2063        qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
2064
2065        rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
2066        if (rc) {
2067                ibdev_err(&rdev->ibdev, "Failed to query HW QP");
2068                goto out;
2069        }
2070        qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
2071        qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state);
2072        qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
2073        qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
2074        qp_attr->pkey_index = qplib_qp->pkey_index;
2075        qp_attr->qkey = qplib_qp->qkey;
2076        qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2077        rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
2078                        qplib_qp->ah.host_sgid_index,
2079                        qplib_qp->ah.hop_limit,
2080                        qplib_qp->ah.traffic_class);
2081        rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
2082        rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
2083        ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
2084        qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
2085        qp_attr->timeout = qplib_qp->timeout;
2086        qp_attr->retry_cnt = qplib_qp->retry_cnt;
2087        qp_attr->rnr_retry = qplib_qp->rnr_retry;
2088        qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
2089        qp_attr->rq_psn = qplib_qp->rq.psn;
2090        qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
2091        qp_attr->sq_psn = qplib_qp->sq.psn;
2092        qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
2093        qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
2094                                                         IB_SIGNAL_REQ_WR;
2095        qp_attr->dest_qp_num = qplib_qp->dest_qpn;
2096
2097        qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
2098        qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
2099        qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
2100        qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
2101        qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
2102        qp_init_attr->cap = qp_attr->cap;
2103
2104out:
2105        kfree(qplib_qp);
2106        return rc;
2107}
2108
2109/* Routine for sending QP1 packets for RoCE V1 an V2
2110 */
2111static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
2112                                     const struct ib_send_wr *wr,
2113                                     struct bnxt_qplib_swqe *wqe,
2114                                     int payload_size)
2115{
2116        struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
2117                                             ib_ah);
2118        struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
2119        const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
2120        struct bnxt_qplib_sge sge;
2121        u8 nw_type;
2122        u16 ether_type;
2123        union ib_gid dgid;
2124        bool is_eth = false;
2125        bool is_vlan = false;
2126        bool is_grh = false;
2127        bool is_udp = false;
2128        u8 ip_version = 0;
2129        u16 vlan_id = 0xFFFF;
2130        void *buf;
2131        int i, rc = 0;
2132
2133        memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
2134
2135        rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL);
2136        if (rc)
2137                return rc;
2138
2139        /* Get network header type for this GID */
2140        nw_type = rdma_gid_attr_network_type(sgid_attr);
2141        switch (nw_type) {
2142        case RDMA_NETWORK_IPV4:
2143                nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
2144                break;
2145        case RDMA_NETWORK_IPV6:
2146                nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
2147                break;
2148        default:
2149                nw_type = BNXT_RE_ROCE_V1_PACKET;
2150                break;
2151        }
2152        memcpy(&dgid.raw, &qplib_ah->dgid, 16);
2153        is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2154        if (is_udp) {
2155                if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
2156                        ip_version = 4;
2157                        ether_type = ETH_P_IP;
2158                } else {
2159                        ip_version = 6;
2160                        ether_type = ETH_P_IPV6;
2161                }
2162                is_grh = false;
2163        } else {
2164                ether_type = ETH_P_IBOE;
2165                is_grh = true;
2166        }
2167
2168        is_eth = true;
2169        is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
2170
2171        ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
2172                          ip_version, is_udp, 0, &qp->qp1_hdr);
2173
2174        /* ETH */
2175        ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
2176        ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
2177
2178        /* For vlan, check the sgid for vlan existence */
2179
2180        if (!is_vlan) {
2181                qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
2182        } else {
2183                qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
2184                qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
2185        }
2186
2187        if (is_grh || (ip_version == 6)) {
2188                memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
2189                       sizeof(sgid_attr->gid));
2190                memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
2191                       sizeof(sgid_attr->gid));
2192                qp->qp1_hdr.grh.hop_limit     = qplib_ah->hop_limit;
2193        }
2194
2195        if (ip_version == 4) {
2196                qp->qp1_hdr.ip4.tos = 0;
2197                qp->qp1_hdr.ip4.id = 0;
2198                qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
2199                qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
2200
2201                memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
2202                memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
2203                qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
2204        }
2205
2206        if (is_udp) {
2207                qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
2208                qp->qp1_hdr.udp.sport = htons(0x8CD1);
2209                qp->qp1_hdr.udp.csum = 0;
2210        }
2211
2212        /* BTH */
2213        if (wr->opcode == IB_WR_SEND_WITH_IMM) {
2214                qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2215                qp->qp1_hdr.immediate_present = 1;
2216        } else {
2217                qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2218        }
2219        if (wr->send_flags & IB_SEND_SOLICITED)
2220                qp->qp1_hdr.bth.solicited_event = 1;
2221        /* pad_count */
2222        qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
2223
2224        /* P_key for QP1 is for all members */
2225        qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
2226        qp->qp1_hdr.bth.destination_qpn = IB_QP1;
2227        qp->qp1_hdr.bth.ack_req = 0;
2228        qp->send_psn++;
2229        qp->send_psn &= BTH_PSN_MASK;
2230        qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
2231        /* DETH */
2232        /* Use the priviledged Q_Key for QP1 */
2233        qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
2234        qp->qp1_hdr.deth.source_qpn = IB_QP1;
2235
2236        /* Pack the QP1 to the transmit buffer */
2237        buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
2238        if (buf) {
2239                ib_ud_header_pack(&qp->qp1_hdr, buf);
2240                for (i = wqe->num_sge; i; i--) {
2241                        wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
2242                        wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
2243                        wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
2244                }
2245
2246                /*
2247                 * Max Header buf size for IPV6 RoCE V2 is 86,
2248                 * which is same as the QP1 SQ header buffer.
2249                 * Header buf size for IPV4 RoCE V2 can be 66.
2250                 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2251                 * Subtract 20 bytes from QP1 SQ header buf size
2252                 */
2253                if (is_udp && ip_version == 4)
2254                        sge.size -= 20;
2255                /*
2256                 * Max Header buf size for RoCE V1 is 78.
2257                 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2258                 * Subtract 8 bytes from QP1 SQ header buf size
2259                 */
2260                if (!is_udp)
2261                        sge.size -= 8;
2262
2263                /* Subtract 4 bytes for non vlan packets */
2264                if (!is_vlan)
2265                        sge.size -= 4;
2266
2267                wqe->sg_list[0].addr = sge.addr;
2268                wqe->sg_list[0].lkey = sge.lkey;
2269                wqe->sg_list[0].size = sge.size;
2270                wqe->num_sge++;
2271
2272        } else {
2273                ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!");
2274                rc = -ENOMEM;
2275        }
2276        return rc;
2277}
2278
2279/* For the MAD layer, it only provides the recv SGE the size of
2280 * ib_grh + MAD datagram.  No Ethernet headers, Ethertype, BTH, DETH,
2281 * nor RoCE iCRC.  The Cu+ solution must provide buffer for the entire
2282 * receive packet (334 bytes) with no VLAN and then copy the GRH
2283 * and the MAD datagram out to the provided SGE.
2284 */
2285static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2286                                            const struct ib_recv_wr *wr,
2287                                            struct bnxt_qplib_swqe *wqe,
2288                                            int payload_size)
2289{
2290        struct bnxt_re_sqp_entries *sqp_entry;
2291        struct bnxt_qplib_sge ref, sge;
2292        struct bnxt_re_dev *rdev;
2293        u32 rq_prod_index;
2294
2295        rdev = qp->rdev;
2296
2297        rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2298
2299        if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2300                return -ENOMEM;
2301
2302        /* Create 1 SGE to receive the entire
2303         * ethernet packet
2304         */
2305        /* Save the reference from ULP */
2306        ref.addr = wqe->sg_list[0].addr;
2307        ref.lkey = wqe->sg_list[0].lkey;
2308        ref.size = wqe->sg_list[0].size;
2309
2310        sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index];
2311
2312        /* SGE 1 */
2313        wqe->sg_list[0].addr = sge.addr;
2314        wqe->sg_list[0].lkey = sge.lkey;
2315        wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2316        sge.size -= wqe->sg_list[0].size;
2317
2318        sqp_entry->sge.addr = ref.addr;
2319        sqp_entry->sge.lkey = ref.lkey;
2320        sqp_entry->sge.size = ref.size;
2321        /* Store the wrid for reporting completion */
2322        sqp_entry->wrid = wqe->wr_id;
2323        /* change the wqe->wrid to table index */
2324        wqe->wr_id = rq_prod_index;
2325        return 0;
2326}
2327
2328static int is_ud_qp(struct bnxt_re_qp *qp)
2329{
2330        return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
2331                qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
2332}
2333
2334static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2335                                  const struct ib_send_wr *wr,
2336                                  struct bnxt_qplib_swqe *wqe)
2337{
2338        struct bnxt_re_ah *ah = NULL;
2339
2340        if (is_ud_qp(qp)) {
2341                ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2342                wqe->send.q_key = ud_wr(wr)->remote_qkey;
2343                wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2344                wqe->send.avid = ah->qplib_ah.id;
2345        }
2346        switch (wr->opcode) {
2347        case IB_WR_SEND:
2348                wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2349                break;
2350        case IB_WR_SEND_WITH_IMM:
2351                wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2352                wqe->send.imm_data = wr->ex.imm_data;
2353                break;
2354        case IB_WR_SEND_WITH_INV:
2355                wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2356                wqe->send.inv_key = wr->ex.invalidate_rkey;
2357                break;
2358        default:
2359                return -EINVAL;
2360        }
2361        if (wr->send_flags & IB_SEND_SIGNALED)
2362                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2363        if (wr->send_flags & IB_SEND_FENCE)
2364                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2365        if (wr->send_flags & IB_SEND_SOLICITED)
2366                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2367        if (wr->send_flags & IB_SEND_INLINE)
2368                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2369
2370        return 0;
2371}
2372
2373static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2374                                  struct bnxt_qplib_swqe *wqe)
2375{
2376        switch (wr->opcode) {
2377        case IB_WR_RDMA_WRITE:
2378                wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2379                break;
2380        case IB_WR_RDMA_WRITE_WITH_IMM:
2381                wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2382                wqe->rdma.imm_data = wr->ex.imm_data;
2383                break;
2384        case IB_WR_RDMA_READ:
2385                wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2386                wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2387                break;
2388        default:
2389                return -EINVAL;
2390        }
2391        wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2392        wqe->rdma.r_key = rdma_wr(wr)->rkey;
2393        if (wr->send_flags & IB_SEND_SIGNALED)
2394                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2395        if (wr->send_flags & IB_SEND_FENCE)
2396                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2397        if (wr->send_flags & IB_SEND_SOLICITED)
2398                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2399        if (wr->send_flags & IB_SEND_INLINE)
2400                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2401
2402        return 0;
2403}
2404
2405static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2406                                    struct bnxt_qplib_swqe *wqe)
2407{
2408        switch (wr->opcode) {
2409        case IB_WR_ATOMIC_CMP_AND_SWP:
2410                wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2411                wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2412                wqe->atomic.swap_data = atomic_wr(wr)->swap;
2413                break;
2414        case IB_WR_ATOMIC_FETCH_AND_ADD:
2415                wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2416                wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2417                break;
2418        default:
2419                return -EINVAL;
2420        }
2421        wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2422        wqe->atomic.r_key = atomic_wr(wr)->rkey;
2423        if (wr->send_flags & IB_SEND_SIGNALED)
2424                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2425        if (wr->send_flags & IB_SEND_FENCE)
2426                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2427        if (wr->send_flags & IB_SEND_SOLICITED)
2428                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2429        return 0;
2430}
2431
2432static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2433                                 struct bnxt_qplib_swqe *wqe)
2434{
2435        wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2436        wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2437
2438        /* Need unconditional fence for local invalidate
2439         * opcode to work as expected.
2440         */
2441        wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2442
2443        if (wr->send_flags & IB_SEND_SIGNALED)
2444                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2445        if (wr->send_flags & IB_SEND_SOLICITED)
2446                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2447
2448        return 0;
2449}
2450
2451static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2452                                 struct bnxt_qplib_swqe *wqe)
2453{
2454        struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2455        struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2456        int access = wr->access;
2457
2458        wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2459        wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2460        wqe->frmr.page_list = mr->pages;
2461        wqe->frmr.page_list_len = mr->npages;
2462        wqe->frmr.levels = qplib_frpl->hwq.level;
2463        wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2464
2465        /* Need unconditional fence for reg_mr
2466         * opcode to function as expected.
2467         */
2468
2469        wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2470
2471        if (wr->wr.send_flags & IB_SEND_SIGNALED)
2472                wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2473
2474        if (access & IB_ACCESS_LOCAL_WRITE)
2475                wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2476        if (access & IB_ACCESS_REMOTE_READ)
2477                wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2478        if (access & IB_ACCESS_REMOTE_WRITE)
2479                wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2480        if (access & IB_ACCESS_REMOTE_ATOMIC)
2481                wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2482        if (access & IB_ACCESS_MW_BIND)
2483                wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2484
2485        wqe->frmr.l_key = wr->key;
2486        wqe->frmr.length = wr->mr->length;
2487        wqe->frmr.pbl_pg_sz_log = ilog2(PAGE_SIZE >> PAGE_SHIFT_4K);
2488        wqe->frmr.pg_sz_log = ilog2(wr->mr->page_size >> PAGE_SHIFT_4K);
2489        wqe->frmr.va = wr->mr->iova;
2490        return 0;
2491}
2492
2493static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2494                                    const struct ib_send_wr *wr,
2495                                    struct bnxt_qplib_swqe *wqe)
2496{
2497        /*  Copy the inline data to the data  field */
2498        u8 *in_data;
2499        u32 i, sge_len;
2500        void *sge_addr;
2501
2502        in_data = wqe->inline_data;
2503        for (i = 0; i < wr->num_sge; i++) {
2504                sge_addr = (void *)(unsigned long)
2505                                wr->sg_list[i].addr;
2506                sge_len = wr->sg_list[i].length;
2507
2508                if ((sge_len + wqe->inline_len) >
2509                    BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2510                        ibdev_err(&rdev->ibdev,
2511                                  "Inline data size requested > supported value");
2512                        return -EINVAL;
2513                }
2514                sge_len = wr->sg_list[i].length;
2515
2516                memcpy(in_data, sge_addr, sge_len);
2517                in_data += wr->sg_list[i].length;
2518                wqe->inline_len += wr->sg_list[i].length;
2519        }
2520        return wqe->inline_len;
2521}
2522
2523static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2524                                   const struct ib_send_wr *wr,
2525                                   struct bnxt_qplib_swqe *wqe)
2526{
2527        int payload_sz = 0;
2528
2529        if (wr->send_flags & IB_SEND_INLINE)
2530                payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2531        else
2532                payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2533                                               wqe->num_sge);
2534
2535        return payload_sz;
2536}
2537
2538static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2539{
2540        if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2541             qp->ib_qp.qp_type == IB_QPT_GSI ||
2542             qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2543             qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2544                int qp_attr_mask;
2545                struct ib_qp_attr qp_attr;
2546
2547                qp_attr_mask = IB_QP_STATE;
2548                qp_attr.qp_state = IB_QPS_RTS;
2549                bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2550                qp->qplib_qp.wqe_cnt = 0;
2551        }
2552}
2553
2554static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2555                                       struct bnxt_re_qp *qp,
2556                                       const struct ib_send_wr *wr)
2557{
2558        int rc = 0, payload_sz = 0;
2559        unsigned long flags;
2560
2561        spin_lock_irqsave(&qp->sq_lock, flags);
2562        while (wr) {
2563                struct bnxt_qplib_swqe wqe = {};
2564
2565                /* Common */
2566                wqe.num_sge = wr->num_sge;
2567                if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2568                        ibdev_err(&rdev->ibdev,
2569                                  "Limit exceeded for Send SGEs");
2570                        rc = -EINVAL;
2571                        goto bad;
2572                }
2573
2574                payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2575                if (payload_sz < 0) {
2576                        rc = -EINVAL;
2577                        goto bad;
2578                }
2579                wqe.wr_id = wr->wr_id;
2580
2581                wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2582
2583                rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2584                if (!rc)
2585                        rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2586bad:
2587                if (rc) {
2588                        ibdev_err(&rdev->ibdev,
2589                                  "Post send failed opcode = %#x rc = %d",
2590                                  wr->opcode, rc);
2591                        break;
2592                }
2593                wr = wr->next;
2594        }
2595        bnxt_qplib_post_send_db(&qp->qplib_qp);
2596        bnxt_ud_qp_hw_stall_workaround(qp);
2597        spin_unlock_irqrestore(&qp->sq_lock, flags);
2598        return rc;
2599}
2600
2601int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2602                      const struct ib_send_wr **bad_wr)
2603{
2604        struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2605        struct bnxt_qplib_swqe wqe;
2606        int rc = 0, payload_sz = 0;
2607        unsigned long flags;
2608
2609        spin_lock_irqsave(&qp->sq_lock, flags);
2610        while (wr) {
2611                /* House keeping */
2612                memset(&wqe, 0, sizeof(wqe));
2613
2614                /* Common */
2615                wqe.num_sge = wr->num_sge;
2616                if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2617                        ibdev_err(&qp->rdev->ibdev,
2618                                  "Limit exceeded for Send SGEs");
2619                        rc = -EINVAL;
2620                        goto bad;
2621                }
2622
2623                payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2624                if (payload_sz < 0) {
2625                        rc = -EINVAL;
2626                        goto bad;
2627                }
2628                wqe.wr_id = wr->wr_id;
2629
2630                switch (wr->opcode) {
2631                case IB_WR_SEND:
2632                case IB_WR_SEND_WITH_IMM:
2633                        if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
2634                                rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2635                                                               payload_sz);
2636                                if (rc)
2637                                        goto bad;
2638                                wqe.rawqp1.lflags |=
2639                                        SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2640                        }
2641                        switch (wr->send_flags) {
2642                        case IB_SEND_IP_CSUM:
2643                                wqe.rawqp1.lflags |=
2644                                        SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2645                                break;
2646                        default:
2647                                break;
2648                        }
2649                        fallthrough;
2650                case IB_WR_SEND_WITH_INV:
2651                        rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2652                        break;
2653                case IB_WR_RDMA_WRITE:
2654                case IB_WR_RDMA_WRITE_WITH_IMM:
2655                case IB_WR_RDMA_READ:
2656                        rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2657                        break;
2658                case IB_WR_ATOMIC_CMP_AND_SWP:
2659                case IB_WR_ATOMIC_FETCH_AND_ADD:
2660                        rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2661                        break;
2662                case IB_WR_RDMA_READ_WITH_INV:
2663                        ibdev_err(&qp->rdev->ibdev,
2664                                  "RDMA Read with Invalidate is not supported");
2665                        rc = -EINVAL;
2666                        goto bad;
2667                case IB_WR_LOCAL_INV:
2668                        rc = bnxt_re_build_inv_wqe(wr, &wqe);
2669                        break;
2670                case IB_WR_REG_MR:
2671                        rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2672                        break;
2673                default:
2674                        /* Unsupported WRs */
2675                        ibdev_err(&qp->rdev->ibdev,
2676                                  "WR (%#x) is not supported", wr->opcode);
2677                        rc = -EINVAL;
2678                        goto bad;
2679                }
2680                if (!rc)
2681                        rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2682bad:
2683                if (rc) {
2684                        ibdev_err(&qp->rdev->ibdev,
2685                                  "post_send failed op:%#x qps = %#x rc = %d\n",
2686                                  wr->opcode, qp->qplib_qp.state, rc);
2687                        *bad_wr = wr;
2688                        break;
2689                }
2690                wr = wr->next;
2691        }
2692        bnxt_qplib_post_send_db(&qp->qplib_qp);
2693        bnxt_ud_qp_hw_stall_workaround(qp);
2694        spin_unlock_irqrestore(&qp->sq_lock, flags);
2695
2696        return rc;
2697}
2698
2699static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2700                                       struct bnxt_re_qp *qp,
2701                                       const struct ib_recv_wr *wr)
2702{
2703        struct bnxt_qplib_swqe wqe;
2704        int rc = 0;
2705
2706        memset(&wqe, 0, sizeof(wqe));
2707        while (wr) {
2708                /* House keeping */
2709                memset(&wqe, 0, sizeof(wqe));
2710
2711                /* Common */
2712                wqe.num_sge = wr->num_sge;
2713                if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2714                        ibdev_err(&rdev->ibdev,
2715                                  "Limit exceeded for Receive SGEs");
2716                        rc = -EINVAL;
2717                        break;
2718                }
2719                bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2720                wqe.wr_id = wr->wr_id;
2721                wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2722
2723                rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2724                if (rc)
2725                        break;
2726
2727                wr = wr->next;
2728        }
2729        if (!rc)
2730                bnxt_qplib_post_recv_db(&qp->qplib_qp);
2731        return rc;
2732}
2733
2734int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
2735                      const struct ib_recv_wr **bad_wr)
2736{
2737        struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2738        struct bnxt_qplib_swqe wqe;
2739        int rc = 0, payload_sz = 0;
2740        unsigned long flags;
2741        u32 count = 0;
2742
2743        spin_lock_irqsave(&qp->rq_lock, flags);
2744        while (wr) {
2745                /* House keeping */
2746                memset(&wqe, 0, sizeof(wqe));
2747
2748                /* Common */
2749                wqe.num_sge = wr->num_sge;
2750                if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2751                        ibdev_err(&qp->rdev->ibdev,
2752                                  "Limit exceeded for Receive SGEs");
2753                        rc = -EINVAL;
2754                        *bad_wr = wr;
2755                        break;
2756                }
2757
2758                payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2759                                               wr->num_sge);
2760                wqe.wr_id = wr->wr_id;
2761                wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2762
2763                if (ib_qp->qp_type == IB_QPT_GSI &&
2764                    qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
2765                        rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2766                                                              payload_sz);
2767                if (!rc)
2768                        rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2769                if (rc) {
2770                        *bad_wr = wr;
2771                        break;
2772                }
2773
2774                /* Ring DB if the RQEs posted reaches a threshold value */
2775                if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
2776                        bnxt_qplib_post_recv_db(&qp->qplib_qp);
2777                        count = 0;
2778                }
2779
2780                wr = wr->next;
2781        }
2782
2783        if (count)
2784                bnxt_qplib_post_recv_db(&qp->qplib_qp);
2785
2786        spin_unlock_irqrestore(&qp->rq_lock, flags);
2787
2788        return rc;
2789}
2790
2791/* Completion Queues */
2792int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
2793{
2794        struct bnxt_re_cq *cq;
2795        struct bnxt_qplib_nq *nq;
2796        struct bnxt_re_dev *rdev;
2797
2798        cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2799        rdev = cq->rdev;
2800        nq = cq->qplib_cq.nq;
2801
2802        bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2803        ib_umem_release(cq->umem);
2804
2805        atomic_dec(&rdev->cq_count);
2806        nq->budget--;
2807        kfree(cq->cql);
2808        return 0;
2809}
2810
2811int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
2812                      struct ib_udata *udata)
2813{
2814        struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);
2815        struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2816        struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
2817        int rc, entries;
2818        int cqe = attr->cqe;
2819        struct bnxt_qplib_nq *nq = NULL;
2820        unsigned int nq_alloc_cnt;
2821
2822        if (attr->flags)
2823                return -EOPNOTSUPP;
2824
2825        /* Validate CQ fields */
2826        if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
2827                ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded");
2828                return -EINVAL;
2829        }
2830
2831        cq->rdev = rdev;
2832        cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
2833
2834        entries = roundup_pow_of_two(cqe + 1);
2835        if (entries > dev_attr->max_cq_wqes + 1)
2836                entries = dev_attr->max_cq_wqes + 1;
2837
2838        cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
2839        cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
2840        if (udata) {
2841                struct bnxt_re_cq_req req;
2842                struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
2843                        udata, struct bnxt_re_ucontext, ib_uctx);
2844                if (ib_copy_from_udata(&req, udata, sizeof(req))) {
2845                        rc = -EFAULT;
2846                        goto fail;
2847                }
2848
2849                cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va,
2850                                       entries * sizeof(struct cq_base),
2851                                       IB_ACCESS_LOCAL_WRITE);
2852                if (IS_ERR(cq->umem)) {
2853                        rc = PTR_ERR(cq->umem);
2854                        goto fail;
2855                }
2856                cq->qplib_cq.sg_info.umem = cq->umem;
2857                cq->qplib_cq.dpi = &uctx->dpi;
2858        } else {
2859                cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
2860                cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
2861                                  GFP_KERNEL);
2862                if (!cq->cql) {
2863                        rc = -ENOMEM;
2864                        goto fail;
2865                }
2866
2867                cq->qplib_cq.dpi = &rdev->dpi_privileged;
2868        }
2869        /*
2870         * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a
2871         * used for getting the NQ index.
2872         */
2873        nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt);
2874        nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)];
2875        cq->qplib_cq.max_wqe = entries;
2876        cq->qplib_cq.cnq_hw_ring_id = nq->ring_id;
2877        cq->qplib_cq.nq = nq;
2878
2879        rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
2880        if (rc) {
2881                ibdev_err(&rdev->ibdev, "Failed to create HW CQ");
2882                goto fail;
2883        }
2884
2885        cq->ib_cq.cqe = entries;
2886        cq->cq_period = cq->qplib_cq.period;
2887        nq->budget++;
2888
2889        atomic_inc(&rdev->cq_count);
2890        spin_lock_init(&cq->cq_lock);
2891
2892        if (udata) {
2893                struct bnxt_re_cq_resp resp;
2894
2895                resp.cqid = cq->qplib_cq.id;
2896                resp.tail = cq->qplib_cq.hwq.cons;
2897                resp.phase = cq->qplib_cq.period;
2898                resp.rsvd = 0;
2899                rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
2900                if (rc) {
2901                        ibdev_err(&rdev->ibdev, "Failed to copy CQ udata");
2902                        bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2903                        goto c2fail;
2904                }
2905        }
2906
2907        return 0;
2908
2909c2fail:
2910        ib_umem_release(cq->umem);
2911fail:
2912        kfree(cq->cql);
2913        return rc;
2914}
2915
2916static u8 __req_to_ib_wc_status(u8 qstatus)
2917{
2918        switch (qstatus) {
2919        case CQ_REQ_STATUS_OK:
2920                return IB_WC_SUCCESS;
2921        case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
2922                return IB_WC_BAD_RESP_ERR;
2923        case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
2924                return IB_WC_LOC_LEN_ERR;
2925        case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
2926                return IB_WC_LOC_QP_OP_ERR;
2927        case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
2928                return IB_WC_LOC_PROT_ERR;
2929        case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
2930                return IB_WC_GENERAL_ERR;
2931        case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
2932                return IB_WC_REM_INV_REQ_ERR;
2933        case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
2934                return IB_WC_REM_ACCESS_ERR;
2935        case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
2936                return IB_WC_REM_OP_ERR;
2937        case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
2938                return IB_WC_RNR_RETRY_EXC_ERR;
2939        case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
2940                return IB_WC_RETRY_EXC_ERR;
2941        case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
2942                return IB_WC_WR_FLUSH_ERR;
2943        default:
2944                return IB_WC_GENERAL_ERR;
2945        }
2946        return 0;
2947}
2948
2949static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
2950{
2951        switch (qstatus) {
2952        case CQ_RES_RAWETH_QP1_STATUS_OK:
2953                return IB_WC_SUCCESS;
2954        case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
2955                return IB_WC_LOC_ACCESS_ERR;
2956        case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
2957                return IB_WC_LOC_LEN_ERR;
2958        case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
2959                return IB_WC_LOC_PROT_ERR;
2960        case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
2961                return IB_WC_LOC_QP_OP_ERR;
2962        case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
2963                return IB_WC_GENERAL_ERR;
2964        case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
2965                return IB_WC_WR_FLUSH_ERR;
2966        case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
2967                return IB_WC_WR_FLUSH_ERR;
2968        default:
2969                return IB_WC_GENERAL_ERR;
2970        }
2971}
2972
2973static u8 __rc_to_ib_wc_status(u8 qstatus)
2974{
2975        switch (qstatus) {
2976        case CQ_RES_RC_STATUS_OK:
2977                return IB_WC_SUCCESS;
2978        case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
2979                return IB_WC_LOC_ACCESS_ERR;
2980        case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
2981                return IB_WC_LOC_LEN_ERR;
2982        case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
2983                return IB_WC_LOC_PROT_ERR;
2984        case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
2985                return IB_WC_LOC_QP_OP_ERR;
2986        case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
2987                return IB_WC_GENERAL_ERR;
2988        case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
2989                return IB_WC_REM_INV_REQ_ERR;
2990        case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
2991                return IB_WC_WR_FLUSH_ERR;
2992        case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
2993                return IB_WC_WR_FLUSH_ERR;
2994        default:
2995                return IB_WC_GENERAL_ERR;
2996        }
2997}
2998
2999static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
3000{
3001        switch (cqe->type) {
3002        case BNXT_QPLIB_SWQE_TYPE_SEND:
3003                wc->opcode = IB_WC_SEND;
3004                break;
3005        case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
3006                wc->opcode = IB_WC_SEND;
3007                wc->wc_flags |= IB_WC_WITH_IMM;
3008                break;
3009        case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
3010                wc->opcode = IB_WC_SEND;
3011                wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3012                break;
3013        case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
3014                wc->opcode = IB_WC_RDMA_WRITE;
3015                break;
3016        case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
3017                wc->opcode = IB_WC_RDMA_WRITE;
3018                wc->wc_flags |= IB_WC_WITH_IMM;
3019                break;
3020        case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
3021                wc->opcode = IB_WC_RDMA_READ;
3022                break;
3023        case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
3024                wc->opcode = IB_WC_COMP_SWAP;
3025                break;
3026        case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
3027                wc->opcode = IB_WC_FETCH_ADD;
3028                break;
3029        case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
3030                wc->opcode = IB_WC_LOCAL_INV;
3031                break;
3032        case BNXT_QPLIB_SWQE_TYPE_REG_MR:
3033                wc->opcode = IB_WC_REG_MR;
3034                break;
3035        default:
3036                wc->opcode = IB_WC_SEND;
3037                break;
3038        }
3039
3040        wc->status = __req_to_ib_wc_status(cqe->status);
3041}
3042
3043static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
3044                                     u16 raweth_qp1_flags2)
3045{
3046        bool is_ipv6 = false, is_ipv4 = false;
3047
3048        /* raweth_qp1_flags Bit 9-6 indicates itype */
3049        if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3050            != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3051                return -1;
3052
3053        if (raweth_qp1_flags2 &
3054            CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
3055            raweth_qp1_flags2 &
3056            CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
3057                /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
3058                (raweth_qp1_flags2 &
3059                 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
3060                        (is_ipv6 = true) : (is_ipv4 = true);
3061                return ((is_ipv6) ?
3062                         BNXT_RE_ROCEV2_IPV6_PACKET :
3063                         BNXT_RE_ROCEV2_IPV4_PACKET);
3064        } else {
3065                return BNXT_RE_ROCE_V1_PACKET;
3066        }
3067}
3068
3069static int bnxt_re_to_ib_nw_type(int nw_type)
3070{
3071        u8 nw_hdr_type = 0xFF;
3072
3073        switch (nw_type) {
3074        case BNXT_RE_ROCE_V1_PACKET:
3075                nw_hdr_type = RDMA_NETWORK_ROCE_V1;
3076                break;
3077        case BNXT_RE_ROCEV2_IPV4_PACKET:
3078                nw_hdr_type = RDMA_NETWORK_IPV4;
3079                break;
3080        case BNXT_RE_ROCEV2_IPV6_PACKET:
3081                nw_hdr_type = RDMA_NETWORK_IPV6;
3082                break;
3083        }
3084        return nw_hdr_type;
3085}
3086
3087static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
3088                                       void *rq_hdr_buf)
3089{
3090        u8 *tmp_buf = NULL;
3091        struct ethhdr *eth_hdr;
3092        u16 eth_type;
3093        bool rc = false;
3094
3095        tmp_buf = (u8 *)rq_hdr_buf;
3096        /*
3097         * If dest mac is not same as I/F mac, this could be a
3098         * loopback address or multicast address, check whether
3099         * it is a loopback packet
3100         */
3101        if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
3102                tmp_buf += 4;
3103                /* Check the  ether type */
3104                eth_hdr = (struct ethhdr *)tmp_buf;
3105                eth_type = ntohs(eth_hdr->h_proto);
3106                switch (eth_type) {
3107                case ETH_P_IBOE:
3108                        rc = true;
3109                        break;
3110                case ETH_P_IP:
3111                case ETH_P_IPV6: {
3112                        u32 len;
3113                        struct udphdr *udp_hdr;
3114
3115                        len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
3116                                                      sizeof(struct ipv6hdr));
3117                        tmp_buf += sizeof(struct ethhdr) + len;
3118                        udp_hdr = (struct udphdr *)tmp_buf;
3119                        if (ntohs(udp_hdr->dest) ==
3120                                    ROCE_V2_UDP_DPORT)
3121                                rc = true;
3122                        break;
3123                        }
3124                default:
3125                        break;
3126                }
3127        }
3128
3129        return rc;
3130}
3131
3132static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp,
3133                                         struct bnxt_qplib_cqe *cqe)
3134{
3135        struct bnxt_re_dev *rdev = gsi_qp->rdev;
3136        struct bnxt_re_sqp_entries *sqp_entry = NULL;
3137        struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp;
3138        struct bnxt_re_ah *gsi_sah;
3139        struct ib_send_wr *swr;
3140        struct ib_ud_wr udwr;
3141        struct ib_recv_wr rwr;
3142        int pkt_type = 0;
3143        u32 tbl_idx;
3144        void *rq_hdr_buf;
3145        dma_addr_t rq_hdr_buf_map;
3146        dma_addr_t shrq_hdr_buf_map;
3147        u32 offset = 0;
3148        u32 skip_bytes = 0;
3149        struct ib_sge s_sge[2];
3150        struct ib_sge r_sge[2];
3151        int rc;
3152
3153        memset(&udwr, 0, sizeof(udwr));
3154        memset(&rwr, 0, sizeof(rwr));
3155        memset(&s_sge, 0, sizeof(s_sge));
3156        memset(&r_sge, 0, sizeof(r_sge));
3157
3158        swr = &udwr.wr;
3159        tbl_idx = cqe->wr_id;
3160
3161        rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf +
3162                        (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size);
3163        rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3164                                                          tbl_idx);
3165
3166        /* Shadow QP header buffer */
3167        shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3168                                                            tbl_idx);
3169        sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3170
3171        /* Store this cqe */
3172        memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
3173        sqp_entry->qp1_qp = gsi_qp;
3174
3175        /* Find packet type from the cqe */
3176
3177        pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
3178                                             cqe->raweth_qp1_flags2);
3179        if (pkt_type < 0) {
3180                ibdev_err(&rdev->ibdev, "Invalid packet\n");
3181                return -EINVAL;
3182        }
3183
3184        /* Adjust the offset for the user buffer and post in the rq */
3185
3186        if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
3187                offset = 20;
3188
3189        /*
3190         * QP1 loopback packet has 4 bytes of internal header before
3191         * ether header. Skip these four bytes.
3192         */
3193        if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
3194                skip_bytes = 4;
3195
3196        /* First send SGE . Skip the ether header*/
3197        s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
3198                        + skip_bytes;
3199        s_sge[0].lkey = 0xFFFFFFFF;
3200        s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
3201                                BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
3202
3203        /* Second Send SGE */
3204        s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
3205                        BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
3206        if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
3207                s_sge[1].addr += 8;
3208        s_sge[1].lkey = 0xFFFFFFFF;
3209        s_sge[1].length = 256;
3210
3211        /* First recv SGE */
3212
3213        r_sge[0].addr = shrq_hdr_buf_map;
3214        r_sge[0].lkey = 0xFFFFFFFF;
3215        r_sge[0].length = 40;
3216
3217        r_sge[1].addr = sqp_entry->sge.addr + offset;
3218        r_sge[1].lkey = sqp_entry->sge.lkey;
3219        r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
3220
3221        /* Create receive work request */
3222        rwr.num_sge = 2;
3223        rwr.sg_list = r_sge;
3224        rwr.wr_id = tbl_idx;
3225        rwr.next = NULL;
3226
3227        rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr);
3228        if (rc) {
3229                ibdev_err(&rdev->ibdev,
3230                          "Failed to post Rx buffers to shadow QP");
3231                return -ENOMEM;
3232        }
3233
3234        swr->num_sge = 2;
3235        swr->sg_list = s_sge;
3236        swr->wr_id = tbl_idx;
3237        swr->opcode = IB_WR_SEND;
3238        swr->next = NULL;
3239        gsi_sah = rdev->gsi_ctx.gsi_sah;
3240        udwr.ah = &gsi_sah->ib_ah;
3241        udwr.remote_qpn = gsi_sqp->qplib_qp.id;
3242        udwr.remote_qkey = gsi_sqp->qplib_qp.qkey;
3243
3244        /* post data received  in the send queue */
3245        rc = bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr);
3246
3247        return 0;
3248}
3249
3250static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3251                                          struct bnxt_qplib_cqe *cqe)
3252{
3253        wc->opcode = IB_WC_RECV;
3254        wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3255        wc->wc_flags |= IB_WC_GRH;
3256}
3257
3258static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev,
3259                                        u16 vlan_id)
3260{
3261        /*
3262         * Check if the vlan is configured in the host.  If not configured, it
3263         * can be a transparent VLAN. So dont report the vlan id.
3264         */
3265        if (!__vlan_find_dev_deep_rcu(rdev->netdev,
3266                                      htons(ETH_P_8021Q), vlan_id))
3267                return false;
3268        return true;
3269}
3270
3271static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3272                                u16 *vid, u8 *sl)
3273{
3274        bool ret = false;
3275        u32 metadata;
3276        u16 tpid;
3277
3278        metadata = orig_cqe->raweth_qp1_metadata;
3279        if (orig_cqe->raweth_qp1_flags2 &
3280                CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3281                tpid = ((metadata &
3282                         CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3283                         CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3284                if (tpid == ETH_P_8021Q) {
3285                        *vid = metadata &
3286                               CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3287                        *sl = (metadata &
3288                               CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3289                               CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3290                        ret = true;
3291                }
3292        }
3293
3294        return ret;
3295}
3296
3297static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3298                                      struct bnxt_qplib_cqe *cqe)
3299{
3300        wc->opcode = IB_WC_RECV;
3301        wc->status = __rc_to_ib_wc_status(cqe->status);
3302
3303        if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3304                wc->wc_flags |= IB_WC_WITH_IMM;
3305        if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3306                wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3307        if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3308            (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3309                wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3310}
3311
3312static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp,
3313                                             struct ib_wc *wc,
3314                                             struct bnxt_qplib_cqe *cqe)
3315{
3316        struct bnxt_re_dev *rdev = gsi_sqp->rdev;
3317        struct bnxt_re_qp *gsi_qp = NULL;
3318        struct bnxt_qplib_cqe *orig_cqe = NULL;
3319        struct bnxt_re_sqp_entries *sqp_entry = NULL;
3320        int nw_type;
3321        u32 tbl_idx;
3322        u16 vlan_id;
3323        u8 sl;
3324
3325        tbl_idx = cqe->wr_id;
3326
3327        sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3328        gsi_qp = sqp_entry->qp1_qp;
3329        orig_cqe = &sqp_entry->cqe;
3330
3331        wc->wr_id = sqp_entry->wrid;
3332        wc->byte_len = orig_cqe->length;
3333        wc->qp = &gsi_qp->ib_qp;
3334
3335        wc->ex.imm_data = orig_cqe->immdata;
3336        wc->src_qp = orig_cqe->src_qp;
3337        memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3338        if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3339                if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3340                        wc->vlan_id = vlan_id;
3341                        wc->sl = sl;
3342                        wc->wc_flags |= IB_WC_WITH_VLAN;
3343                }
3344        }
3345        wc->port_num = 1;
3346        wc->vendor_err = orig_cqe->status;
3347
3348        wc->opcode = IB_WC_RECV;
3349        wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3350        wc->wc_flags |= IB_WC_GRH;
3351
3352        nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3353                                            orig_cqe->raweth_qp1_flags2);
3354        if (nw_type >= 0) {
3355                wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3356                wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3357        }
3358}
3359
3360static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
3361                                      struct ib_wc *wc,
3362                                      struct bnxt_qplib_cqe *cqe)
3363{
3364        struct bnxt_re_dev *rdev;
3365        u16 vlan_id = 0;
3366        u8 nw_type;
3367
3368        rdev = qp->rdev;
3369        wc->opcode = IB_WC_RECV;
3370        wc->status = __rc_to_ib_wc_status(cqe->status);
3371
3372        if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
3373                wc->wc_flags |= IB_WC_WITH_IMM;
3374        /* report only on GSI QP for Thor */
3375        if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
3376                wc->wc_flags |= IB_WC_GRH;
3377                memcpy(wc->smac, cqe->smac, ETH_ALEN);
3378                wc->wc_flags |= IB_WC_WITH_SMAC;
3379                if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
3380                        vlan_id = (cqe->cfa_meta & 0xFFF);
3381                }
3382                /* Mark only if vlan_id is non zero */
3383                if (vlan_id && bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3384                        wc->vlan_id = vlan_id;
3385                        wc->wc_flags |= IB_WC_WITH_VLAN;
3386                }
3387                nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
3388                           CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
3389                wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3390                wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3391        }
3392
3393}
3394
3395static int send_phantom_wqe(struct bnxt_re_qp *qp)
3396{
3397        struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3398        unsigned long flags;
3399        int rc = 0;
3400
3401        spin_lock_irqsave(&qp->sq_lock, flags);
3402
3403        rc = bnxt_re_bind_fence_mw(lib_qp);
3404        if (!rc) {
3405                lib_qp->sq.phantom_wqe_cnt++;
3406                ibdev_dbg(&qp->rdev->ibdev,
3407                          "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3408                          lib_qp->id, lib_qp->sq.hwq.prod,
3409                          HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3410                          lib_qp->sq.phantom_wqe_cnt);
3411        }
3412
3413        spin_unlock_irqrestore(&qp->sq_lock, flags);
3414        return rc;
3415}
3416
3417int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3418{
3419        struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3420        struct bnxt_re_qp *qp, *sh_qp;
3421        struct bnxt_qplib_cqe *cqe;
3422        int i, ncqe, budget;
3423        struct bnxt_qplib_q *sq;
3424        struct bnxt_qplib_qp *lib_qp;
3425        u32 tbl_idx;
3426        struct bnxt_re_sqp_entries *sqp_entry = NULL;
3427        unsigned long flags;
3428
3429        spin_lock_irqsave(&cq->cq_lock, flags);
3430        budget = min_t(u32, num_entries, cq->max_cql);
3431        num_entries = budget;
3432        if (!cq->cql) {
3433                ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use");
3434                goto exit;
3435        }
3436        cqe = &cq->cql[0];
3437        while (budget) {
3438                lib_qp = NULL;
3439                ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3440                if (lib_qp) {
3441                        sq = &lib_qp->sq;
3442                        if (sq->send_phantom) {
3443                                qp = container_of(lib_qp,
3444                                                  struct bnxt_re_qp, qplib_qp);
3445                                if (send_phantom_wqe(qp) == -ENOMEM)
3446                                        ibdev_err(&cq->rdev->ibdev,
3447                                                  "Phantom failed! Scheduled to send again\n");
3448                                else
3449                                        sq->send_phantom = false;
3450                        }
3451                }
3452                if (ncqe < budget)
3453                        ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3454                                                              cqe + ncqe,
3455                                                              budget - ncqe);
3456
3457                if (!ncqe)
3458                        break;
3459
3460                for (i = 0; i < ncqe; i++, cqe++) {
3461                        /* Transcribe each qplib_wqe back to ib_wc */
3462                        memset(wc, 0, sizeof(*wc));
3463
3464                        wc->wr_id = cqe->wr_id;
3465                        wc->byte_len = cqe->length;
3466                        qp = container_of
3467                                ((struct bnxt_qplib_qp *)
3468                                 (unsigned long)(cqe->qp_handle),
3469                                 struct bnxt_re_qp, qplib_qp);
3470                        wc->qp = &qp->ib_qp;
3471                        wc->ex.imm_data = cqe->immdata;
3472                        wc->src_qp = cqe->src_qp;
3473                        memcpy(wc->smac, cqe->smac, ETH_ALEN);
3474                        wc->port_num = 1;
3475                        wc->vendor_err = cqe->status;
3476
3477                        switch (cqe->opcode) {
3478                        case CQ_BASE_CQE_TYPE_REQ:
3479                                sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3480                                if (sh_qp &&
3481                                    qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3482                                        /* Handle this completion with
3483                                         * the stored completion
3484                                         */
3485                                        memset(wc, 0, sizeof(*wc));
3486                                        continue;
3487                                }
3488                                bnxt_re_process_req_wc(wc, cqe);
3489                                break;
3490                        case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3491                                if (!cqe->status) {
3492                                        int rc = 0;
3493
3494                                        rc = bnxt_re_process_raw_qp_pkt_rx
3495                                                                (qp, cqe);
3496                                        if (!rc) {
3497                                                memset(wc, 0, sizeof(*wc));
3498                                                continue;
3499                                        }
3500                                        cqe->status = -1;
3501                                }
3502                                /* Errors need not be looped back.
3503                                 * But change the wr_id to the one
3504                                 * stored in the table
3505                                 */
3506                                tbl_idx = cqe->wr_id;
3507                                sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx];
3508                                wc->wr_id = sqp_entry->wrid;
3509                                bnxt_re_process_res_rawqp1_wc(wc, cqe);
3510                                break;
3511                        case CQ_BASE_CQE_TYPE_RES_RC:
3512                                bnxt_re_process_res_rc_wc(wc, cqe);
3513                                break;
3514                        case CQ_BASE_CQE_TYPE_RES_UD:
3515                                sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3516                                if (sh_qp &&
3517                                    qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3518                                        /* Handle this completion with
3519                                         * the stored completion
3520                                         */
3521                                        if (cqe->status) {
3522                                                continue;
3523                                        } else {
3524                                                bnxt_re_process_res_shadow_qp_wc
3525                                                                (qp, wc, cqe);
3526                                                break;
3527                                        }
3528                                }
3529                                bnxt_re_process_res_ud_wc(qp, wc, cqe);
3530                                break;
3531                        default:
3532                                ibdev_err(&cq->rdev->ibdev,
3533                                          "POLL CQ : type 0x%x not handled",
3534                                          cqe->opcode);
3535                                continue;
3536                        }
3537                        wc++;
3538                        budget--;
3539                }
3540        }
3541exit:
3542        spin_unlock_irqrestore(&cq->cq_lock, flags);
3543        return num_entries - budget;
3544}
3545
3546int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3547                          enum ib_cq_notify_flags ib_cqn_flags)
3548{
3549        struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3550        int type = 0, rc = 0;
3551        unsigned long flags;
3552
3553        spin_lock_irqsave(&cq->cq_lock, flags);
3554        /* Trigger on the very next completion */
3555        if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3556                type = DBC_DBC_TYPE_CQ_ARMALL;
3557        /* Trigger on the next solicited completion */
3558        else if (ib_cqn_flags & IB_CQ_SOLICITED)
3559                type = DBC_DBC_TYPE_CQ_ARMSE;
3560
3561        /* Poll to see if there are missed events */
3562        if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3563            !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3564                rc = 1;
3565                goto exit;
3566        }
3567        bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3568
3569exit:
3570        spin_unlock_irqrestore(&cq->cq_lock, flags);
3571        return rc;
3572}
3573
3574/* Memory Regions */
3575struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3576{
3577        struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3578        struct bnxt_re_dev *rdev = pd->rdev;
3579        struct bnxt_re_mr *mr;
3580        int rc;
3581
3582        mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3583        if (!mr)
3584                return ERR_PTR(-ENOMEM);
3585
3586        mr->rdev = rdev;
3587        mr->qplib_mr.pd = &pd->qplib_pd;
3588        mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3589        mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3590
3591        /* Allocate and register 0 as the address */
3592        rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3593        if (rc)
3594                goto fail;
3595
3596        mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3597        mr->qplib_mr.total_size = -1; /* Infinte length */
3598        rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0,
3599                               PAGE_SIZE);
3600        if (rc)
3601                goto fail_mr;
3602
3603        mr->ib_mr.lkey = mr->qplib_mr.lkey;
3604        if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3605                               IB_ACCESS_REMOTE_ATOMIC))
3606                mr->ib_mr.rkey = mr->ib_mr.lkey;
3607        atomic_inc(&rdev->mr_count);
3608
3609        return &mr->ib_mr;
3610
3611fail_mr:
3612        bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3613fail:
3614        kfree(mr);
3615        return ERR_PTR(rc);
3616}
3617
3618int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
3619{
3620        struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3621        struct bnxt_re_dev *rdev = mr->rdev;
3622        int rc;
3623
3624        rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3625        if (rc) {
3626                ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc);
3627                return rc;
3628        }
3629
3630        if (mr->pages) {
3631                rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3632                                                        &mr->qplib_frpl);
3633                kfree(mr->pages);
3634                mr->npages = 0;
3635                mr->pages = NULL;
3636        }
3637        ib_umem_release(mr->ib_umem);
3638
3639        kfree(mr);
3640        atomic_dec(&rdev->mr_count);
3641        return rc;
3642}
3643
3644static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
3645{
3646        struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3647
3648        if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
3649                return -ENOMEM;
3650
3651        mr->pages[mr->npages++] = addr;
3652        return 0;
3653}
3654
3655int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
3656                      unsigned int *sg_offset)
3657{
3658        struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3659
3660        mr->npages = 0;
3661        return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
3662}
3663
3664struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
3665                               u32 max_num_sg)
3666{
3667        struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3668        struct bnxt_re_dev *rdev = pd->rdev;
3669        struct bnxt_re_mr *mr = NULL;
3670        int rc;
3671
3672        if (type != IB_MR_TYPE_MEM_REG) {
3673                ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type);
3674                return ERR_PTR(-EINVAL);
3675        }
3676        if (max_num_sg > MAX_PBL_LVL_1_PGS)
3677                return ERR_PTR(-EINVAL);
3678
3679        mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3680        if (!mr)
3681                return ERR_PTR(-ENOMEM);
3682
3683        mr->rdev = rdev;
3684        mr->qplib_mr.pd = &pd->qplib_pd;
3685        mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
3686        mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3687
3688        rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3689        if (rc)
3690                goto bail;
3691
3692        mr->ib_mr.lkey = mr->qplib_mr.lkey;
3693        mr->ib_mr.rkey = mr->ib_mr.lkey;
3694
3695        mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
3696        if (!mr->pages) {
3697                rc = -ENOMEM;
3698                goto fail;
3699        }
3700        rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
3701                                                 &mr->qplib_frpl, max_num_sg);
3702        if (rc) {
3703                ibdev_err(&rdev->ibdev,
3704                          "Failed to allocate HW FR page list");
3705                goto fail_mr;
3706        }
3707
3708        atomic_inc(&rdev->mr_count);
3709        return &mr->ib_mr;
3710
3711fail_mr:
3712        kfree(mr->pages);
3713fail:
3714        bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3715bail:
3716        kfree(mr);
3717        return ERR_PTR(rc);
3718}
3719
3720struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
3721                               struct ib_udata *udata)
3722{
3723        struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3724        struct bnxt_re_dev *rdev = pd->rdev;
3725        struct bnxt_re_mw *mw;
3726        int rc;
3727
3728        mw = kzalloc(sizeof(*mw), GFP_KERNEL);
3729        if (!mw)
3730                return ERR_PTR(-ENOMEM);
3731        mw->rdev = rdev;
3732        mw->qplib_mw.pd = &pd->qplib_pd;
3733
3734        mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
3735                               CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
3736                               CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
3737        rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
3738        if (rc) {
3739                ibdev_err(&rdev->ibdev, "Allocate MW failed!");
3740                goto fail;
3741        }
3742        mw->ib_mw.rkey = mw->qplib_mw.rkey;
3743
3744        atomic_inc(&rdev->mw_count);
3745        return &mw->ib_mw;
3746
3747fail:
3748        kfree(mw);
3749        return ERR_PTR(rc);
3750}
3751
3752int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
3753{
3754        struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
3755        struct bnxt_re_dev *rdev = mw->rdev;
3756        int rc;
3757
3758        rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
3759        if (rc) {
3760                ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc);
3761                return rc;
3762        }
3763
3764        kfree(mw);
3765        atomic_dec(&rdev->mw_count);
3766        return rc;
3767}
3768
3769/* uverbs */
3770struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
3771                                  u64 virt_addr, int mr_access_flags,
3772                                  struct ib_udata *udata)
3773{
3774        struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3775        struct bnxt_re_dev *rdev = pd->rdev;
3776        struct bnxt_re_mr *mr;
3777        struct ib_umem *umem;
3778        unsigned long page_size;
3779        int umem_pgs, rc;
3780
3781        if (length > BNXT_RE_MAX_MR_SIZE) {
3782                ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n",
3783                          length, BNXT_RE_MAX_MR_SIZE);
3784                return ERR_PTR(-ENOMEM);
3785        }
3786
3787        mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3788        if (!mr)
3789                return ERR_PTR(-ENOMEM);
3790
3791        mr->rdev = rdev;
3792        mr->qplib_mr.pd = &pd->qplib_pd;
3793        mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3794        mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
3795
3796        rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3797        if (rc) {
3798                ibdev_err(&rdev->ibdev, "Failed to allocate MR");
3799                goto free_mr;
3800        }
3801        /* The fixed portion of the rkey is the same as the lkey */
3802        mr->ib_mr.rkey = mr->qplib_mr.rkey;
3803
3804        umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags);
3805        if (IS_ERR(umem)) {
3806                ibdev_err(&rdev->ibdev, "Failed to get umem");
3807                rc = -EFAULT;
3808                goto free_mrw;
3809        }
3810        mr->ib_umem = umem;
3811
3812        mr->qplib_mr.va = virt_addr;
3813        page_size = ib_umem_find_best_pgsz(
3814                umem, BNXT_RE_PAGE_SIZE_SUPPORTED, virt_addr);
3815        if (!page_size) {
3816                ibdev_err(&rdev->ibdev, "umem page size unsupported!");
3817                rc = -EFAULT;
3818                goto free_umem;
3819        }
3820        mr->qplib_mr.total_size = length;
3821
3822        umem_pgs = ib_umem_num_dma_blocks(umem, page_size);
3823        rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem,
3824                               umem_pgs, page_size);
3825        if (rc) {
3826                ibdev_err(&rdev->ibdev, "Failed to register user MR");
3827                goto free_umem;
3828        }
3829
3830        mr->ib_mr.lkey = mr->qplib_mr.lkey;
3831        mr->ib_mr.rkey = mr->qplib_mr.lkey;
3832        atomic_inc(&rdev->mr_count);
3833
3834        return &mr->ib_mr;
3835free_umem:
3836        ib_umem_release(umem);
3837free_mrw:
3838        bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3839free_mr:
3840        kfree(mr);
3841        return ERR_PTR(rc);
3842}
3843
3844int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)
3845{
3846        struct ib_device *ibdev = ctx->device;
3847        struct bnxt_re_ucontext *uctx =
3848                container_of(ctx, struct bnxt_re_ucontext, ib_uctx);
3849        struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
3850        struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
3851        struct bnxt_re_uctx_resp resp = {};
3852        u32 chip_met_rev_num = 0;
3853        int rc;
3854
3855        ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver);
3856
3857        if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
3858                ibdev_dbg(ibdev, " is different from the device %d ",
3859                          BNXT_RE_ABI_VERSION);
3860                return -EPERM;
3861        }
3862
3863        uctx->rdev = rdev;
3864
3865        uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
3866        if (!uctx->shpg) {
3867                rc = -ENOMEM;
3868                goto fail;
3869        }
3870        spin_lock_init(&uctx->sh_lock);
3871
3872        resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
3873        chip_met_rev_num = rdev->chip_ctx->chip_num;
3874        chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) <<
3875                             BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
3876        chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) <<
3877                             BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
3878        resp.chip_id0 = chip_met_rev_num;
3879        /*Temp, Use xa_alloc instead */
3880        resp.dev_id = rdev->en_dev->pdev->devfn;
3881        resp.max_qp = rdev->qplib_ctx.qpc_count;
3882        resp.pg_size = PAGE_SIZE;
3883        resp.cqe_sz = sizeof(struct cq_base);
3884        resp.max_cqd = dev_attr->max_cq_wqes;
3885
3886        resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE;
3887        resp.mode = rdev->chip_ctx->modes.wqe_mode;
3888
3889        rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
3890        if (rc) {
3891                ibdev_err(ibdev, "Failed to copy user context");
3892                rc = -EFAULT;
3893                goto cfail;
3894        }
3895
3896        return 0;
3897cfail:
3898        free_page((unsigned long)uctx->shpg);
3899        uctx->shpg = NULL;
3900fail:
3901        return rc;
3902}
3903
3904void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
3905{
3906        struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3907                                                   struct bnxt_re_ucontext,
3908                                                   ib_uctx);
3909
3910        struct bnxt_re_dev *rdev = uctx->rdev;
3911
3912        if (uctx->shpg)
3913                free_page((unsigned long)uctx->shpg);
3914
3915        if (uctx->dpi.dbr) {
3916                /* Free DPI only if this is the first PD allocated by the
3917                 * application and mark the context dpi as NULL
3918                 */
3919                bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
3920                                       &rdev->qplib_res.dpi_tbl, &uctx->dpi);
3921                uctx->dpi.dbr = NULL;
3922        }
3923}
3924
3925/* Helper function to mmap the virtual memory from user app */
3926int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
3927{
3928        struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3929                                                   struct bnxt_re_ucontext,
3930                                                   ib_uctx);
3931        struct bnxt_re_dev *rdev = uctx->rdev;
3932        u64 pfn;
3933
3934        if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3935                return -EINVAL;
3936
3937        if (vma->vm_pgoff) {
3938                vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3939                if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
3940                                       PAGE_SIZE, vma->vm_page_prot)) {
3941                        ibdev_err(&rdev->ibdev, "Failed to map DPI");
3942                        return -EAGAIN;
3943                }
3944        } else {
3945                pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
3946                if (remap_pfn_range(vma, vma->vm_start,
3947                                    pfn, PAGE_SIZE, vma->vm_page_prot)) {
3948                        ibdev_err(&rdev->ibdev, "Failed to map shared page");
3949                        return -EAGAIN;
3950                }
3951        }
3952
3953        return 0;
3954}
3955