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8#ifndef _ASM_X86_AMD_IOMMU_TYPES_H
9#define _ASM_X86_AMD_IOMMU_TYPES_H
10
11#include <linux/types.h>
12#include <linux/mutex.h>
13#include <linux/msi.h>
14#include <linux/list.h>
15#include <linux/spinlock.h>
16#include <linux/pci.h>
17#include <linux/irqreturn.h>
18#include <linux/io-pgtable.h>
19
20
21
22
23#define MAX_IOMMUS 32
24
25
26
27
28#define DEV_TABLE_ENTRY_SIZE 32
29#define ALIAS_TABLE_ENTRY_SIZE 2
30#define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
31
32
33#define MMIO_CAP_HDR_OFFSET 0x00
34#define MMIO_RANGE_OFFSET 0x0c
35#define MMIO_MISC_OFFSET 0x10
36
37
38#define MMIO_RANGE_LD_MASK 0xff000000
39#define MMIO_RANGE_FD_MASK 0x00ff0000
40#define MMIO_RANGE_BUS_MASK 0x0000ff00
41#define MMIO_RANGE_LD_SHIFT 24
42#define MMIO_RANGE_FD_SHIFT 16
43#define MMIO_RANGE_BUS_SHIFT 8
44#define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
45#define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
46#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
47#define MMIO_MSI_NUM(x) ((x) & 0x1f)
48
49
50#define MMIO_EXCL_ENABLE_MASK 0x01ULL
51#define MMIO_EXCL_ALLOW_MASK 0x02ULL
52
53
54#define MMIO_DEV_TABLE_OFFSET 0x0000
55#define MMIO_CMD_BUF_OFFSET 0x0008
56#define MMIO_EVT_BUF_OFFSET 0x0010
57#define MMIO_CONTROL_OFFSET 0x0018
58#define MMIO_EXCL_BASE_OFFSET 0x0020
59#define MMIO_EXCL_LIMIT_OFFSET 0x0028
60#define MMIO_EXT_FEATURES 0x0030
61#define MMIO_PPR_LOG_OFFSET 0x0038
62#define MMIO_GA_LOG_BASE_OFFSET 0x00e0
63#define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
64#define MMIO_MSI_ADDR_LO_OFFSET 0x015C
65#define MMIO_MSI_ADDR_HI_OFFSET 0x0160
66#define MMIO_MSI_DATA_OFFSET 0x0164
67#define MMIO_INTCAPXT_EVT_OFFSET 0x0170
68#define MMIO_INTCAPXT_PPR_OFFSET 0x0178
69#define MMIO_INTCAPXT_GALOG_OFFSET 0x0180
70#define MMIO_CMD_HEAD_OFFSET 0x2000
71#define MMIO_CMD_TAIL_OFFSET 0x2008
72#define MMIO_EVT_HEAD_OFFSET 0x2010
73#define MMIO_EVT_TAIL_OFFSET 0x2018
74#define MMIO_STATUS_OFFSET 0x2020
75#define MMIO_PPR_HEAD_OFFSET 0x2030
76#define MMIO_PPR_TAIL_OFFSET 0x2038
77#define MMIO_GA_HEAD_OFFSET 0x2040
78#define MMIO_GA_TAIL_OFFSET 0x2048
79#define MMIO_CNTR_CONF_OFFSET 0x4000
80#define MMIO_CNTR_REG_OFFSET 0x40000
81#define MMIO_REG_END_OFFSET 0x80000
82
83
84
85
86#define FEATURE_PREFETCH (1ULL<<0)
87#define FEATURE_PPR (1ULL<<1)
88#define FEATURE_X2APIC (1ULL<<2)
89#define FEATURE_NX (1ULL<<3)
90#define FEATURE_GT (1ULL<<4)
91#define FEATURE_IA (1ULL<<6)
92#define FEATURE_GA (1ULL<<7)
93#define FEATURE_HE (1ULL<<8)
94#define FEATURE_PC (1ULL<<9)
95#define FEATURE_GAM_VAPIC (1ULL<<21)
96#define FEATURE_EPHSUP (1ULL<<50)
97#define FEATURE_SNP (1ULL<<63)
98
99#define FEATURE_PASID_SHIFT 32
100#define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
101
102#define FEATURE_GLXVAL_SHIFT 14
103#define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT)
104
105
106
107
108
109
110#define PASID_MASK 0x0000ffff
111
112
113#define MMIO_STATUS_EVT_INT_MASK (1 << 1)
114#define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
115#define MMIO_STATUS_PPR_INT_MASK (1 << 6)
116#define MMIO_STATUS_GALOG_RUN_MASK (1 << 8)
117#define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9)
118#define MMIO_STATUS_GALOG_INT_MASK (1 << 10)
119
120
121#define EVENT_ENTRY_SIZE 0x10
122#define EVENT_TYPE_SHIFT 28
123#define EVENT_TYPE_MASK 0xf
124#define EVENT_TYPE_ILL_DEV 0x1
125#define EVENT_TYPE_IO_FAULT 0x2
126#define EVENT_TYPE_DEV_TAB_ERR 0x3
127#define EVENT_TYPE_PAGE_TAB_ERR 0x4
128#define EVENT_TYPE_ILL_CMD 0x5
129#define EVENT_TYPE_CMD_HARD_ERR 0x6
130#define EVENT_TYPE_IOTLB_INV_TO 0x7
131#define EVENT_TYPE_INV_DEV_REQ 0x8
132#define EVENT_TYPE_INV_PPR_REQ 0x9
133#define EVENT_TYPE_RMP_FAULT 0xd
134#define EVENT_TYPE_RMP_HW_ERR 0xe
135#define EVENT_DEVID_MASK 0xffff
136#define EVENT_DEVID_SHIFT 0
137#define EVENT_DOMID_MASK_LO 0xffff
138#define EVENT_DOMID_MASK_HI 0xf0000
139#define EVENT_FLAGS_MASK 0xfff
140#define EVENT_FLAGS_SHIFT 0x10
141#define EVENT_FLAG_RW 0x020
142#define EVENT_FLAG_I 0x008
143
144
145#define CONTROL_IOMMU_EN 0x00ULL
146#define CONTROL_HT_TUN_EN 0x01ULL
147#define CONTROL_EVT_LOG_EN 0x02ULL
148#define CONTROL_EVT_INT_EN 0x03ULL
149#define CONTROL_COMWAIT_EN 0x04ULL
150#define CONTROL_INV_TIMEOUT 0x05ULL
151#define CONTROL_PASSPW_EN 0x08ULL
152#define CONTROL_RESPASSPW_EN 0x09ULL
153#define CONTROL_COHERENT_EN 0x0aULL
154#define CONTROL_ISOC_EN 0x0bULL
155#define CONTROL_CMDBUF_EN 0x0cULL
156#define CONTROL_PPRLOG_EN 0x0dULL
157#define CONTROL_PPRINT_EN 0x0eULL
158#define CONTROL_PPR_EN 0x0fULL
159#define CONTROL_GT_EN 0x10ULL
160#define CONTROL_GA_EN 0x11ULL
161#define CONTROL_GAM_EN 0x19ULL
162#define CONTROL_GALOG_EN 0x1CULL
163#define CONTROL_GAINT_EN 0x1DULL
164#define CONTROL_XT_EN 0x32ULL
165#define CONTROL_INTCAPXT_EN 0x33ULL
166
167#define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
168#define CTRL_INV_TO_NONE 0
169#define CTRL_INV_TO_1MS 1
170#define CTRL_INV_TO_10MS 2
171#define CTRL_INV_TO_100MS 3
172#define CTRL_INV_TO_1S 4
173#define CTRL_INV_TO_10S 5
174#define CTRL_INV_TO_100S 6
175
176
177#define CMD_COMPL_WAIT 0x01
178#define CMD_INV_DEV_ENTRY 0x02
179#define CMD_INV_IOMMU_PAGES 0x03
180#define CMD_INV_IOTLB_PAGES 0x04
181#define CMD_INV_IRT 0x05
182#define CMD_COMPLETE_PPR 0x07
183#define CMD_INV_ALL 0x08
184
185#define CMD_COMPL_WAIT_STORE_MASK 0x01
186#define CMD_COMPL_WAIT_INT_MASK 0x02
187#define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
188#define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
189#define CMD_INV_IOMMU_PAGES_GN_MASK 0x04
190
191#define PPR_STATUS_MASK 0xf
192#define PPR_STATUS_SHIFT 12
193
194#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
195
196
197#define DEV_ENTRY_VALID 0x00
198#define DEV_ENTRY_TRANSLATION 0x01
199#define DEV_ENTRY_PPR 0x34
200#define DEV_ENTRY_IR 0x3d
201#define DEV_ENTRY_IW 0x3e
202#define DEV_ENTRY_NO_PAGE_FAULT 0x62
203#define DEV_ENTRY_EX 0x67
204#define DEV_ENTRY_SYSMGT1 0x68
205#define DEV_ENTRY_SYSMGT2 0x69
206#define DEV_ENTRY_IRQ_TBL_EN 0x80
207#define DEV_ENTRY_INIT_PASS 0xb8
208#define DEV_ENTRY_EINT_PASS 0xb9
209#define DEV_ENTRY_NMI_PASS 0xba
210#define DEV_ENTRY_LINT0_PASS 0xbe
211#define DEV_ENTRY_LINT1_PASS 0xbf
212#define DEV_ENTRY_MODE_MASK 0x07
213#define DEV_ENTRY_MODE_SHIFT 0x09
214
215#define MAX_DEV_TABLE_ENTRIES 0xffff
216
217
218#define CMD_BUFFER_SIZE 8192
219#define CMD_BUFFER_UNINITIALIZED 1
220#define CMD_BUFFER_ENTRIES 512
221#define MMIO_CMD_SIZE_SHIFT 56
222#define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
223
224
225#define EVT_BUFFER_SIZE 8192
226#define EVT_LEN_MASK (0x9ULL << 56)
227
228
229#define PPR_LOG_ENTRIES 512
230#define PPR_LOG_SIZE_SHIFT 56
231#define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT)
232#define PPR_ENTRY_SIZE 16
233#define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
234
235#define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
236#define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
237#define PPR_DEVID(x) ((x) & 0xffffULL)
238#define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
239#define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
240#define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
241#define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
242
243#define PPR_REQ_FAULT 0x01
244
245
246#define GA_LOG_ENTRIES 512
247#define GA_LOG_SIZE_SHIFT 56
248#define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT)
249#define GA_ENTRY_SIZE 8
250#define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES)
251
252#define GA_TAG(x) (u32)(x & 0xffffffffULL)
253#define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL)
254#define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
255
256#define GA_GUEST_NR 0x1
257
258#define IOMMU_IN_ADDR_BIT_SIZE 52
259#define IOMMU_OUT_ADDR_BIT_SIZE 52
260
261
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264
265
266
267
268
269#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
270
271
272#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
273#define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60)
274#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
275#define DTE_IRQ_REMAP_ENABLE 1ULL
276
277
278
279
280
281#define DTE_INTTAB_ALIGNMENT 128
282#define DTE_INTTABLEN_VALUE 9ULL
283#define DTE_INTTABLEN (DTE_INTTABLEN_VALUE << 1)
284#define DTE_INTTABLEN_MASK (0xfULL << 1)
285#define MAX_IRQS_PER_TABLE (1 << DTE_INTTABLEN_VALUE)
286
287#define PAGE_MODE_NONE 0x00
288#define PAGE_MODE_1_LEVEL 0x01
289#define PAGE_MODE_2_LEVEL 0x02
290#define PAGE_MODE_3_LEVEL 0x03
291#define PAGE_MODE_4_LEVEL 0x04
292#define PAGE_MODE_5_LEVEL 0x05
293#define PAGE_MODE_6_LEVEL 0x06
294#define PAGE_MODE_7_LEVEL 0x07
295
296#define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
297#define PM_LEVEL_SIZE(x) (((x) < 6) ? \
298 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
299 (0xffffffffffffffffULL))
300#define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
301#define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
302#define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
303 IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW)
304#define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
305
306#define PM_MAP_4k 0
307#define PM_ADDR_MASK 0x000ffffffffff000ULL
308#define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
309 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
310#define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
311
312
313
314
315
316#define PAGE_SIZE_LEVEL(pagesize) \
317 ((__ffs(pagesize) - 12) / 9)
318
319
320
321
322#define PAGE_SIZE_PTE_COUNT(pagesize) \
323 (1ULL << ((__ffs(pagesize) - 12) % 9))
324
325
326
327
328
329#define PAGE_SIZE_ALIGN(address, pagesize) \
330 ((address) & ~((pagesize) - 1))
331
332
333
334
335
336#define PAGE_SIZE_PTE(address, pagesize) \
337 (((address) | ((pagesize) - 1)) & \
338 (~(pagesize >> 1)) & PM_ADDR_MASK)
339
340
341
342
343#define PTE_PAGE_SIZE(pte) \
344 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
345
346
347
348
349#define PTE_LEVEL_PAGE_SIZE(level) \
350 (1ULL << (12 + (9 * (level))))
351
352
353
354
355#define IOMMU_PTE_PR (1ULL << 0)
356#define IOMMU_PTE_U (1ULL << 59)
357#define IOMMU_PTE_FC (1ULL << 60)
358#define IOMMU_PTE_IR (1ULL << 61)
359#define IOMMU_PTE_IW (1ULL << 62)
360
361
362
363
364#define DTE_FLAG_V (1ULL << 0)
365#define DTE_FLAG_TV (1ULL << 1)
366#define DTE_FLAG_IR (1ULL << 61)
367#define DTE_FLAG_IW (1ULL << 62)
368
369#define DTE_FLAG_IOTLB (1ULL << 32)
370#define DTE_FLAG_GV (1ULL << 55)
371#define DTE_FLAG_MASK (0x3ffULL << 32)
372#define DTE_GLX_SHIFT (56)
373#define DTE_GLX_MASK (3)
374#define DEV_DOMID_MASK 0xffffULL
375
376#define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
377#define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL)
378#define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0x1fffffULL)
379
380#define DTE_GCR3_INDEX_A 0
381#define DTE_GCR3_INDEX_B 1
382#define DTE_GCR3_INDEX_C 1
383
384#define DTE_GCR3_SHIFT_A 58
385#define DTE_GCR3_SHIFT_B 16
386#define DTE_GCR3_SHIFT_C 43
387
388#define GCR3_VALID 0x01ULL
389
390#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
391#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR)
392#define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK))
393#define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
394
395#define IOMMU_PROT_MASK 0x03
396#define IOMMU_PROT_IR 0x01
397#define IOMMU_PROT_IW 0x02
398
399#define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2)
400
401
402#define IOMMU_CAP_IOTLB 24
403#define IOMMU_CAP_NPCACHE 26
404#define IOMMU_CAP_EFR 27
405
406
407#define IOMMU_IVINFO_OFFSET 36
408#define IOMMU_IVINFO_EFRSUP BIT(0)
409
410
411#define IOMMU_FEAT_GASUP_SHIFT 6
412
413
414#define IOMMU_EFR_XTSUP_SHIFT 2
415#define IOMMU_EFR_GASUP_SHIFT 7
416#define IOMMU_EFR_MSICAPMMIOSUP_SHIFT 46
417
418#define MAX_DOMAIN_ID 65536
419
420
421#define PD_DMA_OPS_MASK (1UL << 0)
422#define PD_DEFAULT_MASK (1UL << 1)
423
424#define PD_PASSTHROUGH_MASK (1UL << 2)
425
426#define PD_IOMMUV2_MASK (1UL << 3)
427
428extern bool amd_iommu_dump;
429#define DUMP_printk(format, arg...) \
430 do { \
431 if (amd_iommu_dump) \
432 pr_info("AMD-Vi: " format, ## arg); \
433 } while(0);
434
435
436extern bool amd_iommu_np_cache;
437
438extern bool amd_iommu_iotlb_sup;
439
440struct irq_remap_table {
441 raw_spinlock_t lock;
442 unsigned min_index;
443 u32 *table;
444};
445
446extern struct irq_remap_table **irq_lookup_table;
447
448
449extern bool amd_iommu_irq_remap;
450
451
452extern struct kmem_cache *amd_iommu_irq_cache;
453
454
455
456
457#define for_each_iommu(iommu) \
458 list_for_each_entry((iommu), &amd_iommu_list, list)
459#define for_each_iommu_safe(iommu, next) \
460 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
461
462#define APERTURE_RANGE_SHIFT 27
463#define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
464#define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
465#define APERTURE_MAX_RANGES 32
466#define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
467#define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
468
469
470
471
472
473struct amd_iommu_fault {
474 u64 address;
475 u32 pasid;
476 u16 device_id;
477 u16 tag;
478 u16 flags;
479
480};
481
482
483struct iommu_domain;
484struct irq_domain;
485struct amd_irte_ops;
486
487#define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0)
488
489#define io_pgtable_to_data(x) \
490 container_of((x), struct amd_io_pgtable, iop)
491
492#define io_pgtable_ops_to_data(x) \
493 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x))
494
495#define io_pgtable_ops_to_domain(x) \
496 container_of(io_pgtable_ops_to_data(x), \
497 struct protection_domain, iop)
498
499#define io_pgtable_cfg_to_data(x) \
500 container_of((x), struct amd_io_pgtable, pgtbl_cfg)
501
502struct amd_io_pgtable {
503 struct io_pgtable_cfg pgtbl_cfg;
504 struct io_pgtable iop;
505 int mode;
506 u64 *root;
507 atomic64_t pt_root;
508};
509
510
511
512
513
514struct protection_domain {
515 struct list_head dev_list;
516 struct iommu_domain domain;
517
518 struct amd_io_pgtable iop;
519 spinlock_t lock;
520 u16 id;
521 int glx;
522 u64 *gcr3_tbl;
523 unsigned long flags;
524 unsigned dev_cnt;
525 unsigned dev_iommu[MAX_IOMMUS];
526};
527
528
529
530
531
532struct amd_iommu {
533 struct list_head list;
534
535
536 int index;
537
538
539 raw_spinlock_t lock;
540
541
542 struct pci_dev *dev;
543
544
545 struct pci_dev *root_pdev;
546
547
548 u64 mmio_phys;
549
550
551 u64 mmio_phys_end;
552
553
554 u8 __iomem *mmio_base;
555
556
557 u32 cap;
558
559
560 u8 acpi_flags;
561
562
563 u64 features;
564
565
566 bool is_iommu_v2;
567
568
569 u16 devid;
570
571
572
573
574
575
576 u16 cap_ptr;
577
578
579 u16 pci_seg;
580
581
582 u64 exclusion_start;
583
584 u64 exclusion_length;
585
586
587 u8 *cmd_buf;
588 u32 cmd_buf_head;
589 u32 cmd_buf_tail;
590
591
592 u8 *evt_buf;
593
594
595 u8 *ppr_log;
596
597
598 u8 *ga_log;
599
600
601 u8 *ga_log_tail;
602
603
604 bool int_enabled;
605
606
607 bool need_sync;
608
609
610 struct iommu_device iommu;
611
612
613
614
615
616
617
618 u32 stored_addr_lo;
619 u32 stored_addr_hi;
620
621
622
623
624
625 u32 stored_l1[6][0x12];
626
627
628 u32 stored_l2[0x83];
629
630
631 u8 max_banks;
632 u8 max_counters;
633#ifdef CONFIG_IRQ_REMAP
634 struct irq_domain *ir_domain;
635 struct irq_domain *msi_domain;
636
637 struct amd_irte_ops *irte_ops;
638#endif
639
640 u32 flags;
641 volatile u64 *cmd_sem;
642 u64 cmd_sem_val;
643
644#ifdef CONFIG_AMD_IOMMU_DEBUGFS
645
646 struct dentry *debugfs;
647#endif
648
649 struct irq_affinity_notify intcapxt_notify;
650};
651
652static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
653{
654 struct iommu_device *iommu = dev_to_iommu_device(dev);
655
656 return container_of(iommu, struct amd_iommu, iommu);
657}
658
659#define ACPIHID_UID_LEN 256
660#define ACPIHID_HID_LEN 9
661
662struct acpihid_map_entry {
663 struct list_head list;
664 u8 uid[ACPIHID_UID_LEN];
665 u8 hid[ACPIHID_HID_LEN];
666 u16 devid;
667 u16 root_devid;
668 bool cmd_line;
669 struct iommu_group *group;
670};
671
672struct devid_map {
673 struct list_head list;
674 u8 id;
675 u16 devid;
676 bool cmd_line;
677};
678
679
680
681
682struct iommu_dev_data {
683
684 spinlock_t lock;
685
686 struct list_head list;
687 struct llist_node dev_data_list;
688 struct protection_domain *domain;
689 struct pci_dev *pdev;
690 u16 devid;
691 bool iommu_v2;
692 struct {
693 bool enabled;
694 int qdep;
695 } ats;
696 bool pri_tlp;
697
698 bool use_vapic;
699 bool defer_attach;
700
701 struct ratelimit_state rs;
702};
703
704
705extern struct list_head ioapic_map;
706extern struct list_head hpet_map;
707extern struct list_head acpihid_map;
708
709
710
711
712
713extern struct list_head amd_iommu_list;
714
715
716
717
718
719extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
720
721
722
723
724struct dev_table_entry {
725 u64 data[4];
726};
727
728
729
730
731struct unity_map_entry {
732 struct list_head list;
733
734
735 u16 devid_start;
736
737 u16 devid_end;
738
739
740 u64 address_start;
741
742 u64 address_end;
743
744
745 int prot;
746};
747
748
749
750
751
752extern struct list_head amd_iommu_unity_map;
753
754
755
756
757
758
759
760
761
762extern struct dev_table_entry *amd_iommu_dev_table;
763
764
765
766
767
768extern u16 *amd_iommu_alias_table;
769
770
771
772
773extern struct amd_iommu **amd_iommu_rlookup_table;
774
775
776extern unsigned amd_iommu_aperture_order;
777
778
779extern u16 amd_iommu_last_bdf;
780
781
782extern unsigned long *amd_iommu_pd_alloc_bitmap;
783
784
785extern u32 amd_iommu_max_pasid;
786
787extern bool amd_iommu_v2_present;
788
789extern bool amd_iommu_force_isolation;
790
791
792extern int amd_iommu_max_glx_val;
793
794
795
796
797
798extern void iommu_flush_all_caches(struct amd_iommu *iommu);
799
800static inline int get_ioapic_devid(int id)
801{
802 struct devid_map *entry;
803
804 list_for_each_entry(entry, &ioapic_map, list) {
805 if (entry->id == id)
806 return entry->devid;
807 }
808
809 return -EINVAL;
810}
811
812static inline int get_hpet_devid(int id)
813{
814 struct devid_map *entry;
815
816 list_for_each_entry(entry, &hpet_map, list) {
817 if (entry->id == id)
818 return entry->devid;
819 }
820
821 return -EINVAL;
822}
823
824enum amd_iommu_intr_mode_type {
825 AMD_IOMMU_GUEST_IR_LEGACY,
826
827
828
829
830
831 AMD_IOMMU_GUEST_IR_LEGACY_GA,
832 AMD_IOMMU_GUEST_IR_VAPIC,
833};
834
835#define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \
836 x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
837
838#define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC)
839
840union irte {
841 u32 val;
842 struct {
843 u32 valid : 1,
844 no_fault : 1,
845 int_type : 3,
846 rq_eoi : 1,
847 dm : 1,
848 rsvd_1 : 1,
849 destination : 8,
850 vector : 8,
851 rsvd_2 : 8;
852 } fields;
853};
854
855#define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff)
856#define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff)
857
858union irte_ga_lo {
859 u64 val;
860
861
862 struct {
863 u64 valid : 1,
864 no_fault : 1,
865
866 int_type : 3,
867 rq_eoi : 1,
868 dm : 1,
869
870 guest_mode : 1,
871 destination : 24,
872 ga_tag : 32;
873 } fields_remap;
874
875
876 struct {
877 u64 valid : 1,
878 no_fault : 1,
879
880 ga_log_intr : 1,
881 rsvd1 : 3,
882 is_run : 1,
883
884 guest_mode : 1,
885 destination : 24,
886 ga_tag : 32;
887 } fields_vapic;
888};
889
890union irte_ga_hi {
891 u64 val;
892 struct {
893 u64 vector : 8,
894 rsvd_1 : 4,
895 ga_root_ptr : 40,
896 rsvd_2 : 4,
897 destination : 8;
898 } fields;
899};
900
901struct irte_ga {
902 union irte_ga_lo lo;
903 union irte_ga_hi hi;
904};
905
906struct irq_2_irte {
907 u16 devid;
908 u16 index;
909};
910
911struct amd_ir_data {
912 u32 cached_ga_tag;
913 struct irq_2_irte irq_2_irte;
914 struct msi_msg msi_entry;
915 void *entry;
916 void *ref;
917
918
919
920
921
922 struct irq_cfg *cfg;
923 int ga_vector;
924 int ga_root_ptr;
925 int ga_tag;
926};
927
928struct amd_irte_ops {
929 void (*prepare)(void *, u32, bool, u8, u32, int);
930 void (*activate)(void *, u16, u16);
931 void (*deactivate)(void *, u16, u16);
932 void (*set_affinity)(void *, u16, u16, u8, u32);
933 void *(*get)(struct irq_remap_table *, int);
934 void (*set_allocated)(struct irq_remap_table *, int);
935 bool (*is_allocated)(struct irq_remap_table *, int);
936 void (*clear_allocated)(struct irq_remap_table *, int);
937};
938
939#ifdef CONFIG_IRQ_REMAP
940extern struct amd_irte_ops irte_32_ops;
941extern struct amd_irte_ops irte_128_ops;
942#endif
943
944#endif
945