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42#include <linux/bitfield.h>
43#include <linux/module.h>
44#include <linux/of_irq.h>
45#include <linux/of_mdio.h>
46#include <linux/regmap.h>
47#include <linux/reset.h>
48#include <net/dsa.h>
49
50#define AR9331_SW_NAME "ar9331_switch"
51#define AR9331_SW_PORTS 6
52
53
54#define AR9331_SW_REG_PAGE 0x40000
55
56
57#define AR9331_SW_REG_GINT 0x10
58#define AR9331_SW_REG_GINT_MASK 0x14
59#define AR9331_SW_GINT_PHY_INT BIT(2)
60
61#define AR9331_SW_REG_FLOOD_MASK 0x2c
62#define AR9331_SW_FLOOD_MASK_BROAD_TO_CPU BIT(26)
63
64#define AR9331_SW_REG_GLOBAL_CTRL 0x30
65#define AR9331_SW_GLOBAL_CTRL_MFS_M GENMASK(13, 0)
66
67#define AR9331_SW_REG_MDIO_CTRL 0x98
68#define AR9331_SW_MDIO_CTRL_BUSY BIT(31)
69#define AR9331_SW_MDIO_CTRL_MASTER_EN BIT(30)
70#define AR9331_SW_MDIO_CTRL_CMD_READ BIT(27)
71#define AR9331_SW_MDIO_CTRL_PHY_ADDR_M GENMASK(25, 21)
72#define AR9331_SW_MDIO_CTRL_REG_ADDR_M GENMASK(20, 16)
73#define AR9331_SW_MDIO_CTRL_DATA_M GENMASK(16, 0)
74
75#define AR9331_SW_REG_PORT_STATUS(_port) (0x100 + (_port) * 0x100)
76
77
78
79
80#define AR9331_SW_PORT_STATUS_FLOW_LINK_EN BIT(12)
81
82
83
84
85#define AR9331_SW_PORT_STATUS_LINK_EN BIT(9)
86#define AR9331_SW_PORT_STATUS_DUPLEX_MODE BIT(6)
87#define AR9331_SW_PORT_STATUS_RX_FLOW_EN BIT(5)
88#define AR9331_SW_PORT_STATUS_TX_FLOW_EN BIT(4)
89#define AR9331_SW_PORT_STATUS_RXMAC BIT(3)
90#define AR9331_SW_PORT_STATUS_TXMAC BIT(2)
91#define AR9331_SW_PORT_STATUS_SPEED_M GENMASK(1, 0)
92#define AR9331_SW_PORT_STATUS_SPEED_1000 2
93#define AR9331_SW_PORT_STATUS_SPEED_100 1
94#define AR9331_SW_PORT_STATUS_SPEED_10 0
95
96#define AR9331_SW_PORT_STATUS_MAC_MASK \
97 (AR9331_SW_PORT_STATUS_TXMAC | AR9331_SW_PORT_STATUS_RXMAC)
98
99#define AR9331_SW_PORT_STATUS_LINK_MASK \
100 (AR9331_SW_PORT_STATUS_DUPLEX_MODE | \
101 AR9331_SW_PORT_STATUS_RX_FLOW_EN | AR9331_SW_PORT_STATUS_TX_FLOW_EN | \
102 AR9331_SW_PORT_STATUS_SPEED_M)
103
104#define AR9331_SW_REG_PORT_CTRL(_port) (0x104 + (_port) * 0x100)
105#define AR9331_SW_PORT_CTRL_HEAD_EN BIT(11)
106#define AR9331_SW_PORT_CTRL_PORT_STATE GENMASK(2, 0)
107#define AR9331_SW_PORT_CTRL_PORT_STATE_DISABLED 0
108#define AR9331_SW_PORT_CTRL_PORT_STATE_BLOCKING 1
109#define AR9331_SW_PORT_CTRL_PORT_STATE_LISTENING 2
110#define AR9331_SW_PORT_CTRL_PORT_STATE_LEARNING 3
111#define AR9331_SW_PORT_CTRL_PORT_STATE_FORWARD 4
112
113#define AR9331_SW_REG_PORT_VLAN(_port) (0x108 + (_port) * 0x100)
114#define AR9331_SW_PORT_VLAN_8021Q_MODE GENMASK(31, 30)
115#define AR9331_SW_8021Q_MODE_SECURE 3
116#define AR9331_SW_8021Q_MODE_CHECK 2
117#define AR9331_SW_8021Q_MODE_FALLBACK 1
118#define AR9331_SW_8021Q_MODE_NONE 0
119#define AR9331_SW_PORT_VLAN_PORT_VID_MEMBER GENMASK(25, 16)
120
121
122#define AR9331_MIB_COUNTER(x) (0x20000 + ((x) * 0x100))
123
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149
150#define AR9331_SW_ADDR_PAGE GENMASK(18, 9)
151
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162
163
164#define AR9331_SW_LOW_ADDR_PHY GENMASK(8, 6)
165#define AR9331_SW_LOW_ADDR_REG GENMASK(5, 1)
166
167#define AR9331_SW_MDIO_PHY_MODE_M GENMASK(4, 3)
168#define AR9331_SW_MDIO_PHY_MODE_PAGE 3
169#define AR9331_SW_MDIO_PHY_MODE_REG 2
170#define AR9331_SW_MDIO_PHY_MODE_BYPASS 0
171#define AR9331_SW_MDIO_PHY_ADDR_M GENMASK(2, 0)
172
173
174#define AR9331_SW_MDIO_POLL_SLEEP_US 1
175#define AR9331_SW_MDIO_POLL_TIMEOUT_US 20
176
177
178
179
180
181
182
183#define STATS_INTERVAL_JIFFIES (3 * HZ)
184
185struct ar9331_sw_stats_raw {
186 u32 rxbroad;
187 u32 rxpause;
188 u32 rxmulti;
189 u32 rxfcserr;
190 u32 rxalignerr;
191 u32 rxrunt;
192 u32 rxfragment;
193 u32 rx64byte;
194 u32 rx128byte;
195 u32 rx256byte;
196 u32 rx512byte;
197 u32 rx1024byte;
198 u32 rx1518byte;
199 u32 rxmaxbyte;
200 u32 rxtoolong;
201 u32 rxgoodbyte;
202 u32 rxgoodbyte_hi;
203 u32 rxbadbyte;
204 u32 rxbadbyte_hi;
205 u32 rxoverflow;
206 u32 filtered;
207 u32 txbroad;
208 u32 txpause;
209 u32 txmulti;
210 u32 txunderrun;
211 u32 tx64byte;
212 u32 tx128byte;
213 u32 tx256byte;
214 u32 tx512byte;
215 u32 tx1024byte;
216 u32 tx1518byte;
217 u32 txmaxbyte;
218 u32 txoversize;
219 u32 txbyte;
220 u32 txbyte_hi;
221 u32 txcollision;
222 u32 txabortcol;
223 u32 txmulticol;
224 u32 txsinglecol;
225 u32 txexcdefer;
226 u32 txdefer;
227 u32 txlatecol;
228};
229
230struct ar9331_sw_port {
231 int idx;
232 struct delayed_work mib_read;
233 struct rtnl_link_stats64 stats;
234 struct spinlock stats_lock;
235};
236
237struct ar9331_sw_priv {
238 struct device *dev;
239 struct dsa_switch ds;
240 struct dsa_switch_ops ops;
241 struct irq_domain *irqdomain;
242 u32 irq_mask;
243 struct mutex lock_irq;
244 struct mii_bus *mbus;
245 struct mii_bus *sbus;
246 struct regmap *regmap;
247 struct reset_control *sw_reset;
248 struct ar9331_sw_port port[AR9331_SW_PORTS];
249};
250
251static struct ar9331_sw_priv *ar9331_sw_port_to_priv(struct ar9331_sw_port *port)
252{
253 struct ar9331_sw_port *p = port - port->idx;
254
255 return (struct ar9331_sw_priv *)((void *)p -
256 offsetof(struct ar9331_sw_priv, port));
257}
258
259
260
261
262static int ar9331_sw_reset(struct ar9331_sw_priv *priv)
263{
264 int ret;
265
266 ret = reset_control_assert(priv->sw_reset);
267 if (ret)
268 goto error;
269
270
271
272
273
274
275 usleep_range(10000, 15000);
276 ret = reset_control_deassert(priv->sw_reset);
277 if (ret)
278 goto error;
279
280
281
282
283
284
285
286 return 0;
287error:
288 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
289 return ret;
290}
291
292static int ar9331_sw_mbus_write(struct mii_bus *mbus, int port, int regnum,
293 u16 data)
294{
295 struct ar9331_sw_priv *priv = mbus->priv;
296 struct regmap *regmap = priv->regmap;
297 u32 val;
298 int ret;
299
300 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
301 AR9331_SW_MDIO_CTRL_BUSY |
302 AR9331_SW_MDIO_CTRL_MASTER_EN |
303 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
304 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum) |
305 FIELD_PREP(AR9331_SW_MDIO_CTRL_DATA_M, data));
306 if (ret)
307 goto error;
308
309 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
310 !(val & AR9331_SW_MDIO_CTRL_BUSY),
311 AR9331_SW_MDIO_POLL_SLEEP_US,
312 AR9331_SW_MDIO_POLL_TIMEOUT_US);
313 if (ret)
314 goto error;
315
316 return 0;
317error:
318 dev_err_ratelimited(priv->dev, "PHY write error: %i\n", ret);
319 return ret;
320}
321
322static int ar9331_sw_mbus_read(struct mii_bus *mbus, int port, int regnum)
323{
324 struct ar9331_sw_priv *priv = mbus->priv;
325 struct regmap *regmap = priv->regmap;
326 u32 val;
327 int ret;
328
329 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL,
330 AR9331_SW_MDIO_CTRL_BUSY |
331 AR9331_SW_MDIO_CTRL_MASTER_EN |
332 AR9331_SW_MDIO_CTRL_CMD_READ |
333 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) |
334 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum));
335 if (ret)
336 goto error;
337
338 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val,
339 !(val & AR9331_SW_MDIO_CTRL_BUSY),
340 AR9331_SW_MDIO_POLL_SLEEP_US,
341 AR9331_SW_MDIO_POLL_TIMEOUT_US);
342 if (ret)
343 goto error;
344
345 ret = regmap_read(regmap, AR9331_SW_REG_MDIO_CTRL, &val);
346 if (ret)
347 goto error;
348
349 return FIELD_GET(AR9331_SW_MDIO_CTRL_DATA_M, val);
350
351error:
352 dev_err_ratelimited(priv->dev, "PHY read error: %i\n", ret);
353 return ret;
354}
355
356static int ar9331_sw_mbus_init(struct ar9331_sw_priv *priv)
357{
358 struct device *dev = priv->dev;
359 struct mii_bus *mbus;
360 struct device_node *np, *mnp;
361 int ret;
362
363 np = dev->of_node;
364
365 mbus = devm_mdiobus_alloc(dev);
366 if (!mbus)
367 return -ENOMEM;
368
369 mbus->name = np->full_name;
370 snprintf(mbus->id, MII_BUS_ID_SIZE, "%pOF", np);
371
372 mbus->read = ar9331_sw_mbus_read;
373 mbus->write = ar9331_sw_mbus_write;
374 mbus->priv = priv;
375 mbus->parent = dev;
376
377 mnp = of_get_child_by_name(np, "mdio");
378 if (!mnp)
379 return -ENODEV;
380
381 ret = of_mdiobus_register(mbus, mnp);
382 of_node_put(mnp);
383 if (ret)
384 return ret;
385
386 priv->mbus = mbus;
387
388 return 0;
389}
390
391static int ar9331_sw_setup_port(struct dsa_switch *ds, int port)
392{
393 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
394 struct regmap *regmap = priv->regmap;
395 u32 port_mask, port_ctrl, val;
396 int ret;
397
398
399 port_ctrl = FIELD_PREP(AR9331_SW_PORT_CTRL_PORT_STATE,
400 AR9331_SW_PORT_CTRL_PORT_STATE_FORWARD);
401
402 if (dsa_is_cpu_port(ds, port)) {
403
404
405
406 port_mask = dsa_user_ports(ds);
407
408
409
410 port_ctrl |= AR9331_SW_PORT_CTRL_HEAD_EN;
411 } else if (dsa_is_user_port(ds, port)) {
412
413
414 port_mask = BIT(dsa_upstream_port(ds, port));
415 } else {
416
417 port_mask = 0;
418 }
419
420 val = FIELD_PREP(AR9331_SW_PORT_VLAN_8021Q_MODE,
421 AR9331_SW_8021Q_MODE_NONE) |
422 FIELD_PREP(AR9331_SW_PORT_VLAN_PORT_VID_MEMBER, port_mask);
423
424 ret = regmap_write(regmap, AR9331_SW_REG_PORT_VLAN(port), val);
425 if (ret)
426 goto error;
427
428 ret = regmap_write(regmap, AR9331_SW_REG_PORT_CTRL(port), port_ctrl);
429 if (ret)
430 goto error;
431
432 return 0;
433error:
434 dev_err(priv->dev, "%s: error: %i\n", __func__, ret);
435
436 return ret;
437}
438
439static int ar9331_sw_setup(struct dsa_switch *ds)
440{
441 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
442 struct regmap *regmap = priv->regmap;
443 int ret, i;
444
445 ret = ar9331_sw_reset(priv);
446 if (ret)
447 return ret;
448
449
450
451
452 ret = ar9331_sw_mbus_init(priv);
453 if (ret)
454 return ret;
455
456
457 ret = regmap_write_bits(regmap, AR9331_SW_REG_FLOOD_MASK,
458 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU,
459 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU);
460 if (ret)
461 goto error;
462
463
464 ret = regmap_write_bits(regmap, AR9331_SW_REG_GLOBAL_CTRL,
465 AR9331_SW_GLOBAL_CTRL_MFS_M,
466 AR9331_SW_GLOBAL_CTRL_MFS_M);
467 if (ret)
468 goto error;
469
470 for (i = 0; i < ds->num_ports; i++) {
471 ret = ar9331_sw_setup_port(ds, i);
472 if (ret)
473 goto error;
474 }
475
476 ds->configure_vlan_while_not_filtering = false;
477
478 return 0;
479error:
480 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
481 return ret;
482}
483
484static void ar9331_sw_port_disable(struct dsa_switch *ds, int port)
485{
486 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
487 struct regmap *regmap = priv->regmap;
488 int ret;
489
490 ret = regmap_write(regmap, AR9331_SW_REG_PORT_STATUS(port), 0);
491 if (ret)
492 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
493}
494
495static enum dsa_tag_protocol ar9331_sw_get_tag_protocol(struct dsa_switch *ds,
496 int port,
497 enum dsa_tag_protocol m)
498{
499 return DSA_TAG_PROTO_AR9331;
500}
501
502static void ar9331_sw_phylink_validate(struct dsa_switch *ds, int port,
503 unsigned long *supported,
504 struct phylink_link_state *state)
505{
506 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
507
508 switch (port) {
509 case 0:
510 if (state->interface != PHY_INTERFACE_MODE_GMII)
511 goto unsupported;
512
513 phylink_set(mask, 1000baseT_Full);
514 phylink_set(mask, 1000baseT_Half);
515 break;
516 case 1:
517 case 2:
518 case 3:
519 case 4:
520 case 5:
521 if (state->interface != PHY_INTERFACE_MODE_INTERNAL)
522 goto unsupported;
523 break;
524 default:
525 linkmode_zero(supported);
526 dev_err(ds->dev, "Unsupported port: %i\n", port);
527 return;
528 }
529
530 phylink_set_port_modes(mask);
531 phylink_set(mask, Pause);
532 phylink_set(mask, Asym_Pause);
533
534 phylink_set(mask, 10baseT_Half);
535 phylink_set(mask, 10baseT_Full);
536 phylink_set(mask, 100baseT_Half);
537 phylink_set(mask, 100baseT_Full);
538
539 linkmode_and(supported, supported, mask);
540 linkmode_and(state->advertising, state->advertising, mask);
541
542 return;
543
544unsupported:
545 linkmode_zero(supported);
546 dev_err(ds->dev, "Unsupported interface: %d, port: %d\n",
547 state->interface, port);
548}
549
550static void ar9331_sw_phylink_mac_config(struct dsa_switch *ds, int port,
551 unsigned int mode,
552 const struct phylink_link_state *state)
553{
554 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
555 struct regmap *regmap = priv->regmap;
556 int ret;
557
558 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
559 AR9331_SW_PORT_STATUS_LINK_EN |
560 AR9331_SW_PORT_STATUS_FLOW_LINK_EN, 0);
561 if (ret)
562 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
563}
564
565static void ar9331_sw_phylink_mac_link_down(struct dsa_switch *ds, int port,
566 unsigned int mode,
567 phy_interface_t interface)
568{
569 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
570 struct ar9331_sw_port *p = &priv->port[port];
571 struct regmap *regmap = priv->regmap;
572 int ret;
573
574 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
575 AR9331_SW_PORT_STATUS_MAC_MASK, 0);
576 if (ret)
577 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
578
579 cancel_delayed_work_sync(&p->mib_read);
580}
581
582static void ar9331_sw_phylink_mac_link_up(struct dsa_switch *ds, int port,
583 unsigned int mode,
584 phy_interface_t interface,
585 struct phy_device *phydev,
586 int speed, int duplex,
587 bool tx_pause, bool rx_pause)
588{
589 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
590 struct ar9331_sw_port *p = &priv->port[port];
591 struct regmap *regmap = priv->regmap;
592 u32 val;
593 int ret;
594
595 schedule_delayed_work(&p->mib_read, 0);
596
597 val = AR9331_SW_PORT_STATUS_MAC_MASK;
598 switch (speed) {
599 case SPEED_1000:
600 val |= AR9331_SW_PORT_STATUS_SPEED_1000;
601 break;
602 case SPEED_100:
603 val |= AR9331_SW_PORT_STATUS_SPEED_100;
604 break;
605 case SPEED_10:
606 val |= AR9331_SW_PORT_STATUS_SPEED_10;
607 break;
608 default:
609 return;
610 }
611
612 if (duplex)
613 val |= AR9331_SW_PORT_STATUS_DUPLEX_MODE;
614
615 if (tx_pause)
616 val |= AR9331_SW_PORT_STATUS_TX_FLOW_EN;
617
618 if (rx_pause)
619 val |= AR9331_SW_PORT_STATUS_RX_FLOW_EN;
620
621 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port),
622 AR9331_SW_PORT_STATUS_MAC_MASK |
623 AR9331_SW_PORT_STATUS_LINK_MASK,
624 val);
625 if (ret)
626 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
627}
628
629static void ar9331_read_stats(struct ar9331_sw_port *port)
630{
631 struct ar9331_sw_priv *priv = ar9331_sw_port_to_priv(port);
632 struct rtnl_link_stats64 *stats = &port->stats;
633 struct ar9331_sw_stats_raw raw;
634 int ret;
635
636
637 ret = regmap_bulk_read(priv->regmap, AR9331_MIB_COUNTER(port->idx),
638 &raw, sizeof(raw) / sizeof(u32));
639 if (ret) {
640 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret);
641 return;
642 }
643
644
645 spin_lock(&port->stats_lock);
646
647 stats->rx_bytes += raw.rxgoodbyte;
648 stats->tx_bytes += raw.txbyte;
649
650 stats->rx_packets += raw.rx64byte + raw.rx128byte + raw.rx256byte +
651 raw.rx512byte + raw.rx1024byte + raw.rx1518byte + raw.rxmaxbyte;
652 stats->tx_packets += raw.tx64byte + raw.tx128byte + raw.tx256byte +
653 raw.tx512byte + raw.tx1024byte + raw.tx1518byte + raw.txmaxbyte;
654
655 stats->rx_length_errors += raw.rxrunt + raw.rxfragment + raw.rxtoolong;
656 stats->rx_crc_errors += raw.rxfcserr;
657 stats->rx_frame_errors += raw.rxalignerr;
658 stats->rx_missed_errors += raw.rxoverflow;
659 stats->rx_dropped += raw.filtered;
660 stats->rx_errors += raw.rxfcserr + raw.rxalignerr + raw.rxrunt +
661 raw.rxfragment + raw.rxoverflow + raw.rxtoolong;
662
663 stats->tx_window_errors += raw.txlatecol;
664 stats->tx_fifo_errors += raw.txunderrun;
665 stats->tx_aborted_errors += raw.txabortcol;
666 stats->tx_errors += raw.txoversize + raw.txabortcol + raw.txunderrun +
667 raw.txlatecol;
668
669 stats->multicast += raw.rxmulti;
670 stats->collisions += raw.txcollision;
671
672 spin_unlock(&port->stats_lock);
673}
674
675static void ar9331_do_stats_poll(struct work_struct *work)
676{
677 struct ar9331_sw_port *port = container_of(work, struct ar9331_sw_port,
678 mib_read.work);
679
680 ar9331_read_stats(port);
681
682 schedule_delayed_work(&port->mib_read, STATS_INTERVAL_JIFFIES);
683}
684
685static void ar9331_get_stats64(struct dsa_switch *ds, int port,
686 struct rtnl_link_stats64 *s)
687{
688 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv;
689 struct ar9331_sw_port *p = &priv->port[port];
690
691 spin_lock(&p->stats_lock);
692 memcpy(s, &p->stats, sizeof(*s));
693 spin_unlock(&p->stats_lock);
694}
695
696static const struct dsa_switch_ops ar9331_sw_ops = {
697 .get_tag_protocol = ar9331_sw_get_tag_protocol,
698 .setup = ar9331_sw_setup,
699 .port_disable = ar9331_sw_port_disable,
700 .phylink_validate = ar9331_sw_phylink_validate,
701 .phylink_mac_config = ar9331_sw_phylink_mac_config,
702 .phylink_mac_link_down = ar9331_sw_phylink_mac_link_down,
703 .phylink_mac_link_up = ar9331_sw_phylink_mac_link_up,
704 .get_stats64 = ar9331_get_stats64,
705};
706
707static irqreturn_t ar9331_sw_irq(int irq, void *data)
708{
709 struct ar9331_sw_priv *priv = data;
710 struct regmap *regmap = priv->regmap;
711 u32 stat;
712 int ret;
713
714 ret = regmap_read(regmap, AR9331_SW_REG_GINT, &stat);
715 if (ret) {
716 dev_err(priv->dev, "can't read interrupt status\n");
717 return IRQ_NONE;
718 }
719
720 if (!stat)
721 return IRQ_NONE;
722
723 if (stat & AR9331_SW_GINT_PHY_INT) {
724 int child_irq;
725
726 child_irq = irq_find_mapping(priv->irqdomain, 0);
727 handle_nested_irq(child_irq);
728 }
729
730 ret = regmap_write(regmap, AR9331_SW_REG_GINT, stat);
731 if (ret) {
732 dev_err(priv->dev, "can't write interrupt status\n");
733 return IRQ_NONE;
734 }
735
736 return IRQ_HANDLED;
737}
738
739static void ar9331_sw_mask_irq(struct irq_data *d)
740{
741 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
742
743 priv->irq_mask = 0;
744}
745
746static void ar9331_sw_unmask_irq(struct irq_data *d)
747{
748 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
749
750 priv->irq_mask = AR9331_SW_GINT_PHY_INT;
751}
752
753static void ar9331_sw_irq_bus_lock(struct irq_data *d)
754{
755 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
756
757 mutex_lock(&priv->lock_irq);
758}
759
760static void ar9331_sw_irq_bus_sync_unlock(struct irq_data *d)
761{
762 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d);
763 struct regmap *regmap = priv->regmap;
764 int ret;
765
766 ret = regmap_update_bits(regmap, AR9331_SW_REG_GINT_MASK,
767 AR9331_SW_GINT_PHY_INT, priv->irq_mask);
768 if (ret)
769 dev_err(priv->dev, "failed to change IRQ mask\n");
770
771 mutex_unlock(&priv->lock_irq);
772}
773
774static struct irq_chip ar9331_sw_irq_chip = {
775 .name = AR9331_SW_NAME,
776 .irq_mask = ar9331_sw_mask_irq,
777 .irq_unmask = ar9331_sw_unmask_irq,
778 .irq_bus_lock = ar9331_sw_irq_bus_lock,
779 .irq_bus_sync_unlock = ar9331_sw_irq_bus_sync_unlock,
780};
781
782static int ar9331_sw_irq_map(struct irq_domain *domain, unsigned int irq,
783 irq_hw_number_t hwirq)
784{
785 irq_set_chip_data(irq, domain->host_data);
786 irq_set_chip_and_handler(irq, &ar9331_sw_irq_chip, handle_simple_irq);
787 irq_set_nested_thread(irq, 1);
788 irq_set_noprobe(irq);
789
790 return 0;
791}
792
793static void ar9331_sw_irq_unmap(struct irq_domain *d, unsigned int irq)
794{
795 irq_set_nested_thread(irq, 0);
796 irq_set_chip_and_handler(irq, NULL, NULL);
797 irq_set_chip_data(irq, NULL);
798}
799
800static const struct irq_domain_ops ar9331_sw_irqdomain_ops = {
801 .map = ar9331_sw_irq_map,
802 .unmap = ar9331_sw_irq_unmap,
803 .xlate = irq_domain_xlate_onecell,
804};
805
806static int ar9331_sw_irq_init(struct ar9331_sw_priv *priv)
807{
808 struct device_node *np = priv->dev->of_node;
809 struct device *dev = priv->dev;
810 int ret, irq;
811
812 irq = of_irq_get(np, 0);
813 if (irq <= 0) {
814 dev_err(dev, "failed to get parent IRQ\n");
815 return irq ? irq : -EINVAL;
816 }
817
818 mutex_init(&priv->lock_irq);
819 ret = devm_request_threaded_irq(dev, irq, NULL, ar9331_sw_irq,
820 IRQF_ONESHOT, AR9331_SW_NAME, priv);
821 if (ret) {
822 dev_err(dev, "unable to request irq: %d\n", ret);
823 return ret;
824 }
825
826 priv->irqdomain = irq_domain_add_linear(np, 1, &ar9331_sw_irqdomain_ops,
827 priv);
828 if (!priv->irqdomain) {
829 dev_err(dev, "failed to create IRQ domain\n");
830 return -EINVAL;
831 }
832
833 irq_set_parent(irq_create_mapping(priv->irqdomain, 0), irq);
834
835 return 0;
836}
837
838static int __ar9331_mdio_write(struct mii_bus *sbus, u8 mode, u16 reg, u16 val)
839{
840 u8 r, p;
841
842 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, mode) |
843 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
844 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
845
846 return mdiobus_write(sbus, p, r, val);
847}
848
849static int __ar9331_mdio_read(struct mii_bus *sbus, u16 reg)
850{
851 u8 r, p;
852
853 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, AR9331_SW_MDIO_PHY_MODE_REG) |
854 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg);
855 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg);
856
857 return mdiobus_read(sbus, p, r);
858}
859
860static int ar9331_mdio_read(void *ctx, const void *reg_buf, size_t reg_len,
861 void *val_buf, size_t val_len)
862{
863 struct ar9331_sw_priv *priv = ctx;
864 struct mii_bus *sbus = priv->sbus;
865 u32 reg = *(u32 *)reg_buf;
866 int ret;
867
868 if (reg == AR9331_SW_REG_PAGE) {
869
870
871
872
873 *(u32 *)val_buf = GENMASK(9, 0);
874 return 0;
875 }
876
877 ret = __ar9331_mdio_read(sbus, reg);
878 if (ret < 0)
879 goto error;
880
881 *(u32 *)val_buf = ret;
882 ret = __ar9331_mdio_read(sbus, reg + 2);
883 if (ret < 0)
884 goto error;
885
886 *(u32 *)val_buf |= ret << 16;
887
888 return 0;
889error:
890 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to read register.\n");
891 return ret;
892}
893
894static int ar9331_mdio_write(void *ctx, u32 reg, u32 val)
895{
896 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ctx;
897 struct mii_bus *sbus = priv->sbus;
898 int ret;
899
900 if (reg == AR9331_SW_REG_PAGE) {
901 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_PAGE,
902 0, val);
903 if (ret < 0)
904 goto error;
905
906 return 0;
907 }
908
909
910
911
912
913
914
915
916 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg + 2,
917 val >> 16);
918 if (ret < 0)
919 goto error;
920
921 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg, val);
922 if (ret < 0)
923 goto error;
924
925 return 0;
926
927error:
928 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n");
929 return ret;
930}
931
932static int ar9331_sw_bus_write(void *context, const void *data, size_t count)
933{
934 u32 reg = *(u32 *)data;
935 u32 val = *((u32 *)data + 1);
936
937 return ar9331_mdio_write(context, reg, val);
938}
939
940static const struct regmap_range ar9331_valid_regs[] = {
941 regmap_reg_range(0x0, 0x0),
942 regmap_reg_range(0x10, 0x14),
943 regmap_reg_range(0x20, 0x24),
944 regmap_reg_range(0x2c, 0x30),
945 regmap_reg_range(0x40, 0x44),
946 regmap_reg_range(0x50, 0x78),
947 regmap_reg_range(0x80, 0x98),
948
949 regmap_reg_range(0x100, 0x120),
950 regmap_reg_range(0x200, 0x220),
951 regmap_reg_range(0x300, 0x320),
952 regmap_reg_range(0x400, 0x420),
953 regmap_reg_range(0x500, 0x520),
954 regmap_reg_range(0x600, 0x620),
955
956 regmap_reg_range(0x20000, 0x200a4),
957 regmap_reg_range(0x20100, 0x201a4),
958 regmap_reg_range(0x20200, 0x202a4),
959 regmap_reg_range(0x20300, 0x203a4),
960 regmap_reg_range(0x20400, 0x204a4),
961 regmap_reg_range(0x20500, 0x205a4),
962
963
964 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
965};
966
967static const struct regmap_range ar9331_nonvolatile_regs[] = {
968 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE),
969};
970
971static const struct regmap_range_cfg ar9331_regmap_range[] = {
972 {
973 .selector_reg = AR9331_SW_REG_PAGE,
974 .selector_mask = GENMASK(9, 0),
975 .selector_shift = 0,
976
977 .window_start = 0,
978 .window_len = 512,
979
980 .range_min = 0,
981 .range_max = AR9331_SW_REG_PAGE - 4,
982 },
983};
984
985static const struct regmap_access_table ar9331_register_set = {
986 .yes_ranges = ar9331_valid_regs,
987 .n_yes_ranges = ARRAY_SIZE(ar9331_valid_regs),
988};
989
990static const struct regmap_access_table ar9331_volatile_set = {
991 .no_ranges = ar9331_nonvolatile_regs,
992 .n_no_ranges = ARRAY_SIZE(ar9331_nonvolatile_regs),
993};
994
995static const struct regmap_config ar9331_mdio_regmap_config = {
996 .reg_bits = 32,
997 .val_bits = 32,
998 .reg_stride = 4,
999 .max_register = AR9331_SW_REG_PAGE,
1000
1001 .ranges = ar9331_regmap_range,
1002 .num_ranges = ARRAY_SIZE(ar9331_regmap_range),
1003
1004 .volatile_table = &ar9331_volatile_set,
1005 .wr_table = &ar9331_register_set,
1006 .rd_table = &ar9331_register_set,
1007
1008 .cache_type = REGCACHE_RBTREE,
1009};
1010
1011static struct regmap_bus ar9331_sw_bus = {
1012 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
1013 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
1014 .read = ar9331_mdio_read,
1015 .write = ar9331_sw_bus_write,
1016 .max_raw_read = 4,
1017 .max_raw_write = 4,
1018};
1019
1020static int ar9331_sw_probe(struct mdio_device *mdiodev)
1021{
1022 struct ar9331_sw_priv *priv;
1023 struct dsa_switch *ds;
1024 int ret, i;
1025
1026 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
1027 if (!priv)
1028 return -ENOMEM;
1029
1030 priv->regmap = devm_regmap_init(&mdiodev->dev, &ar9331_sw_bus, priv,
1031 &ar9331_mdio_regmap_config);
1032 if (IS_ERR(priv->regmap)) {
1033 ret = PTR_ERR(priv->regmap);
1034 dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret);
1035 return ret;
1036 }
1037
1038 priv->sw_reset = devm_reset_control_get(&mdiodev->dev, "switch");
1039 if (IS_ERR(priv->sw_reset)) {
1040 dev_err(&mdiodev->dev, "missing switch reset\n");
1041 return PTR_ERR(priv->sw_reset);
1042 }
1043
1044 priv->sbus = mdiodev->bus;
1045 priv->dev = &mdiodev->dev;
1046
1047 ret = ar9331_sw_irq_init(priv);
1048 if (ret)
1049 return ret;
1050
1051 ds = &priv->ds;
1052 ds->dev = &mdiodev->dev;
1053 ds->num_ports = AR9331_SW_PORTS;
1054 ds->priv = priv;
1055 priv->ops = ar9331_sw_ops;
1056 ds->ops = &priv->ops;
1057 dev_set_drvdata(&mdiodev->dev, priv);
1058
1059 for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1060 struct ar9331_sw_port *port = &priv->port[i];
1061
1062 port->idx = i;
1063 spin_lock_init(&port->stats_lock);
1064 INIT_DELAYED_WORK(&port->mib_read, ar9331_do_stats_poll);
1065 }
1066
1067 ret = dsa_register_switch(ds);
1068 if (ret)
1069 goto err_remove_irq;
1070
1071 return 0;
1072
1073err_remove_irq:
1074 irq_domain_remove(priv->irqdomain);
1075
1076 return ret;
1077}
1078
1079static void ar9331_sw_remove(struct mdio_device *mdiodev)
1080{
1081 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
1082 unsigned int i;
1083
1084 if (!priv)
1085 return;
1086
1087 for (i = 0; i < ARRAY_SIZE(priv->port); i++) {
1088 struct ar9331_sw_port *port = &priv->port[i];
1089
1090 cancel_delayed_work_sync(&port->mib_read);
1091 }
1092
1093 irq_domain_remove(priv->irqdomain);
1094 mdiobus_unregister(priv->mbus);
1095 dsa_unregister_switch(&priv->ds);
1096
1097 reset_control_assert(priv->sw_reset);
1098
1099 dev_set_drvdata(&mdiodev->dev, NULL);
1100}
1101
1102static void ar9331_sw_shutdown(struct mdio_device *mdiodev)
1103{
1104 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev);
1105
1106 if (!priv)
1107 return;
1108
1109 dsa_switch_shutdown(&priv->ds);
1110
1111 dev_set_drvdata(&mdiodev->dev, NULL);
1112}
1113
1114static const struct of_device_id ar9331_sw_of_match[] = {
1115 { .compatible = "qca,ar9331-switch" },
1116 { },
1117};
1118
1119static struct mdio_driver ar9331_sw_mdio_driver = {
1120 .probe = ar9331_sw_probe,
1121 .remove = ar9331_sw_remove,
1122 .shutdown = ar9331_sw_shutdown,
1123 .mdiodrv.driver = {
1124 .name = AR9331_SW_NAME,
1125 .of_match_table = ar9331_sw_of_match,
1126 },
1127};
1128
1129mdio_module_driver(ar9331_sw_mdio_driver);
1130
1131MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
1132MODULE_DESCRIPTION("Driver for Atheros AR9331 switch");
1133MODULE_LICENSE("GPL v2");
1134