1
2
3
4
5
6#include "i40e.h"
7#include "i40e_diag.h"
8#include "i40e_txrx_common.h"
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34struct i40e_stats {
35 char stat_string[ETH_GSTRING_LEN];
36 int sizeof_stat;
37 int stat_offset;
38};
39
40
41
42
43
44#define I40E_STAT(_type, _name, _stat) { \
45 .stat_string = _name, \
46 .sizeof_stat = sizeof_field(_type, _stat), \
47 .stat_offset = offsetof(_type, _stat) \
48}
49
50
51
52
53#define I40E_NETDEV_STAT(_net_stat) \
54 I40E_STAT(struct rtnl_link_stats64, #_net_stat, _net_stat)
55
56
57#define I40E_QUEUE_STAT(_name, _stat) \
58 I40E_STAT(struct i40e_ring, _name, _stat)
59
60
61static const struct i40e_stats i40e_gstrings_queue_stats[] = {
62 I40E_QUEUE_STAT("%s-%u.packets", stats.packets),
63 I40E_QUEUE_STAT("%s-%u.bytes", stats.bytes),
64};
65
66
67
68
69
70
71
72
73
74
75
76static void
77i40e_add_one_ethtool_stat(u64 *data, void *pointer,
78 const struct i40e_stats *stat)
79{
80 char *p;
81
82 if (!pointer) {
83
84
85
86 *data = 0;
87 return;
88 }
89
90 p = (char *)pointer + stat->stat_offset;
91 switch (stat->sizeof_stat) {
92 case sizeof(u64):
93 *data = *((u64 *)p);
94 break;
95 case sizeof(u32):
96 *data = *((u32 *)p);
97 break;
98 case sizeof(u16):
99 *data = *((u16 *)p);
100 break;
101 case sizeof(u8):
102 *data = *((u8 *)p);
103 break;
104 default:
105 WARN_ONCE(1, "unexpected stat size for %s",
106 stat->stat_string);
107 *data = 0;
108 }
109}
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124static void
125__i40e_add_ethtool_stats(u64 **data, void *pointer,
126 const struct i40e_stats stats[],
127 const unsigned int size)
128{
129 unsigned int i;
130
131 for (i = 0; i < size; i++)
132 i40e_add_one_ethtool_stat((*data)++, pointer, &stats[i]);
133}
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148#define i40e_add_ethtool_stats(data, pointer, stats) \
149 __i40e_add_ethtool_stats(data, pointer, stats, ARRAY_SIZE(stats))
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165static void
166i40e_add_queue_stats(u64 **data, struct i40e_ring *ring)
167{
168 const unsigned int size = ARRAY_SIZE(i40e_gstrings_queue_stats);
169 const struct i40e_stats *stats = i40e_gstrings_queue_stats;
170 unsigned int start;
171 unsigned int i;
172
173
174
175
176
177
178 do {
179 start = !ring ? 0 : u64_stats_fetch_begin_irq(&ring->syncp);
180 for (i = 0; i < size; i++) {
181 i40e_add_one_ethtool_stat(&(*data)[i], ring,
182 &stats[i]);
183 }
184 } while (ring && u64_stats_fetch_retry_irq(&ring->syncp, start));
185
186
187 *data += size;
188}
189
190
191
192
193
194
195
196
197
198
199static void __i40e_add_stat_strings(u8 **p, const struct i40e_stats stats[],
200 const unsigned int size, ...)
201{
202 unsigned int i;
203
204 for (i = 0; i < size; i++) {
205 va_list args;
206
207 va_start(args, size);
208 vsnprintf(*p, ETH_GSTRING_LEN, stats[i].stat_string, args);
209 *p += ETH_GSTRING_LEN;
210 va_end(args);
211 }
212}
213
214
215
216
217
218
219
220
221
222
223
224
225
226#define i40e_add_stat_strings(p, stats, ...) \
227 __i40e_add_stat_strings(p, stats, ARRAY_SIZE(stats), ## __VA_ARGS__)
228
229#define I40E_PF_STAT(_name, _stat) \
230 I40E_STAT(struct i40e_pf, _name, _stat)
231#define I40E_VSI_STAT(_name, _stat) \
232 I40E_STAT(struct i40e_vsi, _name, _stat)
233#define I40E_VEB_STAT(_name, _stat) \
234 I40E_STAT(struct i40e_veb, _name, _stat)
235#define I40E_VEB_TC_STAT(_name, _stat) \
236 I40E_STAT(struct i40e_cp_veb_tc_stats, _name, _stat)
237#define I40E_PFC_STAT(_name, _stat) \
238 I40E_STAT(struct i40e_pfc_stats, _name, _stat)
239#define I40E_QUEUE_STAT(_name, _stat) \
240 I40E_STAT(struct i40e_ring, _name, _stat)
241
242static const struct i40e_stats i40e_gstrings_net_stats[] = {
243 I40E_NETDEV_STAT(rx_packets),
244 I40E_NETDEV_STAT(tx_packets),
245 I40E_NETDEV_STAT(rx_bytes),
246 I40E_NETDEV_STAT(tx_bytes),
247 I40E_NETDEV_STAT(rx_errors),
248 I40E_NETDEV_STAT(tx_errors),
249 I40E_NETDEV_STAT(rx_dropped),
250 I40E_NETDEV_STAT(tx_dropped),
251 I40E_NETDEV_STAT(collisions),
252 I40E_NETDEV_STAT(rx_length_errors),
253 I40E_NETDEV_STAT(rx_crc_errors),
254};
255
256static const struct i40e_stats i40e_gstrings_veb_stats[] = {
257 I40E_VEB_STAT("veb.rx_bytes", stats.rx_bytes),
258 I40E_VEB_STAT("veb.tx_bytes", stats.tx_bytes),
259 I40E_VEB_STAT("veb.rx_unicast", stats.rx_unicast),
260 I40E_VEB_STAT("veb.tx_unicast", stats.tx_unicast),
261 I40E_VEB_STAT("veb.rx_multicast", stats.rx_multicast),
262 I40E_VEB_STAT("veb.tx_multicast", stats.tx_multicast),
263 I40E_VEB_STAT("veb.rx_broadcast", stats.rx_broadcast),
264 I40E_VEB_STAT("veb.tx_broadcast", stats.tx_broadcast),
265 I40E_VEB_STAT("veb.rx_discards", stats.rx_discards),
266 I40E_VEB_STAT("veb.tx_discards", stats.tx_discards),
267 I40E_VEB_STAT("veb.tx_errors", stats.tx_errors),
268 I40E_VEB_STAT("veb.rx_unknown_protocol", stats.rx_unknown_protocol),
269};
270
271struct i40e_cp_veb_tc_stats {
272 u64 tc_rx_packets;
273 u64 tc_rx_bytes;
274 u64 tc_tx_packets;
275 u64 tc_tx_bytes;
276};
277
278static const struct i40e_stats i40e_gstrings_veb_tc_stats[] = {
279 I40E_VEB_TC_STAT("veb.tc_%u_tx_packets", tc_tx_packets),
280 I40E_VEB_TC_STAT("veb.tc_%u_tx_bytes", tc_tx_bytes),
281 I40E_VEB_TC_STAT("veb.tc_%u_rx_packets", tc_rx_packets),
282 I40E_VEB_TC_STAT("veb.tc_%u_rx_bytes", tc_rx_bytes),
283};
284
285static const struct i40e_stats i40e_gstrings_misc_stats[] = {
286 I40E_VSI_STAT("rx_unicast", eth_stats.rx_unicast),
287 I40E_VSI_STAT("tx_unicast", eth_stats.tx_unicast),
288 I40E_VSI_STAT("rx_multicast", eth_stats.rx_multicast),
289 I40E_VSI_STAT("tx_multicast", eth_stats.tx_multicast),
290 I40E_VSI_STAT("rx_broadcast", eth_stats.rx_broadcast),
291 I40E_VSI_STAT("tx_broadcast", eth_stats.tx_broadcast),
292 I40E_VSI_STAT("rx_unknown_protocol", eth_stats.rx_unknown_protocol),
293 I40E_VSI_STAT("tx_linearize", tx_linearize),
294 I40E_VSI_STAT("tx_force_wb", tx_force_wb),
295 I40E_VSI_STAT("tx_busy", tx_busy),
296 I40E_VSI_STAT("rx_alloc_fail", rx_buf_failed),
297 I40E_VSI_STAT("rx_pg_alloc_fail", rx_page_failed),
298};
299
300
301
302
303
304
305
306
307
308
309
310static const struct i40e_stats i40e_gstrings_stats[] = {
311 I40E_PF_STAT("port.rx_bytes", stats.eth.rx_bytes),
312 I40E_PF_STAT("port.tx_bytes", stats.eth.tx_bytes),
313 I40E_PF_STAT("port.rx_unicast", stats.eth.rx_unicast),
314 I40E_PF_STAT("port.tx_unicast", stats.eth.tx_unicast),
315 I40E_PF_STAT("port.rx_multicast", stats.eth.rx_multicast),
316 I40E_PF_STAT("port.tx_multicast", stats.eth.tx_multicast),
317 I40E_PF_STAT("port.rx_broadcast", stats.eth.rx_broadcast),
318 I40E_PF_STAT("port.tx_broadcast", stats.eth.tx_broadcast),
319 I40E_PF_STAT("port.tx_errors", stats.eth.tx_errors),
320 I40E_PF_STAT("port.rx_dropped", stats.eth.rx_discards),
321 I40E_PF_STAT("port.tx_dropped_link_down", stats.tx_dropped_link_down),
322 I40E_PF_STAT("port.rx_crc_errors", stats.crc_errors),
323 I40E_PF_STAT("port.illegal_bytes", stats.illegal_bytes),
324 I40E_PF_STAT("port.mac_local_faults", stats.mac_local_faults),
325 I40E_PF_STAT("port.mac_remote_faults", stats.mac_remote_faults),
326 I40E_PF_STAT("port.tx_timeout", tx_timeout_count),
327 I40E_PF_STAT("port.rx_csum_bad", hw_csum_rx_error),
328 I40E_PF_STAT("port.rx_length_errors", stats.rx_length_errors),
329 I40E_PF_STAT("port.link_xon_rx", stats.link_xon_rx),
330 I40E_PF_STAT("port.link_xoff_rx", stats.link_xoff_rx),
331 I40E_PF_STAT("port.link_xon_tx", stats.link_xon_tx),
332 I40E_PF_STAT("port.link_xoff_tx", stats.link_xoff_tx),
333 I40E_PF_STAT("port.rx_size_64", stats.rx_size_64),
334 I40E_PF_STAT("port.rx_size_127", stats.rx_size_127),
335 I40E_PF_STAT("port.rx_size_255", stats.rx_size_255),
336 I40E_PF_STAT("port.rx_size_511", stats.rx_size_511),
337 I40E_PF_STAT("port.rx_size_1023", stats.rx_size_1023),
338 I40E_PF_STAT("port.rx_size_1522", stats.rx_size_1522),
339 I40E_PF_STAT("port.rx_size_big", stats.rx_size_big),
340 I40E_PF_STAT("port.tx_size_64", stats.tx_size_64),
341 I40E_PF_STAT("port.tx_size_127", stats.tx_size_127),
342 I40E_PF_STAT("port.tx_size_255", stats.tx_size_255),
343 I40E_PF_STAT("port.tx_size_511", stats.tx_size_511),
344 I40E_PF_STAT("port.tx_size_1023", stats.tx_size_1023),
345 I40E_PF_STAT("port.tx_size_1522", stats.tx_size_1522),
346 I40E_PF_STAT("port.tx_size_big", stats.tx_size_big),
347 I40E_PF_STAT("port.rx_undersize", stats.rx_undersize),
348 I40E_PF_STAT("port.rx_fragments", stats.rx_fragments),
349 I40E_PF_STAT("port.rx_oversize", stats.rx_oversize),
350 I40E_PF_STAT("port.rx_jabber", stats.rx_jabber),
351 I40E_PF_STAT("port.VF_admin_queue_requests", vf_aq_requests),
352 I40E_PF_STAT("port.arq_overflows", arq_overflows),
353 I40E_PF_STAT("port.tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
354 I40E_PF_STAT("port.rx_hwtstamp_cleared", rx_hwtstamp_cleared),
355 I40E_PF_STAT("port.tx_hwtstamp_skipped", tx_hwtstamp_skipped),
356 I40E_PF_STAT("port.fdir_flush_cnt", fd_flush_cnt),
357 I40E_PF_STAT("port.fdir_atr_match", stats.fd_atr_match),
358 I40E_PF_STAT("port.fdir_atr_tunnel_match", stats.fd_atr_tunnel_match),
359 I40E_PF_STAT("port.fdir_atr_status", stats.fd_atr_status),
360 I40E_PF_STAT("port.fdir_sb_match", stats.fd_sb_match),
361 I40E_PF_STAT("port.fdir_sb_status", stats.fd_sb_status),
362
363
364 I40E_PF_STAT("port.tx_lpi_status", stats.tx_lpi_status),
365 I40E_PF_STAT("port.rx_lpi_status", stats.rx_lpi_status),
366 I40E_PF_STAT("port.tx_lpi_count", stats.tx_lpi_count),
367 I40E_PF_STAT("port.rx_lpi_count", stats.rx_lpi_count),
368};
369
370struct i40e_pfc_stats {
371 u64 priority_xon_rx;
372 u64 priority_xoff_rx;
373 u64 priority_xon_tx;
374 u64 priority_xoff_tx;
375 u64 priority_xon_2_xoff;
376};
377
378static const struct i40e_stats i40e_gstrings_pfc_stats[] = {
379 I40E_PFC_STAT("port.tx_priority_%u_xon_tx", priority_xon_tx),
380 I40E_PFC_STAT("port.tx_priority_%u_xoff_tx", priority_xoff_tx),
381 I40E_PFC_STAT("port.rx_priority_%u_xon_rx", priority_xon_rx),
382 I40E_PFC_STAT("port.rx_priority_%u_xoff_rx", priority_xoff_rx),
383 I40E_PFC_STAT("port.rx_priority_%u_xon_2_xoff", priority_xon_2_xoff),
384};
385
386#define I40E_NETDEV_STATS_LEN ARRAY_SIZE(i40e_gstrings_net_stats)
387
388#define I40E_MISC_STATS_LEN ARRAY_SIZE(i40e_gstrings_misc_stats)
389
390#define I40E_VSI_STATS_LEN (I40E_NETDEV_STATS_LEN + I40E_MISC_STATS_LEN)
391
392#define I40E_PFC_STATS_LEN (ARRAY_SIZE(i40e_gstrings_pfc_stats) * \
393 I40E_MAX_USER_PRIORITY)
394
395#define I40E_VEB_STATS_LEN (ARRAY_SIZE(i40e_gstrings_veb_stats) + \
396 (ARRAY_SIZE(i40e_gstrings_veb_tc_stats) * \
397 I40E_MAX_TRAFFIC_CLASS))
398
399#define I40E_GLOBAL_STATS_LEN ARRAY_SIZE(i40e_gstrings_stats)
400
401#define I40E_PF_STATS_LEN (I40E_GLOBAL_STATS_LEN + \
402 I40E_PFC_STATS_LEN + \
403 I40E_VEB_STATS_LEN + \
404 I40E_VSI_STATS_LEN)
405
406
407#define I40E_QUEUE_STATS_LEN ARRAY_SIZE(i40e_gstrings_queue_stats)
408
409enum i40e_ethtool_test_id {
410 I40E_ETH_TEST_REG = 0,
411 I40E_ETH_TEST_EEPROM,
412 I40E_ETH_TEST_INTR,
413 I40E_ETH_TEST_LINK,
414};
415
416static const char i40e_gstrings_test[][ETH_GSTRING_LEN] = {
417 "Register test (offline)",
418 "Eeprom test (offline)",
419 "Interrupt test (offline)",
420 "Link test (on/offline)"
421};
422
423#define I40E_TEST_LEN (sizeof(i40e_gstrings_test) / ETH_GSTRING_LEN)
424
425struct i40e_priv_flags {
426 char flag_string[ETH_GSTRING_LEN];
427 u64 flag;
428 bool read_only;
429};
430
431#define I40E_PRIV_FLAG(_name, _flag, _read_only) { \
432 .flag_string = _name, \
433 .flag = _flag, \
434 .read_only = _read_only, \
435}
436
437static const struct i40e_priv_flags i40e_gstrings_priv_flags[] = {
438
439 I40E_PRIV_FLAG("MFP", I40E_FLAG_MFP_ENABLED, 1),
440 I40E_PRIV_FLAG("total-port-shutdown",
441 I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED, 1),
442 I40E_PRIV_FLAG("LinkPolling", I40E_FLAG_LINK_POLLING_ENABLED, 0),
443 I40E_PRIV_FLAG("flow-director-atr", I40E_FLAG_FD_ATR_ENABLED, 0),
444 I40E_PRIV_FLAG("veb-stats", I40E_FLAG_VEB_STATS_ENABLED, 0),
445 I40E_PRIV_FLAG("hw-atr-eviction", I40E_FLAG_HW_ATR_EVICT_ENABLED, 0),
446 I40E_PRIV_FLAG("link-down-on-close",
447 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED, 0),
448 I40E_PRIV_FLAG("legacy-rx", I40E_FLAG_LEGACY_RX, 0),
449 I40E_PRIV_FLAG("disable-source-pruning",
450 I40E_FLAG_SOURCE_PRUNING_DISABLED, 0),
451 I40E_PRIV_FLAG("disable-fw-lldp", I40E_FLAG_DISABLE_FW_LLDP, 0),
452 I40E_PRIV_FLAG("rs-fec", I40E_FLAG_RS_FEC, 0),
453 I40E_PRIV_FLAG("base-r-fec", I40E_FLAG_BASE_R_FEC, 0),
454};
455
456#define I40E_PRIV_FLAGS_STR_LEN ARRAY_SIZE(i40e_gstrings_priv_flags)
457
458
459static const struct i40e_priv_flags i40e_gl_gstrings_priv_flags[] = {
460 I40E_PRIV_FLAG("vf-true-promisc-support",
461 I40E_FLAG_TRUE_PROMISC_SUPPORT, 0),
462};
463
464#define I40E_GL_PRIV_FLAGS_STR_LEN ARRAY_SIZE(i40e_gl_gstrings_priv_flags)
465
466
467
468
469
470static void i40e_partition_setting_complaint(struct i40e_pf *pf)
471{
472 dev_info(&pf->pdev->dev,
473 "The link settings are allowed to be changed only from the first partition of a given port. Please switch to the first partition in order to change the setting.\n");
474}
475
476
477
478
479
480
481
482static void i40e_phy_type_to_ethtool(struct i40e_pf *pf,
483 struct ethtool_link_ksettings *ks)
484{
485 struct i40e_link_status *hw_link_info = &pf->hw.phy.link_info;
486 u64 phy_types = pf->hw.phy.phy_types;
487
488 ethtool_link_ksettings_zero_link_mode(ks, supported);
489 ethtool_link_ksettings_zero_link_mode(ks, advertising);
490
491 if (phy_types & I40E_CAP_PHY_TYPE_SGMII) {
492 ethtool_link_ksettings_add_link_mode(ks, supported,
493 1000baseT_Full);
494 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
495 ethtool_link_ksettings_add_link_mode(ks, advertising,
496 1000baseT_Full);
497 if (pf->hw_features & I40E_HW_100M_SGMII_CAPABLE) {
498 ethtool_link_ksettings_add_link_mode(ks, supported,
499 100baseT_Full);
500 ethtool_link_ksettings_add_link_mode(ks, advertising,
501 100baseT_Full);
502 }
503 }
504 if (phy_types & I40E_CAP_PHY_TYPE_XAUI ||
505 phy_types & I40E_CAP_PHY_TYPE_XFI ||
506 phy_types & I40E_CAP_PHY_TYPE_SFI ||
507 phy_types & I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU ||
508 phy_types & I40E_CAP_PHY_TYPE_10GBASE_AOC) {
509 ethtool_link_ksettings_add_link_mode(ks, supported,
510 10000baseT_Full);
511 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
512 ethtool_link_ksettings_add_link_mode(ks, advertising,
513 10000baseT_Full);
514 }
515 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_T) {
516 ethtool_link_ksettings_add_link_mode(ks, supported,
517 10000baseT_Full);
518 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
519 ethtool_link_ksettings_add_link_mode(ks, advertising,
520 10000baseT_Full);
521 }
522 if (phy_types & I40E_CAP_PHY_TYPE_2_5GBASE_T) {
523 ethtool_link_ksettings_add_link_mode(ks, supported,
524 2500baseT_Full);
525 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_2_5GB)
526 ethtool_link_ksettings_add_link_mode(ks, advertising,
527 2500baseT_Full);
528 }
529 if (phy_types & I40E_CAP_PHY_TYPE_5GBASE_T) {
530 ethtool_link_ksettings_add_link_mode(ks, supported,
531 5000baseT_Full);
532 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_5GB)
533 ethtool_link_ksettings_add_link_mode(ks, advertising,
534 5000baseT_Full);
535 }
536 if (phy_types & I40E_CAP_PHY_TYPE_XLAUI ||
537 phy_types & I40E_CAP_PHY_TYPE_XLPPI ||
538 phy_types & I40E_CAP_PHY_TYPE_40GBASE_AOC)
539 ethtool_link_ksettings_add_link_mode(ks, supported,
540 40000baseCR4_Full);
541 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU ||
542 phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4) {
543 ethtool_link_ksettings_add_link_mode(ks, supported,
544 40000baseCR4_Full);
545 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_40GB)
546 ethtool_link_ksettings_add_link_mode(ks, advertising,
547 40000baseCR4_Full);
548 }
549 if (phy_types & I40E_CAP_PHY_TYPE_100BASE_TX) {
550 ethtool_link_ksettings_add_link_mode(ks, supported,
551 100baseT_Full);
552 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_100MB)
553 ethtool_link_ksettings_add_link_mode(ks, advertising,
554 100baseT_Full);
555 }
556 if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_T) {
557 ethtool_link_ksettings_add_link_mode(ks, supported,
558 1000baseT_Full);
559 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
560 ethtool_link_ksettings_add_link_mode(ks, advertising,
561 1000baseT_Full);
562 }
563 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_SR4) {
564 ethtool_link_ksettings_add_link_mode(ks, supported,
565 40000baseSR4_Full);
566 ethtool_link_ksettings_add_link_mode(ks, advertising,
567 40000baseSR4_Full);
568 }
569 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_LR4) {
570 ethtool_link_ksettings_add_link_mode(ks, supported,
571 40000baseLR4_Full);
572 ethtool_link_ksettings_add_link_mode(ks, advertising,
573 40000baseLR4_Full);
574 }
575 if (phy_types & I40E_CAP_PHY_TYPE_40GBASE_KR4) {
576 ethtool_link_ksettings_add_link_mode(ks, supported,
577 40000baseKR4_Full);
578 ethtool_link_ksettings_add_link_mode(ks, advertising,
579 40000baseKR4_Full);
580 }
581 if (phy_types & I40E_CAP_PHY_TYPE_20GBASE_KR2) {
582 ethtool_link_ksettings_add_link_mode(ks, supported,
583 20000baseKR2_Full);
584 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_20GB)
585 ethtool_link_ksettings_add_link_mode(ks, advertising,
586 20000baseKR2_Full);
587 }
588 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KX4) {
589 ethtool_link_ksettings_add_link_mode(ks, supported,
590 10000baseKX4_Full);
591 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
592 ethtool_link_ksettings_add_link_mode(ks, advertising,
593 10000baseKX4_Full);
594 }
595 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KR &&
596 !(pf->hw_features & I40E_HW_HAVE_CRT_RETIMER)) {
597 ethtool_link_ksettings_add_link_mode(ks, supported,
598 10000baseKR_Full);
599 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
600 ethtool_link_ksettings_add_link_mode(ks, advertising,
601 10000baseKR_Full);
602 }
603 if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_KX &&
604 !(pf->hw_features & I40E_HW_HAVE_CRT_RETIMER)) {
605 ethtool_link_ksettings_add_link_mode(ks, supported,
606 1000baseKX_Full);
607 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
608 ethtool_link_ksettings_add_link_mode(ks, advertising,
609 1000baseKX_Full);
610 }
611
612 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR) {
613 ethtool_link_ksettings_add_link_mode(ks, supported,
614 25000baseKR_Full);
615 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
616 ethtool_link_ksettings_add_link_mode(ks, advertising,
617 25000baseKR_Full);
618 }
619 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR) {
620 ethtool_link_ksettings_add_link_mode(ks, supported,
621 25000baseCR_Full);
622 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
623 ethtool_link_ksettings_add_link_mode(ks, advertising,
624 25000baseCR_Full);
625 }
626 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
627 phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR) {
628 ethtool_link_ksettings_add_link_mode(ks, supported,
629 25000baseSR_Full);
630 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
631 ethtool_link_ksettings_add_link_mode(ks, advertising,
632 25000baseSR_Full);
633 }
634 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_AOC ||
635 phy_types & I40E_CAP_PHY_TYPE_25GBASE_ACC) {
636 ethtool_link_ksettings_add_link_mode(ks, supported,
637 25000baseCR_Full);
638 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB)
639 ethtool_link_ksettings_add_link_mode(ks, advertising,
640 25000baseCR_Full);
641 }
642 if (phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR ||
643 phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR ||
644 phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
645 phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR ||
646 phy_types & I40E_CAP_PHY_TYPE_25GBASE_AOC ||
647 phy_types & I40E_CAP_PHY_TYPE_25GBASE_ACC) {
648 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
649 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
650 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
651 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_25GB) {
652 ethtool_link_ksettings_add_link_mode(ks, advertising,
653 FEC_NONE);
654 ethtool_link_ksettings_add_link_mode(ks, advertising,
655 FEC_RS);
656 ethtool_link_ksettings_add_link_mode(ks, advertising,
657 FEC_BASER);
658 }
659 }
660
661 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1 ||
662 phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1_CU) {
663 ethtool_link_ksettings_add_link_mode(ks, supported,
664 10000baseCR_Full);
665 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
666 ethtool_link_ksettings_add_link_mode(ks, advertising,
667 10000baseCR_Full);
668 }
669 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_SR) {
670 ethtool_link_ksettings_add_link_mode(ks, supported,
671 10000baseSR_Full);
672 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
673 ethtool_link_ksettings_add_link_mode(ks, advertising,
674 10000baseSR_Full);
675 }
676 if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_LR) {
677 ethtool_link_ksettings_add_link_mode(ks, supported,
678 10000baseLR_Full);
679 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
680 ethtool_link_ksettings_add_link_mode(ks, advertising,
681 10000baseLR_Full);
682 }
683 if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_SX ||
684 phy_types & I40E_CAP_PHY_TYPE_1000BASE_LX ||
685 phy_types & I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL) {
686 ethtool_link_ksettings_add_link_mode(ks, supported,
687 1000baseX_Full);
688 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
689 ethtool_link_ksettings_add_link_mode(ks, advertising,
690 1000baseX_Full);
691 }
692
693 if (phy_types & I40E_CAP_PHY_TYPE_SGMII ||
694 phy_types & I40E_CAP_PHY_TYPE_40GBASE_KR4 ||
695 phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU ||
696 phy_types & I40E_CAP_PHY_TYPE_40GBASE_CR4 ||
697 phy_types & I40E_CAP_PHY_TYPE_25GBASE_SR ||
698 phy_types & I40E_CAP_PHY_TYPE_25GBASE_LR ||
699 phy_types & I40E_CAP_PHY_TYPE_25GBASE_KR ||
700 phy_types & I40E_CAP_PHY_TYPE_25GBASE_CR ||
701 phy_types & I40E_CAP_PHY_TYPE_20GBASE_KR2 ||
702 phy_types & I40E_CAP_PHY_TYPE_10GBASE_SR ||
703 phy_types & I40E_CAP_PHY_TYPE_10GBASE_LR ||
704 phy_types & I40E_CAP_PHY_TYPE_10GBASE_KX4 ||
705 phy_types & I40E_CAP_PHY_TYPE_10GBASE_KR ||
706 phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1_CU ||
707 phy_types & I40E_CAP_PHY_TYPE_10GBASE_CR1 ||
708 phy_types & I40E_CAP_PHY_TYPE_10GBASE_T ||
709 phy_types & I40E_CAP_PHY_TYPE_5GBASE_T ||
710 phy_types & I40E_CAP_PHY_TYPE_2_5GBASE_T ||
711 phy_types & I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL ||
712 phy_types & I40E_CAP_PHY_TYPE_1000BASE_T ||
713 phy_types & I40E_CAP_PHY_TYPE_1000BASE_SX ||
714 phy_types & I40E_CAP_PHY_TYPE_1000BASE_LX ||
715 phy_types & I40E_CAP_PHY_TYPE_1000BASE_KX ||
716 phy_types & I40E_CAP_PHY_TYPE_100BASE_TX) {
717 ethtool_link_ksettings_add_link_mode(ks, supported,
718 Autoneg);
719 ethtool_link_ksettings_add_link_mode(ks, advertising,
720 Autoneg);
721 }
722}
723
724
725
726
727
728
729static void i40e_get_settings_link_up_fec(u8 req_fec_info,
730 struct ethtool_link_ksettings *ks)
731{
732 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_NONE);
733 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_RS);
734 ethtool_link_ksettings_add_link_mode(ks, supported, FEC_BASER);
735
736 if ((I40E_AQ_SET_FEC_REQUEST_RS & req_fec_info) &&
737 (I40E_AQ_SET_FEC_REQUEST_KR & req_fec_info)) {
738 ethtool_link_ksettings_add_link_mode(ks, advertising,
739 FEC_NONE);
740 ethtool_link_ksettings_add_link_mode(ks, advertising,
741 FEC_BASER);
742 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS);
743 } else if (I40E_AQ_SET_FEC_REQUEST_RS & req_fec_info) {
744 ethtool_link_ksettings_add_link_mode(ks, advertising, FEC_RS);
745 } else if (I40E_AQ_SET_FEC_REQUEST_KR & req_fec_info) {
746 ethtool_link_ksettings_add_link_mode(ks, advertising,
747 FEC_BASER);
748 } else {
749 ethtool_link_ksettings_add_link_mode(ks, advertising,
750 FEC_NONE);
751 }
752}
753
754
755
756
757
758
759
760
761static void i40e_get_settings_link_up(struct i40e_hw *hw,
762 struct ethtool_link_ksettings *ks,
763 struct net_device *netdev,
764 struct i40e_pf *pf)
765{
766 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
767 struct ethtool_link_ksettings cap_ksettings;
768 u32 link_speed = hw_link_info->link_speed;
769
770
771 switch (hw_link_info->phy_type) {
772 case I40E_PHY_TYPE_40GBASE_CR4:
773 case I40E_PHY_TYPE_40GBASE_CR4_CU:
774 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
775 ethtool_link_ksettings_add_link_mode(ks, supported,
776 40000baseCR4_Full);
777 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
778 ethtool_link_ksettings_add_link_mode(ks, advertising,
779 40000baseCR4_Full);
780 break;
781 case I40E_PHY_TYPE_XLAUI:
782 case I40E_PHY_TYPE_XLPPI:
783 case I40E_PHY_TYPE_40GBASE_AOC:
784 ethtool_link_ksettings_add_link_mode(ks, supported,
785 40000baseCR4_Full);
786 ethtool_link_ksettings_add_link_mode(ks, advertising,
787 40000baseCR4_Full);
788 break;
789 case I40E_PHY_TYPE_40GBASE_SR4:
790 ethtool_link_ksettings_add_link_mode(ks, supported,
791 40000baseSR4_Full);
792 ethtool_link_ksettings_add_link_mode(ks, advertising,
793 40000baseSR4_Full);
794 break;
795 case I40E_PHY_TYPE_40GBASE_LR4:
796 ethtool_link_ksettings_add_link_mode(ks, supported,
797 40000baseLR4_Full);
798 ethtool_link_ksettings_add_link_mode(ks, advertising,
799 40000baseLR4_Full);
800 break;
801 case I40E_PHY_TYPE_25GBASE_SR:
802 case I40E_PHY_TYPE_25GBASE_LR:
803 case I40E_PHY_TYPE_10GBASE_SR:
804 case I40E_PHY_TYPE_10GBASE_LR:
805 case I40E_PHY_TYPE_1000BASE_SX:
806 case I40E_PHY_TYPE_1000BASE_LX:
807 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
808 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
809 ethtool_link_ksettings_add_link_mode(ks, supported,
810 25000baseSR_Full);
811 ethtool_link_ksettings_add_link_mode(ks, advertising,
812 25000baseSR_Full);
813 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
814 ethtool_link_ksettings_add_link_mode(ks, supported,
815 10000baseSR_Full);
816 ethtool_link_ksettings_add_link_mode(ks, advertising,
817 10000baseSR_Full);
818 ethtool_link_ksettings_add_link_mode(ks, supported,
819 10000baseLR_Full);
820 ethtool_link_ksettings_add_link_mode(ks, advertising,
821 10000baseLR_Full);
822 ethtool_link_ksettings_add_link_mode(ks, supported,
823 1000baseX_Full);
824 ethtool_link_ksettings_add_link_mode(ks, advertising,
825 1000baseX_Full);
826 ethtool_link_ksettings_add_link_mode(ks, supported,
827 10000baseT_Full);
828 if (hw_link_info->module_type[2] &
829 I40E_MODULE_TYPE_1000BASE_SX ||
830 hw_link_info->module_type[2] &
831 I40E_MODULE_TYPE_1000BASE_LX) {
832 ethtool_link_ksettings_add_link_mode(ks, supported,
833 1000baseT_Full);
834 if (hw_link_info->requested_speeds &
835 I40E_LINK_SPEED_1GB)
836 ethtool_link_ksettings_add_link_mode(
837 ks, advertising, 1000baseT_Full);
838 }
839 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
840 ethtool_link_ksettings_add_link_mode(ks, advertising,
841 10000baseT_Full);
842 break;
843 case I40E_PHY_TYPE_10GBASE_T:
844 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:
845 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:
846 case I40E_PHY_TYPE_1000BASE_T:
847 case I40E_PHY_TYPE_100BASE_TX:
848 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
849 ethtool_link_ksettings_add_link_mode(ks, supported,
850 10000baseT_Full);
851 ethtool_link_ksettings_add_link_mode(ks, supported,
852 5000baseT_Full);
853 ethtool_link_ksettings_add_link_mode(ks, supported,
854 2500baseT_Full);
855 ethtool_link_ksettings_add_link_mode(ks, supported,
856 1000baseT_Full);
857 ethtool_link_ksettings_add_link_mode(ks, supported,
858 100baseT_Full);
859 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
860 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
861 ethtool_link_ksettings_add_link_mode(ks, advertising,
862 10000baseT_Full);
863 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_5GB)
864 ethtool_link_ksettings_add_link_mode(ks, advertising,
865 5000baseT_Full);
866 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_2_5GB)
867 ethtool_link_ksettings_add_link_mode(ks, advertising,
868 2500baseT_Full);
869 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
870 ethtool_link_ksettings_add_link_mode(ks, advertising,
871 1000baseT_Full);
872 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_100MB)
873 ethtool_link_ksettings_add_link_mode(ks, advertising,
874 100baseT_Full);
875 break;
876 case I40E_PHY_TYPE_1000BASE_T_OPTICAL:
877 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
878 ethtool_link_ksettings_add_link_mode(ks, supported,
879 1000baseT_Full);
880 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
881 ethtool_link_ksettings_add_link_mode(ks, advertising,
882 1000baseT_Full);
883 break;
884 case I40E_PHY_TYPE_10GBASE_CR1_CU:
885 case I40E_PHY_TYPE_10GBASE_CR1:
886 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
887 ethtool_link_ksettings_add_link_mode(ks, supported,
888 10000baseT_Full);
889 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
890 ethtool_link_ksettings_add_link_mode(ks, advertising,
891 10000baseT_Full);
892 break;
893 case I40E_PHY_TYPE_XAUI:
894 case I40E_PHY_TYPE_XFI:
895 case I40E_PHY_TYPE_SFI:
896 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
897 case I40E_PHY_TYPE_10GBASE_AOC:
898 ethtool_link_ksettings_add_link_mode(ks, supported,
899 10000baseT_Full);
900 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
901 ethtool_link_ksettings_add_link_mode(ks, advertising,
902 10000baseT_Full);
903 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
904 break;
905 case I40E_PHY_TYPE_SGMII:
906 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
907 ethtool_link_ksettings_add_link_mode(ks, supported,
908 1000baseT_Full);
909 if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
910 ethtool_link_ksettings_add_link_mode(ks, advertising,
911 1000baseT_Full);
912 if (pf->hw_features & I40E_HW_100M_SGMII_CAPABLE) {
913 ethtool_link_ksettings_add_link_mode(ks, supported,
914 100baseT_Full);
915 if (hw_link_info->requested_speeds &
916 I40E_LINK_SPEED_100MB)
917 ethtool_link_ksettings_add_link_mode(
918 ks, advertising, 100baseT_Full);
919 }
920 break;
921 case I40E_PHY_TYPE_40GBASE_KR4:
922 case I40E_PHY_TYPE_25GBASE_KR:
923 case I40E_PHY_TYPE_20GBASE_KR2:
924 case I40E_PHY_TYPE_10GBASE_KR:
925 case I40E_PHY_TYPE_10GBASE_KX4:
926 case I40E_PHY_TYPE_1000BASE_KX:
927 ethtool_link_ksettings_add_link_mode(ks, supported,
928 40000baseKR4_Full);
929 ethtool_link_ksettings_add_link_mode(ks, supported,
930 25000baseKR_Full);
931 ethtool_link_ksettings_add_link_mode(ks, supported,
932 20000baseKR2_Full);
933 ethtool_link_ksettings_add_link_mode(ks, supported,
934 10000baseKR_Full);
935 ethtool_link_ksettings_add_link_mode(ks, supported,
936 10000baseKX4_Full);
937 ethtool_link_ksettings_add_link_mode(ks, supported,
938 1000baseKX_Full);
939 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
940 ethtool_link_ksettings_add_link_mode(ks, advertising,
941 40000baseKR4_Full);
942 ethtool_link_ksettings_add_link_mode(ks, advertising,
943 25000baseKR_Full);
944 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
945 ethtool_link_ksettings_add_link_mode(ks, advertising,
946 20000baseKR2_Full);
947 ethtool_link_ksettings_add_link_mode(ks, advertising,
948 10000baseKR_Full);
949 ethtool_link_ksettings_add_link_mode(ks, advertising,
950 10000baseKX4_Full);
951 ethtool_link_ksettings_add_link_mode(ks, advertising,
952 1000baseKX_Full);
953 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
954 break;
955 case I40E_PHY_TYPE_25GBASE_CR:
956 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
957 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
958 ethtool_link_ksettings_add_link_mode(ks, supported,
959 25000baseCR_Full);
960 ethtool_link_ksettings_add_link_mode(ks, advertising,
961 25000baseCR_Full);
962 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
963
964 break;
965 case I40E_PHY_TYPE_25GBASE_AOC:
966 case I40E_PHY_TYPE_25GBASE_ACC:
967 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
968 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
969 ethtool_link_ksettings_add_link_mode(ks, supported,
970 25000baseCR_Full);
971 ethtool_link_ksettings_add_link_mode(ks, advertising,
972 25000baseCR_Full);
973 i40e_get_settings_link_up_fec(hw_link_info->req_fec_info, ks);
974
975 ethtool_link_ksettings_add_link_mode(ks, supported,
976 10000baseCR_Full);
977 ethtool_link_ksettings_add_link_mode(ks, advertising,
978 10000baseCR_Full);
979 break;
980 default:
981
982 netdev_info(netdev,
983 "WARNING: Link is up but PHY type 0x%x is not recognized, or incorrect cable is in use\n",
984 hw_link_info->phy_type);
985 }
986
987
988
989
990
991 memset(&cap_ksettings, 0, sizeof(struct ethtool_link_ksettings));
992 i40e_phy_type_to_ethtool(pf, &cap_ksettings);
993 ethtool_intersect_link_masks(ks, &cap_ksettings);
994
995
996 switch (link_speed) {
997 case I40E_LINK_SPEED_40GB:
998 ks->base.speed = SPEED_40000;
999 break;
1000 case I40E_LINK_SPEED_25GB:
1001 ks->base.speed = SPEED_25000;
1002 break;
1003 case I40E_LINK_SPEED_20GB:
1004 ks->base.speed = SPEED_20000;
1005 break;
1006 case I40E_LINK_SPEED_10GB:
1007 ks->base.speed = SPEED_10000;
1008 break;
1009 case I40E_LINK_SPEED_5GB:
1010 ks->base.speed = SPEED_5000;
1011 break;
1012 case I40E_LINK_SPEED_2_5GB:
1013 ks->base.speed = SPEED_2500;
1014 break;
1015 case I40E_LINK_SPEED_1GB:
1016 ks->base.speed = SPEED_1000;
1017 break;
1018 case I40E_LINK_SPEED_100MB:
1019 ks->base.speed = SPEED_100;
1020 break;
1021 default:
1022 ks->base.speed = SPEED_UNKNOWN;
1023 break;
1024 }
1025 ks->base.duplex = DUPLEX_FULL;
1026}
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036static void i40e_get_settings_link_down(struct i40e_hw *hw,
1037 struct ethtool_link_ksettings *ks,
1038 struct i40e_pf *pf)
1039{
1040
1041
1042
1043 i40e_phy_type_to_ethtool(pf, ks);
1044
1045
1046 ks->base.speed = SPEED_UNKNOWN;
1047 ks->base.duplex = DUPLEX_UNKNOWN;
1048}
1049
1050
1051
1052
1053
1054
1055
1056
1057static int i40e_get_link_ksettings(struct net_device *netdev,
1058 struct ethtool_link_ksettings *ks)
1059{
1060 struct i40e_netdev_priv *np = netdev_priv(netdev);
1061 struct i40e_pf *pf = np->vsi->back;
1062 struct i40e_hw *hw = &pf->hw;
1063 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1064 bool link_up = hw_link_info->link_info & I40E_AQ_LINK_UP;
1065
1066 ethtool_link_ksettings_zero_link_mode(ks, supported);
1067 ethtool_link_ksettings_zero_link_mode(ks, advertising);
1068
1069 if (link_up)
1070 i40e_get_settings_link_up(hw, ks, netdev, pf);
1071 else
1072 i40e_get_settings_link_down(hw, ks, pf);
1073
1074
1075
1076 ks->base.autoneg = ((hw_link_info->an_info & I40E_AQ_AN_COMPLETED) ?
1077 AUTONEG_ENABLE : AUTONEG_DISABLE);
1078
1079
1080 switch (hw->phy.media_type) {
1081 case I40E_MEDIA_TYPE_BACKPLANE:
1082 ethtool_link_ksettings_add_link_mode(ks, supported, Autoneg);
1083 ethtool_link_ksettings_add_link_mode(ks, supported, Backplane);
1084 ethtool_link_ksettings_add_link_mode(ks, advertising, Autoneg);
1085 ethtool_link_ksettings_add_link_mode(ks, advertising,
1086 Backplane);
1087 ks->base.port = PORT_NONE;
1088 break;
1089 case I40E_MEDIA_TYPE_BASET:
1090 ethtool_link_ksettings_add_link_mode(ks, supported, TP);
1091 ethtool_link_ksettings_add_link_mode(ks, advertising, TP);
1092 ks->base.port = PORT_TP;
1093 break;
1094 case I40E_MEDIA_TYPE_DA:
1095 case I40E_MEDIA_TYPE_CX4:
1096 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
1097 ethtool_link_ksettings_add_link_mode(ks, advertising, FIBRE);
1098 ks->base.port = PORT_DA;
1099 break;
1100 case I40E_MEDIA_TYPE_FIBER:
1101 ethtool_link_ksettings_add_link_mode(ks, supported, FIBRE);
1102 ethtool_link_ksettings_add_link_mode(ks, advertising, FIBRE);
1103 ks->base.port = PORT_FIBRE;
1104 break;
1105 case I40E_MEDIA_TYPE_UNKNOWN:
1106 default:
1107 ks->base.port = PORT_OTHER;
1108 break;
1109 }
1110
1111
1112 ethtool_link_ksettings_add_link_mode(ks, supported, Pause);
1113 ethtool_link_ksettings_add_link_mode(ks, supported, Asym_Pause);
1114
1115 switch (hw->fc.requested_mode) {
1116 case I40E_FC_FULL:
1117 ethtool_link_ksettings_add_link_mode(ks, advertising, Pause);
1118 break;
1119 case I40E_FC_TX_PAUSE:
1120 ethtool_link_ksettings_add_link_mode(ks, advertising,
1121 Asym_Pause);
1122 break;
1123 case I40E_FC_RX_PAUSE:
1124 ethtool_link_ksettings_add_link_mode(ks, advertising, Pause);
1125 ethtool_link_ksettings_add_link_mode(ks, advertising,
1126 Asym_Pause);
1127 break;
1128 default:
1129 ethtool_link_ksettings_del_link_mode(ks, advertising, Pause);
1130 ethtool_link_ksettings_del_link_mode(ks, advertising,
1131 Asym_Pause);
1132 break;
1133 }
1134
1135 return 0;
1136}
1137
1138
1139
1140
1141
1142
1143
1144
1145static int i40e_set_link_ksettings(struct net_device *netdev,
1146 const struct ethtool_link_ksettings *ks)
1147{
1148 struct i40e_netdev_priv *np = netdev_priv(netdev);
1149 struct i40e_aq_get_phy_abilities_resp abilities;
1150 struct ethtool_link_ksettings safe_ks;
1151 struct ethtool_link_ksettings copy_ks;
1152 struct i40e_aq_set_phy_config config;
1153 struct i40e_pf *pf = np->vsi->back;
1154 struct i40e_vsi *vsi = np->vsi;
1155 struct i40e_hw *hw = &pf->hw;
1156 bool autoneg_changed = false;
1157 i40e_status status = 0;
1158 int timeout = 50;
1159 int err = 0;
1160 u8 autoneg;
1161
1162
1163
1164
1165 if (hw->partition_id != 1) {
1166 i40e_partition_setting_complaint(pf);
1167 return -EOPNOTSUPP;
1168 }
1169 if (vsi != pf->vsi[pf->lan_vsi])
1170 return -EOPNOTSUPP;
1171 if (hw->phy.media_type != I40E_MEDIA_TYPE_BASET &&
1172 hw->phy.media_type != I40E_MEDIA_TYPE_FIBER &&
1173 hw->phy.media_type != I40E_MEDIA_TYPE_BACKPLANE &&
1174 hw->phy.media_type != I40E_MEDIA_TYPE_DA &&
1175 hw->phy.link_info.link_info & I40E_AQ_LINK_UP)
1176 return -EOPNOTSUPP;
1177 if (hw->device_id == I40E_DEV_ID_KX_B ||
1178 hw->device_id == I40E_DEV_ID_KX_C ||
1179 hw->device_id == I40E_DEV_ID_20G_KR2 ||
1180 hw->device_id == I40E_DEV_ID_20G_KR2_A ||
1181 hw->device_id == I40E_DEV_ID_25G_B ||
1182 hw->device_id == I40E_DEV_ID_KX_X722) {
1183 netdev_info(netdev, "Changing settings is not supported on backplane.\n");
1184 return -EOPNOTSUPP;
1185 }
1186
1187
1188 memcpy(©_ks, ks, sizeof(struct ethtool_link_ksettings));
1189
1190
1191 autoneg = copy_ks.base.autoneg;
1192
1193
1194 memset(&safe_ks, 0, sizeof(struct ethtool_link_ksettings));
1195 safe_ks.base.cmd = copy_ks.base.cmd;
1196 safe_ks.base.link_mode_masks_nwords =
1197 copy_ks.base.link_mode_masks_nwords;
1198 i40e_get_link_ksettings(netdev, &safe_ks);
1199
1200
1201
1202
1203 if (!bitmap_subset(copy_ks.link_modes.advertising,
1204 safe_ks.link_modes.supported,
1205 __ETHTOOL_LINK_MODE_MASK_NBITS))
1206 return -EINVAL;
1207
1208
1209 copy_ks.base.autoneg = safe_ks.base.autoneg;
1210
1211
1212
1213
1214 if (memcmp(©_ks.base, &safe_ks.base,
1215 sizeof(struct ethtool_link_settings)))
1216 return -EOPNOTSUPP;
1217
1218 while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) {
1219 timeout--;
1220 if (!timeout)
1221 return -EBUSY;
1222 usleep_range(1000, 2000);
1223 }
1224
1225
1226 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1227 NULL);
1228 if (status) {
1229 err = -EAGAIN;
1230 goto done;
1231 }
1232
1233
1234
1235
1236 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1237 config.abilities = abilities.abilities;
1238
1239
1240 if (autoneg == AUTONEG_ENABLE) {
1241
1242 if (!(hw->phy.link_info.an_info & I40E_AQ_AN_COMPLETED)) {
1243
1244 if (!ethtool_link_ksettings_test_link_mode(&safe_ks,
1245 supported,
1246 Autoneg)) {
1247 netdev_info(netdev, "Autoneg not supported on this phy\n");
1248 err = -EINVAL;
1249 goto done;
1250 }
1251
1252 config.abilities = abilities.abilities |
1253 I40E_AQ_PHY_ENABLE_AN;
1254 autoneg_changed = true;
1255 }
1256 } else {
1257
1258 if (hw->phy.link_info.an_info & I40E_AQ_AN_COMPLETED) {
1259
1260
1261
1262 if (ethtool_link_ksettings_test_link_mode(&safe_ks,
1263 supported,
1264 Autoneg) &&
1265 hw->phy.media_type != I40E_MEDIA_TYPE_BASET) {
1266 netdev_info(netdev, "Autoneg cannot be disabled on this phy\n");
1267 err = -EINVAL;
1268 goto done;
1269 }
1270
1271 config.abilities = abilities.abilities &
1272 ~I40E_AQ_PHY_ENABLE_AN;
1273 autoneg_changed = true;
1274 }
1275 }
1276
1277 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1278 100baseT_Full))
1279 config.link_speed |= I40E_LINK_SPEED_100MB;
1280 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1281 1000baseT_Full) ||
1282 ethtool_link_ksettings_test_link_mode(ks, advertising,
1283 1000baseX_Full) ||
1284 ethtool_link_ksettings_test_link_mode(ks, advertising,
1285 1000baseKX_Full))
1286 config.link_speed |= I40E_LINK_SPEED_1GB;
1287 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1288 10000baseT_Full) ||
1289 ethtool_link_ksettings_test_link_mode(ks, advertising,
1290 10000baseKX4_Full) ||
1291 ethtool_link_ksettings_test_link_mode(ks, advertising,
1292 10000baseKR_Full) ||
1293 ethtool_link_ksettings_test_link_mode(ks, advertising,
1294 10000baseCR_Full) ||
1295 ethtool_link_ksettings_test_link_mode(ks, advertising,
1296 10000baseSR_Full) ||
1297 ethtool_link_ksettings_test_link_mode(ks, advertising,
1298 10000baseLR_Full))
1299 config.link_speed |= I40E_LINK_SPEED_10GB;
1300 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1301 2500baseT_Full))
1302 config.link_speed |= I40E_LINK_SPEED_2_5GB;
1303 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1304 5000baseT_Full))
1305 config.link_speed |= I40E_LINK_SPEED_5GB;
1306 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1307 20000baseKR2_Full))
1308 config.link_speed |= I40E_LINK_SPEED_20GB;
1309 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1310 25000baseCR_Full) ||
1311 ethtool_link_ksettings_test_link_mode(ks, advertising,
1312 25000baseKR_Full) ||
1313 ethtool_link_ksettings_test_link_mode(ks, advertising,
1314 25000baseSR_Full))
1315 config.link_speed |= I40E_LINK_SPEED_25GB;
1316 if (ethtool_link_ksettings_test_link_mode(ks, advertising,
1317 40000baseKR4_Full) ||
1318 ethtool_link_ksettings_test_link_mode(ks, advertising,
1319 40000baseCR4_Full) ||
1320 ethtool_link_ksettings_test_link_mode(ks, advertising,
1321 40000baseSR4_Full) ||
1322 ethtool_link_ksettings_test_link_mode(ks, advertising,
1323 40000baseLR4_Full))
1324 config.link_speed |= I40E_LINK_SPEED_40GB;
1325
1326
1327
1328
1329
1330 if (!config.link_speed)
1331 config.link_speed = abilities.link_speed;
1332 if (autoneg_changed || abilities.link_speed != config.link_speed) {
1333
1334 config.phy_type = abilities.phy_type;
1335 config.phy_type_ext = abilities.phy_type_ext;
1336 config.eee_capability = abilities.eee_capability;
1337 config.eeer = abilities.eeer_val;
1338 config.low_power_ctrl = abilities.d3_lpan;
1339 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
1340 I40E_AQ_PHY_FEC_CONFIG_MASK;
1341
1342
1343 hw->phy.link_info.requested_speeds = config.link_speed;
1344
1345 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1346
1347 if (hw->phy.link_info.link_info & I40E_AQ_LINK_UP) {
1348
1349
1350
1351 i40e_print_link_message(vsi, false);
1352 netif_carrier_off(netdev);
1353 netif_tx_stop_all_queues(netdev);
1354 }
1355
1356
1357 status = i40e_aq_set_phy_config(hw, &config, NULL);
1358 if (status) {
1359 netdev_info(netdev,
1360 "Set phy config failed, err %s aq_err %s\n",
1361 i40e_stat_str(hw, status),
1362 i40e_aq_str(hw, hw->aq.asq_last_status));
1363 err = -EAGAIN;
1364 goto done;
1365 }
1366
1367 status = i40e_update_link_info(hw);
1368 if (status)
1369 netdev_dbg(netdev,
1370 "Updating link info failed with err %s aq_err %s\n",
1371 i40e_stat_str(hw, status),
1372 i40e_aq_str(hw, hw->aq.asq_last_status));
1373
1374 } else {
1375 netdev_info(netdev, "Nothing changed, exiting without setting anything.\n");
1376 }
1377
1378done:
1379 clear_bit(__I40E_CONFIG_BUSY, pf->state);
1380
1381 return err;
1382}
1383
1384static int i40e_set_fec_cfg(struct net_device *netdev, u8 fec_cfg)
1385{
1386 struct i40e_netdev_priv *np = netdev_priv(netdev);
1387 struct i40e_aq_get_phy_abilities_resp abilities;
1388 struct i40e_pf *pf = np->vsi->back;
1389 struct i40e_hw *hw = &pf->hw;
1390 i40e_status status = 0;
1391 u32 flags = 0;
1392 int err = 0;
1393
1394 flags = READ_ONCE(pf->flags);
1395 i40e_set_fec_in_flags(fec_cfg, &flags);
1396
1397
1398 memset(&abilities, 0, sizeof(abilities));
1399 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1400 NULL);
1401 if (status) {
1402 err = -EAGAIN;
1403 goto done;
1404 }
1405
1406 if (abilities.fec_cfg_curr_mod_ext_info != fec_cfg) {
1407 struct i40e_aq_set_phy_config config;
1408
1409 memset(&config, 0, sizeof(config));
1410 config.phy_type = abilities.phy_type;
1411 config.abilities = abilities.abilities |
1412 I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1413 config.phy_type_ext = abilities.phy_type_ext;
1414 config.link_speed = abilities.link_speed;
1415 config.eee_capability = abilities.eee_capability;
1416 config.eeer = abilities.eeer_val;
1417 config.low_power_ctrl = abilities.d3_lpan;
1418 config.fec_config = fec_cfg & I40E_AQ_PHY_FEC_CONFIG_MASK;
1419 status = i40e_aq_set_phy_config(hw, &config, NULL);
1420 if (status) {
1421 netdev_info(netdev,
1422 "Set phy config failed, err %s aq_err %s\n",
1423 i40e_stat_str(hw, status),
1424 i40e_aq_str(hw, hw->aq.asq_last_status));
1425 err = -EAGAIN;
1426 goto done;
1427 }
1428 pf->flags = flags;
1429 status = i40e_update_link_info(hw);
1430 if (status)
1431
1432
1433
1434
1435 netdev_dbg(netdev,
1436 "Updating link info failed with err %s aq_err %s\n",
1437 i40e_stat_str(hw, status),
1438 i40e_aq_str(hw, hw->aq.asq_last_status));
1439 }
1440
1441done:
1442 return err;
1443}
1444
1445static int i40e_get_fec_param(struct net_device *netdev,
1446 struct ethtool_fecparam *fecparam)
1447{
1448 struct i40e_netdev_priv *np = netdev_priv(netdev);
1449 struct i40e_aq_get_phy_abilities_resp abilities;
1450 struct i40e_pf *pf = np->vsi->back;
1451 struct i40e_hw *hw = &pf->hw;
1452 i40e_status status = 0;
1453 int err = 0;
1454 u8 fec_cfg;
1455
1456
1457 memset(&abilities, 0, sizeof(abilities));
1458 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1459 NULL);
1460 if (status) {
1461 err = -EAGAIN;
1462 goto done;
1463 }
1464
1465 fecparam->fec = 0;
1466 fec_cfg = abilities.fec_cfg_curr_mod_ext_info;
1467 if (fec_cfg & I40E_AQ_SET_FEC_AUTO)
1468 fecparam->fec |= ETHTOOL_FEC_AUTO;
1469 else if (fec_cfg & (I40E_AQ_SET_FEC_REQUEST_RS |
1470 I40E_AQ_SET_FEC_ABILITY_RS))
1471 fecparam->fec |= ETHTOOL_FEC_RS;
1472 else if (fec_cfg & (I40E_AQ_SET_FEC_REQUEST_KR |
1473 I40E_AQ_SET_FEC_ABILITY_KR))
1474 fecparam->fec |= ETHTOOL_FEC_BASER;
1475 if (fec_cfg == 0)
1476 fecparam->fec |= ETHTOOL_FEC_OFF;
1477
1478 if (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_KR_ENA)
1479 fecparam->active_fec = ETHTOOL_FEC_BASER;
1480 else if (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_RS_ENA)
1481 fecparam->active_fec = ETHTOOL_FEC_RS;
1482 else
1483 fecparam->active_fec = ETHTOOL_FEC_OFF;
1484done:
1485 return err;
1486}
1487
1488static int i40e_set_fec_param(struct net_device *netdev,
1489 struct ethtool_fecparam *fecparam)
1490{
1491 struct i40e_netdev_priv *np = netdev_priv(netdev);
1492 struct i40e_pf *pf = np->vsi->back;
1493 struct i40e_hw *hw = &pf->hw;
1494 u8 fec_cfg = 0;
1495
1496 if (hw->device_id != I40E_DEV_ID_25G_SFP28 &&
1497 hw->device_id != I40E_DEV_ID_25G_B &&
1498 hw->device_id != I40E_DEV_ID_KX_X722)
1499 return -EPERM;
1500
1501 if (hw->mac.type == I40E_MAC_X722 &&
1502 !(hw->flags & I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE)) {
1503 netdev_err(netdev, "Setting FEC encoding not supported by firmware. Please update the NVM image.\n");
1504 return -EOPNOTSUPP;
1505 }
1506
1507 switch (fecparam->fec) {
1508 case ETHTOOL_FEC_AUTO:
1509 fec_cfg = I40E_AQ_SET_FEC_AUTO;
1510 break;
1511 case ETHTOOL_FEC_RS:
1512 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_RS |
1513 I40E_AQ_SET_FEC_ABILITY_RS);
1514 break;
1515 case ETHTOOL_FEC_BASER:
1516 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_KR |
1517 I40E_AQ_SET_FEC_ABILITY_KR);
1518 break;
1519 case ETHTOOL_FEC_OFF:
1520 case ETHTOOL_FEC_NONE:
1521 fec_cfg = 0;
1522 break;
1523 default:
1524 dev_warn(&pf->pdev->dev, "Unsupported FEC mode: %d",
1525 fecparam->fec);
1526 return -EINVAL;
1527 }
1528
1529 return i40e_set_fec_cfg(netdev, fec_cfg);
1530}
1531
1532static int i40e_nway_reset(struct net_device *netdev)
1533{
1534
1535 struct i40e_netdev_priv *np = netdev_priv(netdev);
1536 struct i40e_pf *pf = np->vsi->back;
1537 struct i40e_hw *hw = &pf->hw;
1538 bool link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1539 i40e_status ret = 0;
1540
1541 ret = i40e_aq_set_link_restart_an(hw, link_up, NULL);
1542 if (ret) {
1543 netdev_info(netdev, "link restart failed, err %s aq_err %s\n",
1544 i40e_stat_str(hw, ret),
1545 i40e_aq_str(hw, hw->aq.asq_last_status));
1546 return -EIO;
1547 }
1548
1549 return 0;
1550}
1551
1552
1553
1554
1555
1556
1557
1558
1559static void i40e_get_pauseparam(struct net_device *netdev,
1560 struct ethtool_pauseparam *pause)
1561{
1562 struct i40e_netdev_priv *np = netdev_priv(netdev);
1563 struct i40e_pf *pf = np->vsi->back;
1564 struct i40e_hw *hw = &pf->hw;
1565 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1566 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
1567
1568 pause->autoneg =
1569 ((hw_link_info->an_info & I40E_AQ_AN_COMPLETED) ?
1570 AUTONEG_ENABLE : AUTONEG_DISABLE);
1571
1572
1573 if (dcbx_cfg->pfc.pfcenable) {
1574 pause->rx_pause = 0;
1575 pause->tx_pause = 0;
1576 return;
1577 }
1578
1579 if (hw->fc.current_mode == I40E_FC_RX_PAUSE) {
1580 pause->rx_pause = 1;
1581 } else if (hw->fc.current_mode == I40E_FC_TX_PAUSE) {
1582 pause->tx_pause = 1;
1583 } else if (hw->fc.current_mode == I40E_FC_FULL) {
1584 pause->rx_pause = 1;
1585 pause->tx_pause = 1;
1586 }
1587}
1588
1589
1590
1591
1592
1593
1594static int i40e_set_pauseparam(struct net_device *netdev,
1595 struct ethtool_pauseparam *pause)
1596{
1597 struct i40e_netdev_priv *np = netdev_priv(netdev);
1598 struct i40e_pf *pf = np->vsi->back;
1599 struct i40e_vsi *vsi = np->vsi;
1600 struct i40e_hw *hw = &pf->hw;
1601 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1602 struct i40e_dcbx_config *dcbx_cfg = &hw->local_dcbx_config;
1603 bool link_up = hw_link_info->link_info & I40E_AQ_LINK_UP;
1604 i40e_status status;
1605 u8 aq_failures;
1606 int err = 0;
1607 u32 is_an;
1608
1609
1610
1611
1612 if (hw->partition_id != 1) {
1613 i40e_partition_setting_complaint(pf);
1614 return -EOPNOTSUPP;
1615 }
1616
1617 if (vsi != pf->vsi[pf->lan_vsi])
1618 return -EOPNOTSUPP;
1619
1620 is_an = hw_link_info->an_info & I40E_AQ_AN_COMPLETED;
1621 if (pause->autoneg != is_an) {
1622 netdev_info(netdev, "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
1623 return -EOPNOTSUPP;
1624 }
1625
1626
1627 if (!test_bit(__I40E_DOWN, pf->state) && !is_an) {
1628
1629 netdev_info(netdev, "Autoneg did not complete so changing settings may not result in an actual change.\n");
1630 }
1631
1632 if (dcbx_cfg->pfc.pfcenable) {
1633 netdev_info(netdev,
1634 "Priority flow control enabled. Cannot set link flow control.\n");
1635 return -EOPNOTSUPP;
1636 }
1637
1638 if (pause->rx_pause && pause->tx_pause)
1639 hw->fc.requested_mode = I40E_FC_FULL;
1640 else if (pause->rx_pause && !pause->tx_pause)
1641 hw->fc.requested_mode = I40E_FC_RX_PAUSE;
1642 else if (!pause->rx_pause && pause->tx_pause)
1643 hw->fc.requested_mode = I40E_FC_TX_PAUSE;
1644 else if (!pause->rx_pause && !pause->tx_pause)
1645 hw->fc.requested_mode = I40E_FC_NONE;
1646 else
1647 return -EINVAL;
1648
1649
1650
1651
1652 i40e_print_link_message(vsi, false);
1653 netif_carrier_off(netdev);
1654 netif_tx_stop_all_queues(netdev);
1655
1656
1657 status = i40e_set_fc(hw, &aq_failures, link_up);
1658
1659 if (aq_failures & I40E_SET_FC_AQ_FAIL_GET) {
1660 netdev_info(netdev, "Set fc failed on the get_phy_capabilities call with err %s aq_err %s\n",
1661 i40e_stat_str(hw, status),
1662 i40e_aq_str(hw, hw->aq.asq_last_status));
1663 err = -EAGAIN;
1664 }
1665 if (aq_failures & I40E_SET_FC_AQ_FAIL_SET) {
1666 netdev_info(netdev, "Set fc failed on the set_phy_config call with err %s aq_err %s\n",
1667 i40e_stat_str(hw, status),
1668 i40e_aq_str(hw, hw->aq.asq_last_status));
1669 err = -EAGAIN;
1670 }
1671 if (aq_failures & I40E_SET_FC_AQ_FAIL_UPDATE) {
1672 netdev_info(netdev, "Set fc failed on the get_link_info call with err %s aq_err %s\n",
1673 i40e_stat_str(hw, status),
1674 i40e_aq_str(hw, hw->aq.asq_last_status));
1675 err = -EAGAIN;
1676 }
1677
1678 if (!test_bit(__I40E_DOWN, pf->state) && is_an) {
1679
1680 msleep(75);
1681 if (!test_bit(__I40E_DOWN, pf->state))
1682 return i40e_nway_reset(netdev);
1683 }
1684
1685 return err;
1686}
1687
1688static u32 i40e_get_msglevel(struct net_device *netdev)
1689{
1690 struct i40e_netdev_priv *np = netdev_priv(netdev);
1691 struct i40e_pf *pf = np->vsi->back;
1692 u32 debug_mask = pf->hw.debug_mask;
1693
1694 if (debug_mask)
1695 netdev_info(netdev, "i40e debug_mask: 0x%08X\n", debug_mask);
1696
1697 return pf->msg_enable;
1698}
1699
1700static void i40e_set_msglevel(struct net_device *netdev, u32 data)
1701{
1702 struct i40e_netdev_priv *np = netdev_priv(netdev);
1703 struct i40e_pf *pf = np->vsi->back;
1704
1705 if (I40E_DEBUG_USER & data)
1706 pf->hw.debug_mask = data;
1707 else
1708 pf->msg_enable = data;
1709}
1710
1711static int i40e_get_regs_len(struct net_device *netdev)
1712{
1713 int reg_count = 0;
1714 int i;
1715
1716 for (i = 0; i40e_reg_list[i].offset != 0; i++)
1717 reg_count += i40e_reg_list[i].elements;
1718
1719 return reg_count * sizeof(u32);
1720}
1721
1722static void i40e_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
1723 void *p)
1724{
1725 struct i40e_netdev_priv *np = netdev_priv(netdev);
1726 struct i40e_pf *pf = np->vsi->back;
1727 struct i40e_hw *hw = &pf->hw;
1728 u32 *reg_buf = p;
1729 unsigned int i, j, ri;
1730 u32 reg;
1731
1732
1733
1734
1735
1736
1737
1738
1739 regs->version = 1;
1740
1741
1742 ri = 0;
1743 for (i = 0; i40e_reg_list[i].offset != 0; i++) {
1744 for (j = 0; j < i40e_reg_list[i].elements; j++) {
1745 reg = i40e_reg_list[i].offset
1746 + (j * i40e_reg_list[i].stride);
1747 reg_buf[ri++] = rd32(hw, reg);
1748 }
1749 }
1750
1751}
1752
1753static int i40e_get_eeprom(struct net_device *netdev,
1754 struct ethtool_eeprom *eeprom, u8 *bytes)
1755{
1756 struct i40e_netdev_priv *np = netdev_priv(netdev);
1757 struct i40e_hw *hw = &np->vsi->back->hw;
1758 struct i40e_pf *pf = np->vsi->back;
1759 int ret_val = 0, len, offset;
1760 u8 *eeprom_buff;
1761 u16 i, sectors;
1762 bool last;
1763 u32 magic;
1764
1765#define I40E_NVM_SECTOR_SIZE 4096
1766 if (eeprom->len == 0)
1767 return -EINVAL;
1768
1769
1770 magic = hw->vendor_id | (hw->device_id << 16);
1771 if (eeprom->magic && eeprom->magic != magic) {
1772 struct i40e_nvm_access *cmd = (struct i40e_nvm_access *)eeprom;
1773 int errno = 0;
1774
1775
1776 if ((eeprom->magic >> 16) != hw->device_id)
1777 errno = -EINVAL;
1778 else if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
1779 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
1780 errno = -EBUSY;
1781 else
1782 ret_val = i40e_nvmupd_command(hw, cmd, bytes, &errno);
1783
1784 if ((errno || ret_val) && (hw->debug_mask & I40E_DEBUG_NVM))
1785 dev_info(&pf->pdev->dev,
1786 "NVMUpdate read failed err=%d status=0x%x errno=%d module=%d offset=0x%x size=%d\n",
1787 ret_val, hw->aq.asq_last_status, errno,
1788 (u8)(cmd->config & I40E_NVM_MOD_PNT_MASK),
1789 cmd->offset, cmd->data_size);
1790
1791 return errno;
1792 }
1793
1794
1795 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
1796
1797 eeprom_buff = kzalloc(eeprom->len, GFP_KERNEL);
1798 if (!eeprom_buff)
1799 return -ENOMEM;
1800
1801 ret_val = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
1802 if (ret_val) {
1803 dev_info(&pf->pdev->dev,
1804 "Failed Acquiring NVM resource for read err=%d status=0x%x\n",
1805 ret_val, hw->aq.asq_last_status);
1806 goto free_buff;
1807 }
1808
1809 sectors = eeprom->len / I40E_NVM_SECTOR_SIZE;
1810 sectors += (eeprom->len % I40E_NVM_SECTOR_SIZE) ? 1 : 0;
1811 len = I40E_NVM_SECTOR_SIZE;
1812 last = false;
1813 for (i = 0; i < sectors; i++) {
1814 if (i == (sectors - 1)) {
1815 len = eeprom->len - (I40E_NVM_SECTOR_SIZE * i);
1816 last = true;
1817 }
1818 offset = eeprom->offset + (I40E_NVM_SECTOR_SIZE * i),
1819 ret_val = i40e_aq_read_nvm(hw, 0x0, offset, len,
1820 (u8 *)eeprom_buff + (I40E_NVM_SECTOR_SIZE * i),
1821 last, NULL);
1822 if (ret_val && hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
1823 dev_info(&pf->pdev->dev,
1824 "read NVM failed, invalid offset 0x%x\n",
1825 offset);
1826 break;
1827 } else if (ret_val &&
1828 hw->aq.asq_last_status == I40E_AQ_RC_EACCES) {
1829 dev_info(&pf->pdev->dev,
1830 "read NVM failed, access, offset 0x%x\n",
1831 offset);
1832 break;
1833 } else if (ret_val) {
1834 dev_info(&pf->pdev->dev,
1835 "read NVM failed offset %d err=%d status=0x%x\n",
1836 offset, ret_val, hw->aq.asq_last_status);
1837 break;
1838 }
1839 }
1840
1841 i40e_release_nvm(hw);
1842 memcpy(bytes, (u8 *)eeprom_buff, eeprom->len);
1843free_buff:
1844 kfree(eeprom_buff);
1845 return ret_val;
1846}
1847
1848static int i40e_get_eeprom_len(struct net_device *netdev)
1849{
1850 struct i40e_netdev_priv *np = netdev_priv(netdev);
1851 struct i40e_hw *hw = &np->vsi->back->hw;
1852 u32 val;
1853
1854#define X722_EEPROM_SCOPE_LIMIT 0x5B9FFF
1855 if (hw->mac.type == I40E_MAC_X722) {
1856 val = X722_EEPROM_SCOPE_LIMIT + 1;
1857 return val;
1858 }
1859 val = (rd32(hw, I40E_GLPCI_LBARCTRL)
1860 & I40E_GLPCI_LBARCTRL_FL_SIZE_MASK)
1861 >> I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT;
1862
1863 val = (64 * 1024) * BIT(val);
1864 return val;
1865}
1866
1867static int i40e_set_eeprom(struct net_device *netdev,
1868 struct ethtool_eeprom *eeprom, u8 *bytes)
1869{
1870 struct i40e_netdev_priv *np = netdev_priv(netdev);
1871 struct i40e_hw *hw = &np->vsi->back->hw;
1872 struct i40e_pf *pf = np->vsi->back;
1873 struct i40e_nvm_access *cmd = (struct i40e_nvm_access *)eeprom;
1874 int ret_val = 0;
1875 int errno = 0;
1876 u32 magic;
1877
1878
1879 magic = hw->vendor_id | (hw->device_id << 16);
1880 if (eeprom->magic == magic)
1881 errno = -EOPNOTSUPP;
1882
1883 else if (!eeprom->magic || (eeprom->magic >> 16) != hw->device_id)
1884 errno = -EINVAL;
1885 else if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
1886 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
1887 errno = -EBUSY;
1888 else
1889 ret_val = i40e_nvmupd_command(hw, cmd, bytes, &errno);
1890
1891 if ((errno || ret_val) && (hw->debug_mask & I40E_DEBUG_NVM))
1892 dev_info(&pf->pdev->dev,
1893 "NVMUpdate write failed err=%d status=0x%x errno=%d module=%d offset=0x%x size=%d\n",
1894 ret_val, hw->aq.asq_last_status, errno,
1895 (u8)(cmd->config & I40E_NVM_MOD_PNT_MASK),
1896 cmd->offset, cmd->data_size);
1897
1898 return errno;
1899}
1900
1901static void i40e_get_drvinfo(struct net_device *netdev,
1902 struct ethtool_drvinfo *drvinfo)
1903{
1904 struct i40e_netdev_priv *np = netdev_priv(netdev);
1905 struct i40e_vsi *vsi = np->vsi;
1906 struct i40e_pf *pf = vsi->back;
1907
1908 strlcpy(drvinfo->driver, i40e_driver_name, sizeof(drvinfo->driver));
1909 strlcpy(drvinfo->fw_version, i40e_nvm_version_str(&pf->hw),
1910 sizeof(drvinfo->fw_version));
1911 strlcpy(drvinfo->bus_info, pci_name(pf->pdev),
1912 sizeof(drvinfo->bus_info));
1913 drvinfo->n_priv_flags = I40E_PRIV_FLAGS_STR_LEN;
1914 if (pf->hw.pf_id == 0)
1915 drvinfo->n_priv_flags += I40E_GL_PRIV_FLAGS_STR_LEN;
1916}
1917
1918static void i40e_get_ringparam(struct net_device *netdev,
1919 struct ethtool_ringparam *ring)
1920{
1921 struct i40e_netdev_priv *np = netdev_priv(netdev);
1922 struct i40e_pf *pf = np->vsi->back;
1923 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
1924
1925 ring->rx_max_pending = I40E_MAX_NUM_DESCRIPTORS;
1926 ring->tx_max_pending = I40E_MAX_NUM_DESCRIPTORS;
1927 ring->rx_mini_max_pending = 0;
1928 ring->rx_jumbo_max_pending = 0;
1929 ring->rx_pending = vsi->rx_rings[0]->count;
1930 ring->tx_pending = vsi->tx_rings[0]->count;
1931 ring->rx_mini_pending = 0;
1932 ring->rx_jumbo_pending = 0;
1933}
1934
1935static bool i40e_active_tx_ring_index(struct i40e_vsi *vsi, u16 index)
1936{
1937 if (i40e_enabled_xdp_vsi(vsi)) {
1938 return index < vsi->num_queue_pairs ||
1939 (index >= vsi->alloc_queue_pairs &&
1940 index < vsi->alloc_queue_pairs + vsi->num_queue_pairs);
1941 }
1942
1943 return index < vsi->num_queue_pairs;
1944}
1945
1946static int i40e_set_ringparam(struct net_device *netdev,
1947 struct ethtool_ringparam *ring)
1948{
1949 struct i40e_ring *tx_rings = NULL, *rx_rings = NULL;
1950 struct i40e_netdev_priv *np = netdev_priv(netdev);
1951 struct i40e_hw *hw = &np->vsi->back->hw;
1952 struct i40e_vsi *vsi = np->vsi;
1953 struct i40e_pf *pf = vsi->back;
1954 u32 new_rx_count, new_tx_count;
1955 u16 tx_alloc_queue_pairs;
1956 int timeout = 50;
1957 int i, err = 0;
1958
1959 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
1960 return -EINVAL;
1961
1962 if (ring->tx_pending > I40E_MAX_NUM_DESCRIPTORS ||
1963 ring->tx_pending < I40E_MIN_NUM_DESCRIPTORS ||
1964 ring->rx_pending > I40E_MAX_NUM_DESCRIPTORS ||
1965 ring->rx_pending < I40E_MIN_NUM_DESCRIPTORS) {
1966 netdev_info(netdev,
1967 "Descriptors requested (Tx: %d / Rx: %d) out of range [%d-%d]\n",
1968 ring->tx_pending, ring->rx_pending,
1969 I40E_MIN_NUM_DESCRIPTORS, I40E_MAX_NUM_DESCRIPTORS);
1970 return -EINVAL;
1971 }
1972
1973 new_tx_count = ALIGN(ring->tx_pending, I40E_REQ_DESCRIPTOR_MULTIPLE);
1974 new_rx_count = ALIGN(ring->rx_pending, I40E_REQ_DESCRIPTOR_MULTIPLE);
1975
1976
1977 if ((new_tx_count == vsi->tx_rings[0]->count) &&
1978 (new_rx_count == vsi->rx_rings[0]->count))
1979 return 0;
1980
1981
1982
1983
1984
1985 if (i40e_xsk_any_rx_ring_enabled(vsi))
1986 return -EBUSY;
1987
1988 while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) {
1989 timeout--;
1990 if (!timeout)
1991 return -EBUSY;
1992 usleep_range(1000, 2000);
1993 }
1994
1995 if (!netif_running(vsi->netdev)) {
1996
1997 for (i = 0; i < vsi->num_queue_pairs; i++) {
1998 vsi->tx_rings[i]->count = new_tx_count;
1999 vsi->rx_rings[i]->count = new_rx_count;
2000 if (i40e_enabled_xdp_vsi(vsi))
2001 vsi->xdp_rings[i]->count = new_tx_count;
2002 }
2003 vsi->num_tx_desc = new_tx_count;
2004 vsi->num_rx_desc = new_rx_count;
2005 goto done;
2006 }
2007
2008
2009
2010
2011
2012
2013
2014 tx_alloc_queue_pairs = vsi->alloc_queue_pairs *
2015 (i40e_enabled_xdp_vsi(vsi) ? 2 : 1);
2016 if (new_tx_count != vsi->tx_rings[0]->count) {
2017 netdev_info(netdev,
2018 "Changing Tx descriptor count from %d to %d.\n",
2019 vsi->tx_rings[0]->count, new_tx_count);
2020 tx_rings = kcalloc(tx_alloc_queue_pairs,
2021 sizeof(struct i40e_ring), GFP_KERNEL);
2022 if (!tx_rings) {
2023 err = -ENOMEM;
2024 goto done;
2025 }
2026
2027 for (i = 0; i < tx_alloc_queue_pairs; i++) {
2028 if (!i40e_active_tx_ring_index(vsi, i))
2029 continue;
2030
2031 tx_rings[i] = *vsi->tx_rings[i];
2032 tx_rings[i].count = new_tx_count;
2033
2034
2035
2036 tx_rings[i].desc = NULL;
2037 tx_rings[i].rx_bi = NULL;
2038 err = i40e_setup_tx_descriptors(&tx_rings[i]);
2039 if (err) {
2040 while (i) {
2041 i--;
2042 if (!i40e_active_tx_ring_index(vsi, i))
2043 continue;
2044 i40e_free_tx_resources(&tx_rings[i]);
2045 }
2046 kfree(tx_rings);
2047 tx_rings = NULL;
2048
2049 goto done;
2050 }
2051 }
2052 }
2053
2054
2055 if (new_rx_count != vsi->rx_rings[0]->count) {
2056 netdev_info(netdev,
2057 "Changing Rx descriptor count from %d to %d\n",
2058 vsi->rx_rings[0]->count, new_rx_count);
2059 rx_rings = kcalloc(vsi->alloc_queue_pairs,
2060 sizeof(struct i40e_ring), GFP_KERNEL);
2061 if (!rx_rings) {
2062 err = -ENOMEM;
2063 goto free_tx;
2064 }
2065
2066 for (i = 0; i < vsi->num_queue_pairs; i++) {
2067 u16 unused;
2068
2069
2070 rx_rings[i] = *vsi->rx_rings[i];
2071 rx_rings[i].count = new_rx_count;
2072
2073
2074
2075 rx_rings[i].desc = NULL;
2076 rx_rings[i].rx_bi = NULL;
2077
2078 memset(&rx_rings[i].xdp_rxq, 0, sizeof(rx_rings[i].xdp_rxq));
2079
2080
2081
2082 rx_rings[i].tail = hw->hw_addr + I40E_PRTGEN_STATUS;
2083 err = i40e_setup_rx_descriptors(&rx_rings[i]);
2084 if (err)
2085 goto rx_unwind;
2086 err = i40e_alloc_rx_bi(&rx_rings[i]);
2087 if (err)
2088 goto rx_unwind;
2089
2090
2091
2092
2093 unused = I40E_DESC_UNUSED(&rx_rings[i]);
2094 err = i40e_alloc_rx_buffers(&rx_rings[i], unused);
2095rx_unwind:
2096 if (err) {
2097 do {
2098 i40e_free_rx_resources(&rx_rings[i]);
2099 } while (i--);
2100 kfree(rx_rings);
2101 rx_rings = NULL;
2102
2103 goto free_tx;
2104 }
2105 }
2106 }
2107
2108
2109
2110
2111 i40e_down(vsi);
2112
2113 if (tx_rings) {
2114 for (i = 0; i < tx_alloc_queue_pairs; i++) {
2115 if (i40e_active_tx_ring_index(vsi, i)) {
2116 i40e_free_tx_resources(vsi->tx_rings[i]);
2117 *vsi->tx_rings[i] = tx_rings[i];
2118 }
2119 }
2120 kfree(tx_rings);
2121 tx_rings = NULL;
2122 }
2123
2124 if (rx_rings) {
2125 for (i = 0; i < vsi->num_queue_pairs; i++) {
2126 i40e_free_rx_resources(vsi->rx_rings[i]);
2127
2128 rx_rings[i].tail = vsi->rx_rings[i]->tail;
2129
2130
2131
2132
2133
2134 rx_rings[i].next_to_use = 0;
2135 rx_rings[i].next_to_clean = 0;
2136 rx_rings[i].next_to_alloc = 0;
2137
2138 *vsi->rx_rings[i] = rx_rings[i];
2139 }
2140 kfree(rx_rings);
2141 rx_rings = NULL;
2142 }
2143
2144 vsi->num_tx_desc = new_tx_count;
2145 vsi->num_rx_desc = new_rx_count;
2146 i40e_up(vsi);
2147
2148free_tx:
2149
2150 if (tx_rings) {
2151 for (i = 0; i < tx_alloc_queue_pairs; i++) {
2152 if (i40e_active_tx_ring_index(vsi, i))
2153 i40e_free_tx_resources(vsi->tx_rings[i]);
2154 }
2155 kfree(tx_rings);
2156 tx_rings = NULL;
2157 }
2158
2159done:
2160 clear_bit(__I40E_CONFIG_BUSY, pf->state);
2161
2162 return err;
2163}
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179static int i40e_get_stats_count(struct net_device *netdev)
2180{
2181 struct i40e_netdev_priv *np = netdev_priv(netdev);
2182 struct i40e_vsi *vsi = np->vsi;
2183 struct i40e_pf *pf = vsi->back;
2184 int stats_len;
2185
2186 if (vsi == pf->vsi[pf->lan_vsi] && pf->hw.partition_id == 1)
2187 stats_len = I40E_PF_STATS_LEN;
2188 else
2189 stats_len = I40E_VSI_STATS_LEN;
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205 stats_len += I40E_QUEUE_STATS_LEN * 2 * netdev->num_tx_queues;
2206
2207 return stats_len;
2208}
2209
2210static int i40e_get_sset_count(struct net_device *netdev, int sset)
2211{
2212 struct i40e_netdev_priv *np = netdev_priv(netdev);
2213 struct i40e_vsi *vsi = np->vsi;
2214 struct i40e_pf *pf = vsi->back;
2215
2216 switch (sset) {
2217 case ETH_SS_TEST:
2218 return I40E_TEST_LEN;
2219 case ETH_SS_STATS:
2220 return i40e_get_stats_count(netdev);
2221 case ETH_SS_PRIV_FLAGS:
2222 return I40E_PRIV_FLAGS_STR_LEN +
2223 (pf->hw.pf_id == 0 ? I40E_GL_PRIV_FLAGS_STR_LEN : 0);
2224 default:
2225 return -EOPNOTSUPP;
2226 }
2227}
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239static struct i40e_cp_veb_tc_stats
2240i40e_get_veb_tc_stats(struct i40e_veb_tc_stats *tc, unsigned int i)
2241{
2242 struct i40e_cp_veb_tc_stats veb_tc = {
2243 .tc_rx_packets = tc->tc_rx_packets[i],
2244 .tc_rx_bytes = tc->tc_rx_bytes[i],
2245 .tc_tx_packets = tc->tc_tx_packets[i],
2246 .tc_tx_bytes = tc->tc_tx_bytes[i],
2247 };
2248
2249 return veb_tc;
2250}
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261static inline struct i40e_pfc_stats
2262i40e_get_pfc_stats(struct i40e_pf *pf, unsigned int i)
2263{
2264#define I40E_GET_PFC_STAT(stat, priority) \
2265 .stat = pf->stats.stat[priority]
2266
2267 struct i40e_pfc_stats pfc = {
2268 I40E_GET_PFC_STAT(priority_xon_rx, i),
2269 I40E_GET_PFC_STAT(priority_xoff_rx, i),
2270 I40E_GET_PFC_STAT(priority_xon_tx, i),
2271 I40E_GET_PFC_STAT(priority_xoff_tx, i),
2272 I40E_GET_PFC_STAT(priority_xon_2_xoff, i),
2273 };
2274 return pfc;
2275}
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291static void i40e_get_ethtool_stats(struct net_device *netdev,
2292 struct ethtool_stats *stats, u64 *data)
2293{
2294 struct i40e_netdev_priv *np = netdev_priv(netdev);
2295 struct i40e_vsi *vsi = np->vsi;
2296 struct i40e_pf *pf = vsi->back;
2297 struct i40e_veb *veb = NULL;
2298 unsigned int i;
2299 bool veb_stats;
2300 u64 *p = data;
2301
2302 i40e_update_stats(vsi);
2303
2304 i40e_add_ethtool_stats(&data, i40e_get_vsi_stats_struct(vsi),
2305 i40e_gstrings_net_stats);
2306
2307 i40e_add_ethtool_stats(&data, vsi, i40e_gstrings_misc_stats);
2308
2309 rcu_read_lock();
2310 for (i = 0; i < netdev->num_tx_queues; i++) {
2311 i40e_add_queue_stats(&data, READ_ONCE(vsi->tx_rings[i]));
2312 i40e_add_queue_stats(&data, READ_ONCE(vsi->rx_rings[i]));
2313 }
2314 rcu_read_unlock();
2315
2316 if (vsi != pf->vsi[pf->lan_vsi] || pf->hw.partition_id != 1)
2317 goto check_data_pointer;
2318
2319 veb_stats = ((pf->lan_veb != I40E_NO_VEB) &&
2320 (pf->lan_veb < I40E_MAX_VEB) &&
2321 (pf->flags & I40E_FLAG_VEB_STATS_ENABLED));
2322
2323 if (veb_stats) {
2324 veb = pf->veb[pf->lan_veb];
2325 i40e_update_veb_stats(veb);
2326 }
2327
2328
2329
2330
2331
2332 i40e_add_ethtool_stats(&data, veb_stats ? veb : NULL,
2333 i40e_gstrings_veb_stats);
2334
2335 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2336 if (veb_stats) {
2337 struct i40e_cp_veb_tc_stats veb_tc =
2338 i40e_get_veb_tc_stats(&veb->tc_stats, i);
2339
2340 i40e_add_ethtool_stats(&data, &veb_tc,
2341 i40e_gstrings_veb_tc_stats);
2342 } else {
2343 i40e_add_ethtool_stats(&data, NULL,
2344 i40e_gstrings_veb_tc_stats);
2345 }
2346
2347 i40e_add_ethtool_stats(&data, pf, i40e_gstrings_stats);
2348
2349 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
2350 struct i40e_pfc_stats pfc = i40e_get_pfc_stats(pf, i);
2351
2352 i40e_add_ethtool_stats(&data, &pfc, i40e_gstrings_pfc_stats);
2353 }
2354
2355check_data_pointer:
2356 WARN_ONCE(data - p != i40e_get_stats_count(netdev),
2357 "ethtool stats count mismatch!");
2358}
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370static void i40e_get_stat_strings(struct net_device *netdev, u8 *data)
2371{
2372 struct i40e_netdev_priv *np = netdev_priv(netdev);
2373 struct i40e_vsi *vsi = np->vsi;
2374 struct i40e_pf *pf = vsi->back;
2375 unsigned int i;
2376 u8 *p = data;
2377
2378 i40e_add_stat_strings(&data, i40e_gstrings_net_stats);
2379
2380 i40e_add_stat_strings(&data, i40e_gstrings_misc_stats);
2381
2382 for (i = 0; i < netdev->num_tx_queues; i++) {
2383 i40e_add_stat_strings(&data, i40e_gstrings_queue_stats,
2384 "tx", i);
2385 i40e_add_stat_strings(&data, i40e_gstrings_queue_stats,
2386 "rx", i);
2387 }
2388
2389 if (vsi != pf->vsi[pf->lan_vsi] || pf->hw.partition_id != 1)
2390 goto check_data_pointer;
2391
2392 i40e_add_stat_strings(&data, i40e_gstrings_veb_stats);
2393
2394 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2395 i40e_add_stat_strings(&data, i40e_gstrings_veb_tc_stats, i);
2396
2397 i40e_add_stat_strings(&data, i40e_gstrings_stats);
2398
2399 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
2400 i40e_add_stat_strings(&data, i40e_gstrings_pfc_stats, i);
2401
2402check_data_pointer:
2403 WARN_ONCE(data - p != i40e_get_stats_count(netdev) * ETH_GSTRING_LEN,
2404 "stat strings count mismatch!");
2405}
2406
2407static void i40e_get_priv_flag_strings(struct net_device *netdev, u8 *data)
2408{
2409 struct i40e_netdev_priv *np = netdev_priv(netdev);
2410 struct i40e_vsi *vsi = np->vsi;
2411 struct i40e_pf *pf = vsi->back;
2412 unsigned int i;
2413 u8 *p = data;
2414
2415 for (i = 0; i < I40E_PRIV_FLAGS_STR_LEN; i++)
2416 ethtool_sprintf(&p, i40e_gstrings_priv_flags[i].flag_string);
2417 if (pf->hw.pf_id != 0)
2418 return;
2419 for (i = 0; i < I40E_GL_PRIV_FLAGS_STR_LEN; i++)
2420 ethtool_sprintf(&p, i40e_gl_gstrings_priv_flags[i].flag_string);
2421}
2422
2423static void i40e_get_strings(struct net_device *netdev, u32 stringset,
2424 u8 *data)
2425{
2426 switch (stringset) {
2427 case ETH_SS_TEST:
2428 memcpy(data, i40e_gstrings_test,
2429 I40E_TEST_LEN * ETH_GSTRING_LEN);
2430 break;
2431 case ETH_SS_STATS:
2432 i40e_get_stat_strings(netdev, data);
2433 break;
2434 case ETH_SS_PRIV_FLAGS:
2435 i40e_get_priv_flag_strings(netdev, data);
2436 break;
2437 default:
2438 break;
2439 }
2440}
2441
2442static int i40e_get_ts_info(struct net_device *dev,
2443 struct ethtool_ts_info *info)
2444{
2445 struct i40e_pf *pf = i40e_netdev_to_pf(dev);
2446
2447
2448 if (!(pf->flags & I40E_FLAG_PTP))
2449 return ethtool_op_get_ts_info(dev, info);
2450
2451 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2452 SOF_TIMESTAMPING_RX_SOFTWARE |
2453 SOF_TIMESTAMPING_SOFTWARE |
2454 SOF_TIMESTAMPING_TX_HARDWARE |
2455 SOF_TIMESTAMPING_RX_HARDWARE |
2456 SOF_TIMESTAMPING_RAW_HARDWARE;
2457
2458 if (pf->ptp_clock)
2459 info->phc_index = ptp_clock_index(pf->ptp_clock);
2460 else
2461 info->phc_index = -1;
2462
2463 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
2464
2465 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
2466 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2467 BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2468 BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ);
2469
2470 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE)
2471 info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2472 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2473 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
2474 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2475 BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) |
2476 BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2477 BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2478 BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ);
2479
2480 return 0;
2481}
2482
2483static u64 i40e_link_test(struct net_device *netdev, u64 *data)
2484{
2485 struct i40e_netdev_priv *np = netdev_priv(netdev);
2486 struct i40e_pf *pf = np->vsi->back;
2487 i40e_status status;
2488 bool link_up = false;
2489
2490 netif_info(pf, hw, netdev, "link test\n");
2491 status = i40e_get_link_status(&pf->hw, &link_up);
2492 if (status) {
2493 netif_err(pf, drv, netdev, "link query timed out, please retry test\n");
2494 *data = 1;
2495 return *data;
2496 }
2497
2498 if (link_up)
2499 *data = 0;
2500 else
2501 *data = 1;
2502
2503 return *data;
2504}
2505
2506static u64 i40e_reg_test(struct net_device *netdev, u64 *data)
2507{
2508 struct i40e_netdev_priv *np = netdev_priv(netdev);
2509 struct i40e_pf *pf = np->vsi->back;
2510
2511 netif_info(pf, hw, netdev, "register test\n");
2512 *data = i40e_diag_reg_test(&pf->hw);
2513
2514 return *data;
2515}
2516
2517static u64 i40e_eeprom_test(struct net_device *netdev, u64 *data)
2518{
2519 struct i40e_netdev_priv *np = netdev_priv(netdev);
2520 struct i40e_pf *pf = np->vsi->back;
2521
2522 netif_info(pf, hw, netdev, "eeprom test\n");
2523 *data = i40e_diag_eeprom_test(&pf->hw);
2524
2525
2526 pf->hw.nvmupd_state = I40E_NVMUPD_STATE_INIT;
2527
2528 return *data;
2529}
2530
2531static u64 i40e_intr_test(struct net_device *netdev, u64 *data)
2532{
2533 struct i40e_netdev_priv *np = netdev_priv(netdev);
2534 struct i40e_pf *pf = np->vsi->back;
2535 u16 swc_old = pf->sw_int_count;
2536
2537 netif_info(pf, hw, netdev, "interrupt test\n");
2538 wr32(&pf->hw, I40E_PFINT_DYN_CTL0,
2539 (I40E_PFINT_DYN_CTL0_INTENA_MASK |
2540 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
2541 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK |
2542 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK |
2543 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK));
2544 usleep_range(1000, 2000);
2545 *data = (swc_old == pf->sw_int_count);
2546
2547 return *data;
2548}
2549
2550static inline bool i40e_active_vfs(struct i40e_pf *pf)
2551{
2552 struct i40e_vf *vfs = pf->vf;
2553 int i;
2554
2555 for (i = 0; i < pf->num_alloc_vfs; i++)
2556 if (test_bit(I40E_VF_STATE_ACTIVE, &vfs[i].vf_states))
2557 return true;
2558 return false;
2559}
2560
2561static inline bool i40e_active_vmdqs(struct i40e_pf *pf)
2562{
2563 return !!i40e_find_vsi_by_type(pf, I40E_VSI_VMDQ2);
2564}
2565
2566static void i40e_diag_test(struct net_device *netdev,
2567 struct ethtool_test *eth_test, u64 *data)
2568{
2569 struct i40e_netdev_priv *np = netdev_priv(netdev);
2570 bool if_running = netif_running(netdev);
2571 struct i40e_pf *pf = np->vsi->back;
2572
2573 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
2574
2575 netif_info(pf, drv, netdev, "offline testing starting\n");
2576
2577 set_bit(__I40E_TESTING, pf->state);
2578
2579 if (i40e_active_vfs(pf) || i40e_active_vmdqs(pf)) {
2580 dev_warn(&pf->pdev->dev,
2581 "Please take active VFs and Netqueues offline and restart the adapter before running NIC diagnostics\n");
2582 data[I40E_ETH_TEST_REG] = 1;
2583 data[I40E_ETH_TEST_EEPROM] = 1;
2584 data[I40E_ETH_TEST_INTR] = 1;
2585 data[I40E_ETH_TEST_LINK] = 1;
2586 eth_test->flags |= ETH_TEST_FL_FAILED;
2587 clear_bit(__I40E_TESTING, pf->state);
2588 goto skip_ol_tests;
2589 }
2590
2591
2592 if (if_running)
2593
2594 i40e_close(netdev);
2595 else
2596
2597
2598
2599
2600
2601 i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true);
2602
2603 if (i40e_link_test(netdev, &data[I40E_ETH_TEST_LINK]))
2604 eth_test->flags |= ETH_TEST_FL_FAILED;
2605
2606 if (i40e_eeprom_test(netdev, &data[I40E_ETH_TEST_EEPROM]))
2607 eth_test->flags |= ETH_TEST_FL_FAILED;
2608
2609 if (i40e_intr_test(netdev, &data[I40E_ETH_TEST_INTR]))
2610 eth_test->flags |= ETH_TEST_FL_FAILED;
2611
2612
2613 if (i40e_reg_test(netdev, &data[I40E_ETH_TEST_REG]))
2614 eth_test->flags |= ETH_TEST_FL_FAILED;
2615
2616 clear_bit(__I40E_TESTING, pf->state);
2617 i40e_do_reset(pf, BIT(__I40E_PF_RESET_REQUESTED), true);
2618
2619 if (if_running)
2620 i40e_open(netdev);
2621 } else {
2622
2623 netif_info(pf, drv, netdev, "online testing starting\n");
2624
2625 if (i40e_link_test(netdev, &data[I40E_ETH_TEST_LINK]))
2626 eth_test->flags |= ETH_TEST_FL_FAILED;
2627
2628
2629 data[I40E_ETH_TEST_REG] = 0;
2630 data[I40E_ETH_TEST_EEPROM] = 0;
2631 data[I40E_ETH_TEST_INTR] = 0;
2632 }
2633
2634skip_ol_tests:
2635
2636 netif_info(pf, drv, netdev, "testing finished\n");
2637}
2638
2639static void i40e_get_wol(struct net_device *netdev,
2640 struct ethtool_wolinfo *wol)
2641{
2642 struct i40e_netdev_priv *np = netdev_priv(netdev);
2643 struct i40e_pf *pf = np->vsi->back;
2644 struct i40e_hw *hw = &pf->hw;
2645 u16 wol_nvm_bits;
2646
2647
2648 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
2649 if ((BIT(hw->port) & wol_nvm_bits) || (hw->partition_id != 1)) {
2650 wol->supported = 0;
2651 wol->wolopts = 0;
2652 } else {
2653 wol->supported = WAKE_MAGIC;
2654 wol->wolopts = (pf->wol_en ? WAKE_MAGIC : 0);
2655 }
2656}
2657
2658
2659
2660
2661
2662
2663static int i40e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2664{
2665 struct i40e_netdev_priv *np = netdev_priv(netdev);
2666 struct i40e_pf *pf = np->vsi->back;
2667 struct i40e_vsi *vsi = np->vsi;
2668 struct i40e_hw *hw = &pf->hw;
2669 u16 wol_nvm_bits;
2670
2671
2672 if (hw->partition_id != 1) {
2673 i40e_partition_setting_complaint(pf);
2674 return -EOPNOTSUPP;
2675 }
2676
2677 if (vsi != pf->vsi[pf->lan_vsi])
2678 return -EOPNOTSUPP;
2679
2680
2681 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
2682 if (BIT(hw->port) & wol_nvm_bits)
2683 return -EOPNOTSUPP;
2684
2685
2686 if (wol->wolopts & ~WAKE_MAGIC)
2687 return -EOPNOTSUPP;
2688
2689
2690 if (pf->wol_en != !!wol->wolopts) {
2691 pf->wol_en = !!wol->wolopts;
2692 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
2693 }
2694
2695 return 0;
2696}
2697
2698static int i40e_set_phys_id(struct net_device *netdev,
2699 enum ethtool_phys_id_state state)
2700{
2701 struct i40e_netdev_priv *np = netdev_priv(netdev);
2702 i40e_status ret = 0;
2703 struct i40e_pf *pf = np->vsi->back;
2704 struct i40e_hw *hw = &pf->hw;
2705 int blink_freq = 2;
2706 u16 temp_status;
2707
2708 switch (state) {
2709 case ETHTOOL_ID_ACTIVE:
2710 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS)) {
2711 pf->led_status = i40e_led_get(hw);
2712 } else {
2713 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE))
2714 i40e_aq_set_phy_debug(hw, I40E_PHY_DEBUG_ALL,
2715 NULL);
2716 ret = i40e_led_get_phy(hw, &temp_status,
2717 &pf->phy_led_val);
2718 pf->led_status = temp_status;
2719 }
2720 return blink_freq;
2721 case ETHTOOL_ID_ON:
2722 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS))
2723 i40e_led_set(hw, 0xf, false);
2724 else
2725 ret = i40e_led_set_phy(hw, true, pf->led_status, 0);
2726 break;
2727 case ETHTOOL_ID_OFF:
2728 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS))
2729 i40e_led_set(hw, 0x0, false);
2730 else
2731 ret = i40e_led_set_phy(hw, false, pf->led_status, 0);
2732 break;
2733 case ETHTOOL_ID_INACTIVE:
2734 if (!(pf->hw_features & I40E_HW_PHY_CONTROLS_LEDS)) {
2735 i40e_led_set(hw, pf->led_status, false);
2736 } else {
2737 ret = i40e_led_set_phy(hw, false, pf->led_status,
2738 (pf->phy_led_val |
2739 I40E_PHY_LED_MODE_ORIG));
2740 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE))
2741 i40e_aq_set_phy_debug(hw, 0, NULL);
2742 }
2743 break;
2744 default:
2745 break;
2746 }
2747 if (ret)
2748 return -ENOENT;
2749 else
2750 return 0;
2751}
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768static int __i40e_get_coalesce(struct net_device *netdev,
2769 struct ethtool_coalesce *ec,
2770 int queue)
2771{
2772 struct i40e_netdev_priv *np = netdev_priv(netdev);
2773 struct i40e_ring *rx_ring, *tx_ring;
2774 struct i40e_vsi *vsi = np->vsi;
2775
2776 ec->tx_max_coalesced_frames_irq = vsi->work_limit;
2777 ec->rx_max_coalesced_frames_irq = vsi->work_limit;
2778
2779
2780
2781
2782 if (queue < 0)
2783 queue = 0;
2784 else if (queue >= vsi->num_queue_pairs)
2785 return -EINVAL;
2786
2787 rx_ring = vsi->rx_rings[queue];
2788 tx_ring = vsi->tx_rings[queue];
2789
2790 if (ITR_IS_DYNAMIC(rx_ring->itr_setting))
2791 ec->use_adaptive_rx_coalesce = 1;
2792
2793 if (ITR_IS_DYNAMIC(tx_ring->itr_setting))
2794 ec->use_adaptive_tx_coalesce = 1;
2795
2796 ec->rx_coalesce_usecs = rx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
2797 ec->tx_coalesce_usecs = tx_ring->itr_setting & ~I40E_ITR_DYNAMIC;
2798
2799
2800
2801
2802
2803
2804
2805 ec->rx_coalesce_usecs_high = vsi->int_rate_limit;
2806 ec->tx_coalesce_usecs_high = vsi->int_rate_limit;
2807
2808 return 0;
2809}
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822static int i40e_get_coalesce(struct net_device *netdev,
2823 struct ethtool_coalesce *ec,
2824 struct kernel_ethtool_coalesce *kernel_coal,
2825 struct netlink_ext_ack *extack)
2826{
2827 return __i40e_get_coalesce(netdev, ec, -1);
2828}
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838static int i40e_get_per_queue_coalesce(struct net_device *netdev, u32 queue,
2839 struct ethtool_coalesce *ec)
2840{
2841 return __i40e_get_coalesce(netdev, ec, queue);
2842}
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852static void i40e_set_itr_per_queue(struct i40e_vsi *vsi,
2853 struct ethtool_coalesce *ec,
2854 int queue)
2855{
2856 struct i40e_ring *rx_ring = vsi->rx_rings[queue];
2857 struct i40e_ring *tx_ring = vsi->tx_rings[queue];
2858 struct i40e_pf *pf = vsi->back;
2859 struct i40e_hw *hw = &pf->hw;
2860 struct i40e_q_vector *q_vector;
2861 u16 intrl;
2862
2863 intrl = i40e_intrl_usec_to_reg(vsi->int_rate_limit);
2864
2865 rx_ring->itr_setting = ITR_REG_ALIGN(ec->rx_coalesce_usecs);
2866 tx_ring->itr_setting = ITR_REG_ALIGN(ec->tx_coalesce_usecs);
2867
2868 if (ec->use_adaptive_rx_coalesce)
2869 rx_ring->itr_setting |= I40E_ITR_DYNAMIC;
2870 else
2871 rx_ring->itr_setting &= ~I40E_ITR_DYNAMIC;
2872
2873 if (ec->use_adaptive_tx_coalesce)
2874 tx_ring->itr_setting |= I40E_ITR_DYNAMIC;
2875 else
2876 tx_ring->itr_setting &= ~I40E_ITR_DYNAMIC;
2877
2878 q_vector = rx_ring->q_vector;
2879 q_vector->rx.target_itr = ITR_TO_REG(rx_ring->itr_setting);
2880
2881 q_vector = tx_ring->q_vector;
2882 q_vector->tx.target_itr = ITR_TO_REG(tx_ring->itr_setting);
2883
2884
2885
2886
2887
2888
2889 wr32(hw, I40E_PFINT_RATEN(q_vector->reg_idx), intrl);
2890 i40e_flush(hw);
2891}
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901static int __i40e_set_coalesce(struct net_device *netdev,
2902 struct ethtool_coalesce *ec,
2903 int queue)
2904{
2905 struct i40e_netdev_priv *np = netdev_priv(netdev);
2906 u16 intrl_reg, cur_rx_itr, cur_tx_itr;
2907 struct i40e_vsi *vsi = np->vsi;
2908 struct i40e_pf *pf = vsi->back;
2909 int i;
2910
2911 if (ec->tx_max_coalesced_frames_irq || ec->rx_max_coalesced_frames_irq)
2912 vsi->work_limit = ec->tx_max_coalesced_frames_irq;
2913
2914 if (queue < 0) {
2915 cur_rx_itr = vsi->rx_rings[0]->itr_setting;
2916 cur_tx_itr = vsi->tx_rings[0]->itr_setting;
2917 } else if (queue < vsi->num_queue_pairs) {
2918 cur_rx_itr = vsi->rx_rings[queue]->itr_setting;
2919 cur_tx_itr = vsi->tx_rings[queue]->itr_setting;
2920 } else {
2921 netif_info(pf, drv, netdev, "Invalid queue value, queue range is 0 - %d\n",
2922 vsi->num_queue_pairs - 1);
2923 return -EINVAL;
2924 }
2925
2926 cur_tx_itr &= ~I40E_ITR_DYNAMIC;
2927 cur_rx_itr &= ~I40E_ITR_DYNAMIC;
2928
2929
2930 if (ec->tx_coalesce_usecs_high != vsi->int_rate_limit) {
2931 netif_info(pf, drv, netdev, "tx-usecs-high is not used, please program rx-usecs-high\n");
2932 return -EINVAL;
2933 }
2934
2935 if (ec->rx_coalesce_usecs_high > INTRL_REG_TO_USEC(I40E_MAX_INTRL)) {
2936 netif_info(pf, drv, netdev, "Invalid value, rx-usecs-high range is 0-%lu\n",
2937 INTRL_REG_TO_USEC(I40E_MAX_INTRL));
2938 return -EINVAL;
2939 }
2940
2941 if (ec->rx_coalesce_usecs != cur_rx_itr &&
2942 ec->use_adaptive_rx_coalesce) {
2943 netif_info(pf, drv, netdev, "RX interrupt moderation cannot be changed if adaptive-rx is enabled.\n");
2944 return -EINVAL;
2945 }
2946
2947 if (ec->rx_coalesce_usecs > I40E_MAX_ITR) {
2948 netif_info(pf, drv, netdev, "Invalid value, rx-usecs range is 0-8160\n");
2949 return -EINVAL;
2950 }
2951
2952 if (ec->tx_coalesce_usecs != cur_tx_itr &&
2953 ec->use_adaptive_tx_coalesce) {
2954 netif_info(pf, drv, netdev, "TX interrupt moderation cannot be changed if adaptive-tx is enabled.\n");
2955 return -EINVAL;
2956 }
2957
2958 if (ec->tx_coalesce_usecs > I40E_MAX_ITR) {
2959 netif_info(pf, drv, netdev, "Invalid value, tx-usecs range is 0-8160\n");
2960 return -EINVAL;
2961 }
2962
2963 if (ec->use_adaptive_rx_coalesce && !cur_rx_itr)
2964 ec->rx_coalesce_usecs = I40E_MIN_ITR;
2965
2966 if (ec->use_adaptive_tx_coalesce && !cur_tx_itr)
2967 ec->tx_coalesce_usecs = I40E_MIN_ITR;
2968
2969 intrl_reg = i40e_intrl_usec_to_reg(ec->rx_coalesce_usecs_high);
2970 vsi->int_rate_limit = INTRL_REG_TO_USEC(intrl_reg);
2971 if (vsi->int_rate_limit != ec->rx_coalesce_usecs_high) {
2972 netif_info(pf, drv, netdev, "Interrupt rate limit rounded down to %d\n",
2973 vsi->int_rate_limit);
2974 }
2975
2976
2977
2978
2979 if (queue < 0) {
2980 for (i = 0; i < vsi->num_queue_pairs; i++)
2981 i40e_set_itr_per_queue(vsi, ec, i);
2982 } else {
2983 i40e_set_itr_per_queue(vsi, ec, queue);
2984 }
2985
2986 return 0;
2987}
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998static int i40e_set_coalesce(struct net_device *netdev,
2999 struct ethtool_coalesce *ec,
3000 struct kernel_ethtool_coalesce *kernel_coal,
3001 struct netlink_ext_ack *extack)
3002{
3003 return __i40e_set_coalesce(netdev, ec, -1);
3004}
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014static int i40e_set_per_queue_coalesce(struct net_device *netdev, u32 queue,
3015 struct ethtool_coalesce *ec)
3016{
3017 return __i40e_set_coalesce(netdev, ec, queue);
3018}
3019
3020
3021
3022
3023
3024
3025
3026
3027static int i40e_get_rss_hash_opts(struct i40e_pf *pf, struct ethtool_rxnfc *cmd)
3028{
3029 struct i40e_hw *hw = &pf->hw;
3030 u8 flow_pctype = 0;
3031 u64 i_set = 0;
3032
3033 cmd->data = 0;
3034
3035 switch (cmd->flow_type) {
3036 case TCP_V4_FLOW:
3037 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3038 break;
3039 case UDP_V4_FLOW:
3040 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3041 break;
3042 case TCP_V6_FLOW:
3043 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3044 break;
3045 case UDP_V6_FLOW:
3046 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3047 break;
3048 case SCTP_V4_FLOW:
3049 case AH_ESP_V4_FLOW:
3050 case AH_V4_FLOW:
3051 case ESP_V4_FLOW:
3052 case IPV4_FLOW:
3053 case SCTP_V6_FLOW:
3054 case AH_ESP_V6_FLOW:
3055 case AH_V6_FLOW:
3056 case ESP_V6_FLOW:
3057 case IPV6_FLOW:
3058
3059 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
3060 break;
3061 default:
3062 return -EINVAL;
3063 }
3064
3065
3066 if (flow_pctype) {
3067 i_set = (u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0,
3068 flow_pctype)) |
3069 ((u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1,
3070 flow_pctype)) << 32);
3071 }
3072
3073
3074 if (i_set) {
3075 if (i_set & I40E_L4_SRC_MASK)
3076 cmd->data |= RXH_L4_B_0_1;
3077 if (i_set & I40E_L4_DST_MASK)
3078 cmd->data |= RXH_L4_B_2_3;
3079
3080 if (cmd->flow_type == TCP_V4_FLOW ||
3081 cmd->flow_type == UDP_V4_FLOW) {
3082 if (i_set & I40E_L3_SRC_MASK)
3083 cmd->data |= RXH_IP_SRC;
3084 if (i_set & I40E_L3_DST_MASK)
3085 cmd->data |= RXH_IP_DST;
3086 } else if (cmd->flow_type == TCP_V6_FLOW ||
3087 cmd->flow_type == UDP_V6_FLOW) {
3088 if (i_set & I40E_L3_V6_SRC_MASK)
3089 cmd->data |= RXH_IP_SRC;
3090 if (i_set & I40E_L3_V6_DST_MASK)
3091 cmd->data |= RXH_IP_DST;
3092 }
3093 }
3094
3095 return 0;
3096}
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106static int i40e_check_mask(u64 mask, u64 field)
3107{
3108 u64 value = mask & field;
3109
3110 if (value == field)
3111 return 1;
3112 else if (!value)
3113 return 0;
3114 else
3115 return -1;
3116}
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137static int i40e_parse_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp,
3138 struct i40e_rx_flow_userdef *data)
3139{
3140 u64 value, mask;
3141 int valid;
3142
3143
3144 memset(data, 0, sizeof(*data));
3145
3146 if (!(fsp->flow_type & FLOW_EXT))
3147 return 0;
3148
3149 value = be64_to_cpu(*((__be64 *)fsp->h_ext.data));
3150 mask = be64_to_cpu(*((__be64 *)fsp->m_ext.data));
3151
3152#define I40E_USERDEF_FLEX_WORD GENMASK_ULL(15, 0)
3153#define I40E_USERDEF_FLEX_OFFSET GENMASK_ULL(31, 16)
3154#define I40E_USERDEF_FLEX_FILTER GENMASK_ULL(31, 0)
3155
3156 valid = i40e_check_mask(mask, I40E_USERDEF_FLEX_FILTER);
3157 if (valid < 0) {
3158 return -EINVAL;
3159 } else if (valid) {
3160 data->flex_word = value & I40E_USERDEF_FLEX_WORD;
3161 data->flex_offset =
3162 (value & I40E_USERDEF_FLEX_OFFSET) >> 16;
3163 data->flex_filter = true;
3164 }
3165
3166 return 0;
3167}
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177static void i40e_fill_rx_flow_user_data(struct ethtool_rx_flow_spec *fsp,
3178 struct i40e_rx_flow_userdef *data)
3179{
3180 u64 value = 0, mask = 0;
3181
3182 if (data->flex_filter) {
3183 value |= data->flex_word;
3184 value |= (u64)data->flex_offset << 16;
3185 mask |= I40E_USERDEF_FLEX_FILTER;
3186 }
3187
3188 if (value || mask)
3189 fsp->flow_type |= FLOW_EXT;
3190
3191 *((__be64 *)fsp->h_ext.data) = cpu_to_be64(value);
3192 *((__be64 *)fsp->m_ext.data) = cpu_to_be64(mask);
3193}
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206static int i40e_get_ethtool_fdir_all(struct i40e_pf *pf,
3207 struct ethtool_rxnfc *cmd,
3208 u32 *rule_locs)
3209{
3210 struct i40e_fdir_filter *rule;
3211 struct hlist_node *node2;
3212 int cnt = 0;
3213
3214
3215 cmd->data = i40e_get_fd_cnt_all(pf);
3216
3217 hlist_for_each_entry_safe(rule, node2,
3218 &pf->fdir_filter_list, fdir_node) {
3219 if (cnt == cmd->rule_cnt)
3220 return -EMSGSIZE;
3221
3222 rule_locs[cnt] = rule->fd_id;
3223 cnt++;
3224 }
3225
3226 cmd->rule_cnt = cnt;
3227
3228 return 0;
3229}
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241static int i40e_get_ethtool_fdir_entry(struct i40e_pf *pf,
3242 struct ethtool_rxnfc *cmd)
3243{
3244 struct ethtool_rx_flow_spec *fsp =
3245 (struct ethtool_rx_flow_spec *)&cmd->fs;
3246 struct i40e_rx_flow_userdef userdef = {0};
3247 struct i40e_fdir_filter *rule = NULL;
3248 struct hlist_node *node2;
3249 u64 input_set;
3250 u16 index;
3251
3252 hlist_for_each_entry_safe(rule, node2,
3253 &pf->fdir_filter_list, fdir_node) {
3254 if (fsp->location <= rule->fd_id)
3255 break;
3256 }
3257
3258 if (!rule || fsp->location != rule->fd_id)
3259 return -EINVAL;
3260
3261 fsp->flow_type = rule->flow_type;
3262 if (fsp->flow_type == IP_USER_FLOW) {
3263 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
3264 fsp->h_u.usr_ip4_spec.proto = 0;
3265 fsp->m_u.usr_ip4_spec.proto = 0;
3266 }
3267
3268 if (fsp->flow_type == IPV6_USER_FLOW ||
3269 fsp->flow_type == UDP_V6_FLOW ||
3270 fsp->flow_type == TCP_V6_FLOW ||
3271 fsp->flow_type == SCTP_V6_FLOW) {
3272
3273
3274
3275
3276 fsp->h_u.tcp_ip6_spec.psrc = rule->dst_port;
3277 fsp->h_u.tcp_ip6_spec.pdst = rule->src_port;
3278 memcpy(fsp->h_u.tcp_ip6_spec.ip6dst, rule->src_ip6,
3279 sizeof(__be32) * 4);
3280 memcpy(fsp->h_u.tcp_ip6_spec.ip6src, rule->dst_ip6,
3281 sizeof(__be32) * 4);
3282 } else {
3283
3284
3285
3286
3287 fsp->h_u.tcp_ip4_spec.psrc = rule->dst_port;
3288 fsp->h_u.tcp_ip4_spec.pdst = rule->src_port;
3289 fsp->h_u.tcp_ip4_spec.ip4src = rule->dst_ip;
3290 fsp->h_u.tcp_ip4_spec.ip4dst = rule->src_ip;
3291 }
3292
3293 switch (rule->flow_type) {
3294 case SCTP_V4_FLOW:
3295 index = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
3296 break;
3297 case TCP_V4_FLOW:
3298 index = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3299 break;
3300 case UDP_V4_FLOW:
3301 index = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3302 break;
3303 case SCTP_V6_FLOW:
3304 index = I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
3305 break;
3306 case TCP_V6_FLOW:
3307 index = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3308 break;
3309 case UDP_V6_FLOW:
3310 index = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3311 break;
3312 case IP_USER_FLOW:
3313 index = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
3314 break;
3315 case IPV6_USER_FLOW:
3316 index = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
3317 break;
3318 default:
3319
3320
3321
3322
3323
3324 WARN(1, "Missing input set index for flow_type %d\n",
3325 rule->flow_type);
3326 input_set = 0xFFFFFFFFFFFFFFFFULL;
3327 goto no_input_set;
3328 }
3329
3330 input_set = i40e_read_fd_input_set(pf, index);
3331
3332no_input_set:
3333 if (input_set & I40E_L3_V6_SRC_MASK) {
3334 fsp->m_u.tcp_ip6_spec.ip6src[0] = htonl(0xFFFFFFFF);
3335 fsp->m_u.tcp_ip6_spec.ip6src[1] = htonl(0xFFFFFFFF);
3336 fsp->m_u.tcp_ip6_spec.ip6src[2] = htonl(0xFFFFFFFF);
3337 fsp->m_u.tcp_ip6_spec.ip6src[3] = htonl(0xFFFFFFFF);
3338 }
3339
3340 if (input_set & I40E_L3_V6_DST_MASK) {
3341 fsp->m_u.tcp_ip6_spec.ip6dst[0] = htonl(0xFFFFFFFF);
3342 fsp->m_u.tcp_ip6_spec.ip6dst[1] = htonl(0xFFFFFFFF);
3343 fsp->m_u.tcp_ip6_spec.ip6dst[2] = htonl(0xFFFFFFFF);
3344 fsp->m_u.tcp_ip6_spec.ip6dst[3] = htonl(0xFFFFFFFF);
3345 }
3346
3347 if (input_set & I40E_L3_SRC_MASK)
3348 fsp->m_u.tcp_ip4_spec.ip4src = htonl(0xFFFFFFFF);
3349
3350 if (input_set & I40E_L3_DST_MASK)
3351 fsp->m_u.tcp_ip4_spec.ip4dst = htonl(0xFFFFFFFF);
3352
3353 if (input_set & I40E_L4_SRC_MASK)
3354 fsp->m_u.tcp_ip4_spec.psrc = htons(0xFFFF);
3355
3356 if (input_set & I40E_L4_DST_MASK)
3357 fsp->m_u.tcp_ip4_spec.pdst = htons(0xFFFF);
3358
3359 if (rule->dest_ctl == I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET)
3360 fsp->ring_cookie = RX_CLS_FLOW_DISC;
3361 else
3362 fsp->ring_cookie = rule->q_index;
3363
3364 if (rule->vlan_tag) {
3365 fsp->h_ext.vlan_etype = rule->vlan_etype;
3366 fsp->m_ext.vlan_etype = htons(0xFFFF);
3367 fsp->h_ext.vlan_tci = rule->vlan_tag;
3368 fsp->m_ext.vlan_tci = htons(0xFFFF);
3369 fsp->flow_type |= FLOW_EXT;
3370 }
3371
3372 if (rule->dest_vsi != pf->vsi[pf->lan_vsi]->id) {
3373 struct i40e_vsi *vsi;
3374
3375 vsi = i40e_find_vsi_from_id(pf, rule->dest_vsi);
3376 if (vsi && vsi->type == I40E_VSI_SRIOV) {
3377
3378
3379
3380 u64 ring_vf = vsi->vf_id + 1;
3381
3382 ring_vf <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
3383 fsp->ring_cookie |= ring_vf;
3384 }
3385 }
3386
3387 if (rule->flex_filter) {
3388 userdef.flex_filter = true;
3389 userdef.flex_word = be16_to_cpu(rule->flex_word);
3390 userdef.flex_offset = rule->flex_offset;
3391 }
3392
3393 i40e_fill_rx_flow_user_data(fsp, &userdef);
3394
3395 return 0;
3396}
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406static int i40e_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3407 u32 *rule_locs)
3408{
3409 struct i40e_netdev_priv *np = netdev_priv(netdev);
3410 struct i40e_vsi *vsi = np->vsi;
3411 struct i40e_pf *pf = vsi->back;
3412 int ret = -EOPNOTSUPP;
3413
3414 switch (cmd->cmd) {
3415 case ETHTOOL_GRXRINGS:
3416 cmd->data = vsi->rss_size;
3417 ret = 0;
3418 break;
3419 case ETHTOOL_GRXFH:
3420 ret = i40e_get_rss_hash_opts(pf, cmd);
3421 break;
3422 case ETHTOOL_GRXCLSRLCNT:
3423 cmd->rule_cnt = pf->fdir_pf_active_filters;
3424
3425 cmd->data = i40e_get_fd_cnt_all(pf);
3426 ret = 0;
3427 break;
3428 case ETHTOOL_GRXCLSRULE:
3429 ret = i40e_get_ethtool_fdir_entry(pf, cmd);
3430 break;
3431 case ETHTOOL_GRXCLSRLALL:
3432 ret = i40e_get_ethtool_fdir_all(pf, cmd, rule_locs);
3433 break;
3434 default:
3435 break;
3436 }
3437
3438 return ret;
3439}
3440
3441
3442
3443
3444
3445
3446
3447
3448static u64 i40e_get_rss_hash_bits(struct ethtool_rxnfc *nfc, u64 i_setc)
3449{
3450 u64 i_set = i_setc;
3451 u64 src_l3 = 0, dst_l3 = 0;
3452
3453 if (nfc->data & RXH_L4_B_0_1)
3454 i_set |= I40E_L4_SRC_MASK;
3455 else
3456 i_set &= ~I40E_L4_SRC_MASK;
3457 if (nfc->data & RXH_L4_B_2_3)
3458 i_set |= I40E_L4_DST_MASK;
3459 else
3460 i_set &= ~I40E_L4_DST_MASK;
3461
3462 if (nfc->flow_type == TCP_V6_FLOW || nfc->flow_type == UDP_V6_FLOW) {
3463 src_l3 = I40E_L3_V6_SRC_MASK;
3464 dst_l3 = I40E_L3_V6_DST_MASK;
3465 } else if (nfc->flow_type == TCP_V4_FLOW ||
3466 nfc->flow_type == UDP_V4_FLOW) {
3467 src_l3 = I40E_L3_SRC_MASK;
3468 dst_l3 = I40E_L3_DST_MASK;
3469 } else {
3470
3471 return i_set;
3472 }
3473
3474 if (nfc->data & RXH_IP_SRC)
3475 i_set |= src_l3;
3476 else
3477 i_set &= ~src_l3;
3478 if (nfc->data & RXH_IP_DST)
3479 i_set |= dst_l3;
3480 else
3481 i_set &= ~dst_l3;
3482
3483 return i_set;
3484}
3485
3486
3487
3488
3489
3490
3491
3492
3493static int i40e_set_rss_hash_opt(struct i40e_pf *pf, struct ethtool_rxnfc *nfc)
3494{
3495 struct i40e_hw *hw = &pf->hw;
3496 u64 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
3497 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
3498 u8 flow_pctype = 0;
3499 u64 i_set, i_setc;
3500
3501 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
3502 dev_err(&pf->pdev->dev,
3503 "Change of RSS hash input set is not supported when MFP mode is enabled\n");
3504 return -EOPNOTSUPP;
3505 }
3506
3507
3508
3509
3510 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3511 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3512 return -EINVAL;
3513
3514 switch (nfc->flow_type) {
3515 case TCP_V4_FLOW:
3516 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
3517 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3518 hena |=
3519 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3520 break;
3521 case TCP_V6_FLOW:
3522 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
3523 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3524 hena |=
3525 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3526 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3527 hena |=
3528 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3529 break;
3530 case UDP_V4_FLOW:
3531 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
3532 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3533 hena |=
3534 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
3535 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3536
3537 hena |= BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4);
3538 break;
3539 case UDP_V6_FLOW:
3540 flow_pctype = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
3541 if (pf->hw_features & I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE)
3542 hena |=
3543 BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
3544 BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3545
3546 hena |= BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6);
3547 break;
3548 case AH_ESP_V4_FLOW:
3549 case AH_V4_FLOW:
3550 case ESP_V4_FLOW:
3551 case SCTP_V4_FLOW:
3552 if ((nfc->data & RXH_L4_B_0_1) ||
3553 (nfc->data & RXH_L4_B_2_3))
3554 return -EINVAL;
3555 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3556 break;
3557 case AH_ESP_V6_FLOW:
3558 case AH_V6_FLOW:
3559 case ESP_V6_FLOW:
3560 case SCTP_V6_FLOW:
3561 if ((nfc->data & RXH_L4_B_0_1) ||
3562 (nfc->data & RXH_L4_B_2_3))
3563 return -EINVAL;
3564 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3565 break;
3566 case IPV4_FLOW:
3567 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |
3568 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4);
3569 break;
3570 case IPV6_FLOW:
3571 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |
3572 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6);
3573 break;
3574 default:
3575 return -EINVAL;
3576 }
3577
3578 if (flow_pctype) {
3579 i_setc = (u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0,
3580 flow_pctype)) |
3581 ((u64)i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1,
3582 flow_pctype)) << 32);
3583 i_set = i40e_get_rss_hash_bits(nfc, i_setc);
3584 i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, flow_pctype),
3585 (u32)i_set);
3586 i40e_write_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, flow_pctype),
3587 (u32)(i_set >> 32));
3588 hena |= BIT_ULL(flow_pctype);
3589 }
3590
3591 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
3592 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
3593 i40e_flush(hw);
3594
3595 return 0;
3596}
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610static int i40e_update_ethtool_fdir_entry(struct i40e_vsi *vsi,
3611 struct i40e_fdir_filter *input,
3612 u16 sw_idx,
3613 struct ethtool_rxnfc *cmd)
3614{
3615 struct i40e_fdir_filter *rule, *parent;
3616 struct i40e_pf *pf = vsi->back;
3617 struct hlist_node *node2;
3618 int err = -EINVAL;
3619
3620 parent = NULL;
3621 rule = NULL;
3622
3623 hlist_for_each_entry_safe(rule, node2,
3624 &pf->fdir_filter_list, fdir_node) {
3625
3626 if (rule->fd_id >= sw_idx)
3627 break;
3628 parent = rule;
3629 }
3630
3631
3632 if (rule && (rule->fd_id == sw_idx)) {
3633
3634
3635
3636 err = i40e_add_del_fdir(vsi, rule, false);
3637 hlist_del(&rule->fdir_node);
3638 kfree(rule);
3639 pf->fdir_pf_active_filters--;
3640 }
3641
3642
3643
3644
3645 if (!input)
3646 return err;
3647
3648
3649 INIT_HLIST_NODE(&input->fdir_node);
3650
3651
3652 if (parent)
3653 hlist_add_behind(&input->fdir_node, &parent->fdir_node);
3654 else
3655 hlist_add_head(&input->fdir_node,
3656 &pf->fdir_filter_list);
3657
3658
3659 pf->fdir_pf_active_filters++;
3660
3661 return 0;
3662}
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672static void i40e_prune_flex_pit_list(struct i40e_pf *pf)
3673{
3674 struct i40e_flex_pit *entry, *tmp;
3675 struct i40e_fdir_filter *rule;
3676
3677
3678 list_for_each_entry_safe(entry, tmp, &pf->l3_flex_pit_list, list) {
3679 bool found = false;
3680
3681 hlist_for_each_entry(rule, &pf->fdir_filter_list, fdir_node) {
3682 if (rule->flow_type != IP_USER_FLOW)
3683 continue;
3684 if (rule->flex_filter &&
3685 rule->flex_offset == entry->src_offset) {
3686 found = true;
3687 break;
3688 }
3689 }
3690
3691
3692
3693
3694 if (!found) {
3695 list_del(&entry->list);
3696 kfree(entry);
3697 }
3698 }
3699
3700
3701 list_for_each_entry_safe(entry, tmp, &pf->l4_flex_pit_list, list) {
3702 bool found = false;
3703
3704 hlist_for_each_entry(rule, &pf->fdir_filter_list, fdir_node) {
3705
3706
3707
3708 if (rule->flow_type == IP_USER_FLOW)
3709 continue;
3710 if (rule->flex_filter &&
3711 rule->flex_offset == entry->src_offset) {
3712 found = true;
3713 break;
3714 }
3715 }
3716
3717
3718
3719
3720 if (!found) {
3721 list_del(&entry->list);
3722 kfree(entry);
3723 }
3724 }
3725}
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737static int i40e_del_fdir_entry(struct i40e_vsi *vsi,
3738 struct ethtool_rxnfc *cmd)
3739{
3740 struct ethtool_rx_flow_spec *fsp =
3741 (struct ethtool_rx_flow_spec *)&cmd->fs;
3742 struct i40e_pf *pf = vsi->back;
3743 int ret = 0;
3744
3745 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
3746 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
3747 return -EBUSY;
3748
3749 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
3750 return -EBUSY;
3751
3752 ret = i40e_update_ethtool_fdir_entry(vsi, NULL, fsp->location, cmd);
3753
3754 i40e_prune_flex_pit_list(pf);
3755
3756 i40e_fdir_check_and_reenable(pf);
3757 return ret;
3758}
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769static u8 i40e_unused_pit_index(struct i40e_pf *pf)
3770{
3771 unsigned long available_index = 0xFF;
3772 struct i40e_flex_pit *entry;
3773
3774
3775
3776
3777
3778
3779 list_for_each_entry(entry, &pf->l4_flex_pit_list, list)
3780 clear_bit(entry->pit_index, &available_index);
3781
3782 list_for_each_entry(entry, &pf->l3_flex_pit_list, list)
3783 clear_bit(entry->pit_index, &available_index);
3784
3785 return find_first_bit(&available_index, 8);
3786}
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797static
3798struct i40e_flex_pit *i40e_find_flex_offset(struct list_head *flex_pit_list,
3799 u16 src_offset)
3800{
3801 struct i40e_flex_pit *entry;
3802 int size = 0;
3803
3804
3805
3806
3807 list_for_each_entry(entry, flex_pit_list, list) {
3808 size++;
3809 if (entry->src_offset == src_offset)
3810 return entry;
3811 }
3812
3813
3814
3815
3816
3817
3818 if (size >= I40E_FLEX_PIT_TABLE_SIZE)
3819 return ERR_PTR(-ENOSPC);
3820
3821 return NULL;
3822}
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837static int i40e_add_flex_offset(struct list_head *flex_pit_list,
3838 u16 src_offset,
3839 u8 pit_index)
3840{
3841 struct i40e_flex_pit *new_pit, *entry;
3842
3843 new_pit = kzalloc(sizeof(*entry), GFP_KERNEL);
3844 if (!new_pit)
3845 return -ENOMEM;
3846
3847 new_pit->src_offset = src_offset;
3848 new_pit->pit_index = pit_index;
3849
3850
3851
3852
3853 list_for_each_entry(entry, flex_pit_list, list) {
3854 if (new_pit->src_offset < entry->src_offset) {
3855 list_add_tail(&new_pit->list, &entry->list);
3856 return 0;
3857 }
3858
3859
3860
3861
3862
3863 if (new_pit->src_offset == entry->src_offset) {
3864 int err = 0;
3865
3866
3867
3868
3869 if (new_pit->pit_index != entry->pit_index)
3870 err = -EINVAL;
3871
3872 kfree(new_pit);
3873 return err;
3874 }
3875 }
3876
3877
3878
3879
3880 list_add_tail(&new_pit->list, flex_pit_list);
3881 return 0;
3882}
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905static void __i40e_reprogram_flex_pit(struct i40e_pf *pf,
3906 struct list_head *flex_pit_list,
3907 int flex_pit_start)
3908{
3909 struct i40e_flex_pit *entry = NULL;
3910 u16 last_offset = 0;
3911 int i = 0, j = 0;
3912
3913
3914
3915
3916 list_for_each_entry(entry, flex_pit_list, list) {
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931 for (j = i + 1; j < 3; j++) {
3932 u16 offset = entry->src_offset + j;
3933 int index = flex_pit_start + i;
3934 u32 value = I40E_FLEX_PREP_VAL(I40E_FLEX_DEST_UNUSED,
3935 1,
3936 offset - 3);
3937
3938 if (offset > I40E_MAX_FLEX_SRC_OFFSET) {
3939 i40e_write_rx_ctl(&pf->hw,
3940 I40E_PRTQF_FLX_PIT(index),
3941 value);
3942 i++;
3943 }
3944 }
3945
3946
3947 i40e_write_rx_ctl(&pf->hw,
3948 I40E_PRTQF_FLX_PIT(flex_pit_start + i),
3949 I40E_FLEX_PREP_VAL(entry->pit_index + 50,
3950 1,
3951 entry->src_offset));
3952 i++;
3953 }
3954
3955
3956
3957
3958
3959
3960
3961 if (!list_empty(flex_pit_list))
3962 last_offset = list_prev_entry(entry, list)->src_offset + 1;
3963
3964 for (; i < 3; i++, last_offset++) {
3965 i40e_write_rx_ctl(&pf->hw,
3966 I40E_PRTQF_FLX_PIT(flex_pit_start + i),
3967 I40E_FLEX_PREP_VAL(I40E_FLEX_DEST_UNUSED,
3968 1,
3969 last_offset));
3970 }
3971}
3972
3973
3974
3975
3976
3977
3978
3979
3980static void i40e_reprogram_flex_pit(struct i40e_pf *pf)
3981{
3982 __i40e_reprogram_flex_pit(pf, &pf->l3_flex_pit_list,
3983 I40E_FLEX_PIT_IDX_START_L3);
3984
3985 __i40e_reprogram_flex_pit(pf, &pf->l4_flex_pit_list,
3986 I40E_FLEX_PIT_IDX_START_L4);
3987
3988
3989 i40e_write_rx_ctl(&pf->hw,
3990 I40E_GLQF_ORT(I40E_L3_GLQF_ORT_IDX),
3991 I40E_ORT_PREP_VAL(I40E_FLEX_PIT_IDX_START_L3,
3992 3, 1));
3993
3994 i40e_write_rx_ctl(&pf->hw,
3995 I40E_GLQF_ORT(I40E_L4_GLQF_ORT_IDX),
3996 I40E_ORT_PREP_VAL(I40E_FLEX_PIT_IDX_START_L4,
3997 3, 1));
3998}
3999
4000
4001
4002
4003
4004
4005
4006
4007static const char *i40e_flow_str(struct ethtool_rx_flow_spec *fsp)
4008{
4009 switch (fsp->flow_type & ~FLOW_EXT) {
4010 case TCP_V4_FLOW:
4011 return "tcp4";
4012 case UDP_V4_FLOW:
4013 return "udp4";
4014 case SCTP_V4_FLOW:
4015 return "sctp4";
4016 case IP_USER_FLOW:
4017 return "ip4";
4018 case TCP_V6_FLOW:
4019 return "tcp6";
4020 case UDP_V6_FLOW:
4021 return "udp6";
4022 case SCTP_V6_FLOW:
4023 return "sctp6";
4024 case IPV6_USER_FLOW:
4025 return "ip6";
4026 default:
4027 return "unknown";
4028 }
4029}
4030
4031
4032
4033
4034
4035
4036
4037
4038static u64 i40e_pit_index_to_mask(int pit_index)
4039{
4040 switch (pit_index) {
4041 case 0:
4042 return I40E_FLEX_50_MASK;
4043 case 1:
4044 return I40E_FLEX_51_MASK;
4045 case 2:
4046 return I40E_FLEX_52_MASK;
4047 case 3:
4048 return I40E_FLEX_53_MASK;
4049 case 4:
4050 return I40E_FLEX_54_MASK;
4051 case 5:
4052 return I40E_FLEX_55_MASK;
4053 case 6:
4054 return I40E_FLEX_56_MASK;
4055 case 7:
4056 return I40E_FLEX_57_MASK;
4057 default:
4058 return 0;
4059 }
4060}
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072static void i40e_print_input_set(struct i40e_vsi *vsi, u64 old, u64 new)
4073{
4074 struct i40e_pf *pf = vsi->back;
4075 bool old_value, new_value;
4076 int i;
4077
4078 old_value = !!(old & I40E_L3_SRC_MASK);
4079 new_value = !!(new & I40E_L3_SRC_MASK);
4080 if (old_value != new_value)
4081 netif_info(pf, drv, vsi->netdev, "L3 source address: %s -> %s\n",
4082 old_value ? "ON" : "OFF",
4083 new_value ? "ON" : "OFF");
4084
4085 old_value = !!(old & I40E_L3_DST_MASK);
4086 new_value = !!(new & I40E_L3_DST_MASK);
4087 if (old_value != new_value)
4088 netif_info(pf, drv, vsi->netdev, "L3 destination address: %s -> %s\n",
4089 old_value ? "ON" : "OFF",
4090 new_value ? "ON" : "OFF");
4091
4092 old_value = !!(old & I40E_L4_SRC_MASK);
4093 new_value = !!(new & I40E_L4_SRC_MASK);
4094 if (old_value != new_value)
4095 netif_info(pf, drv, vsi->netdev, "L4 source port: %s -> %s\n",
4096 old_value ? "ON" : "OFF",
4097 new_value ? "ON" : "OFF");
4098
4099 old_value = !!(old & I40E_L4_DST_MASK);
4100 new_value = !!(new & I40E_L4_DST_MASK);
4101 if (old_value != new_value)
4102 netif_info(pf, drv, vsi->netdev, "L4 destination port: %s -> %s\n",
4103 old_value ? "ON" : "OFF",
4104 new_value ? "ON" : "OFF");
4105
4106 old_value = !!(old & I40E_VERIFY_TAG_MASK);
4107 new_value = !!(new & I40E_VERIFY_TAG_MASK);
4108 if (old_value != new_value)
4109 netif_info(pf, drv, vsi->netdev, "SCTP verification tag: %s -> %s\n",
4110 old_value ? "ON" : "OFF",
4111 new_value ? "ON" : "OFF");
4112
4113
4114 for (i = 0; i < I40E_FLEX_INDEX_ENTRIES; i++) {
4115 u64 flex_mask = i40e_pit_index_to_mask(i);
4116
4117 old_value = !!(old & flex_mask);
4118 new_value = !!(new & flex_mask);
4119 if (old_value != new_value)
4120 netif_info(pf, drv, vsi->netdev, "FLEX index %d: %s -> %s\n",
4121 i,
4122 old_value ? "ON" : "OFF",
4123 new_value ? "ON" : "OFF");
4124 }
4125
4126 netif_info(pf, drv, vsi->netdev, " Current input set: %0llx\n",
4127 old);
4128 netif_info(pf, drv, vsi->netdev, "Requested input set: %0llx\n",
4129 new);
4130}
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157static int i40e_check_fdir_input_set(struct i40e_vsi *vsi,
4158 struct ethtool_rx_flow_spec *fsp,
4159 struct i40e_rx_flow_userdef *userdef)
4160{
4161 static const __be32 ipv6_full_mask[4] = {cpu_to_be32(0xffffffff),
4162 cpu_to_be32(0xffffffff), cpu_to_be32(0xffffffff),
4163 cpu_to_be32(0xffffffff)};
4164 struct ethtool_tcpip6_spec *tcp_ip6_spec;
4165 struct ethtool_usrip6_spec *usr_ip6_spec;
4166 struct ethtool_tcpip4_spec *tcp_ip4_spec;
4167 struct ethtool_usrip4_spec *usr_ip4_spec;
4168 struct i40e_pf *pf = vsi->back;
4169 u64 current_mask, new_mask;
4170 bool new_flex_offset = false;
4171 bool flex_l3 = false;
4172 u16 *fdir_filter_count;
4173 u16 index, src_offset = 0;
4174 u8 pit_index = 0;
4175 int err;
4176
4177 switch (fsp->flow_type & ~FLOW_EXT) {
4178 case SCTP_V4_FLOW:
4179 index = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4180 fdir_filter_count = &pf->fd_sctp4_filter_cnt;
4181 break;
4182 case TCP_V4_FLOW:
4183 index = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4184 fdir_filter_count = &pf->fd_tcp4_filter_cnt;
4185 break;
4186 case UDP_V4_FLOW:
4187 index = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4188 fdir_filter_count = &pf->fd_udp4_filter_cnt;
4189 break;
4190 case SCTP_V6_FLOW:
4191 index = I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4192 fdir_filter_count = &pf->fd_sctp6_filter_cnt;
4193 break;
4194 case TCP_V6_FLOW:
4195 index = I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4196 fdir_filter_count = &pf->fd_tcp6_filter_cnt;
4197 break;
4198 case UDP_V6_FLOW:
4199 index = I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4200 fdir_filter_count = &pf->fd_udp6_filter_cnt;
4201 break;
4202 case IP_USER_FLOW:
4203 index = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4204 fdir_filter_count = &pf->fd_ip4_filter_cnt;
4205 flex_l3 = true;
4206 break;
4207 case IPV6_USER_FLOW:
4208 index = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4209 fdir_filter_count = &pf->fd_ip6_filter_cnt;
4210 flex_l3 = true;
4211 break;
4212 default:
4213 return -EOPNOTSUPP;
4214 }
4215
4216
4217 current_mask = i40e_read_fd_input_set(pf, index);
4218 new_mask = current_mask;
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229 switch (fsp->flow_type & ~FLOW_EXT) {
4230 case SCTP_V4_FLOW:
4231 new_mask &= ~I40E_VERIFY_TAG_MASK;
4232 fallthrough;
4233 case TCP_V4_FLOW:
4234 case UDP_V4_FLOW:
4235 tcp_ip4_spec = &fsp->m_u.tcp_ip4_spec;
4236
4237
4238 if (tcp_ip4_spec->ip4src == htonl(0xFFFFFFFF))
4239 new_mask |= I40E_L3_SRC_MASK;
4240 else if (!tcp_ip4_spec->ip4src)
4241 new_mask &= ~I40E_L3_SRC_MASK;
4242 else
4243 return -EOPNOTSUPP;
4244
4245
4246 if (tcp_ip4_spec->ip4dst == htonl(0xFFFFFFFF))
4247 new_mask |= I40E_L3_DST_MASK;
4248 else if (!tcp_ip4_spec->ip4dst)
4249 new_mask &= ~I40E_L3_DST_MASK;
4250 else
4251 return -EOPNOTSUPP;
4252
4253
4254 if (tcp_ip4_spec->psrc == htons(0xFFFF))
4255 new_mask |= I40E_L4_SRC_MASK;
4256 else if (!tcp_ip4_spec->psrc)
4257 new_mask &= ~I40E_L4_SRC_MASK;
4258 else
4259 return -EOPNOTSUPP;
4260
4261
4262 if (tcp_ip4_spec->pdst == htons(0xFFFF))
4263 new_mask |= I40E_L4_DST_MASK;
4264 else if (!tcp_ip4_spec->pdst)
4265 new_mask &= ~I40E_L4_DST_MASK;
4266 else
4267 return -EOPNOTSUPP;
4268
4269
4270 if (tcp_ip4_spec->tos)
4271 return -EOPNOTSUPP;
4272
4273 break;
4274 case SCTP_V6_FLOW:
4275 new_mask &= ~I40E_VERIFY_TAG_MASK;
4276 fallthrough;
4277 case TCP_V6_FLOW:
4278 case UDP_V6_FLOW:
4279 tcp_ip6_spec = &fsp->m_u.tcp_ip6_spec;
4280
4281
4282 if (ipv6_addr_equal((struct in6_addr *)&tcp_ip6_spec->ip6src,
4283 (struct in6_addr *)&ipv6_full_mask))
4284 new_mask |= I40E_L3_V6_SRC_MASK;
4285 else if (ipv6_addr_any((struct in6_addr *)
4286 &tcp_ip6_spec->ip6src))
4287 new_mask &= ~I40E_L3_V6_SRC_MASK;
4288 else
4289 return -EOPNOTSUPP;
4290
4291
4292 if (ipv6_addr_equal((struct in6_addr *)&tcp_ip6_spec->ip6dst,
4293 (struct in6_addr *)&ipv6_full_mask))
4294 new_mask |= I40E_L3_V6_DST_MASK;
4295 else if (ipv6_addr_any((struct in6_addr *)
4296 &tcp_ip6_spec->ip6dst))
4297 new_mask &= ~I40E_L3_V6_DST_MASK;
4298 else
4299 return -EOPNOTSUPP;
4300
4301
4302 if (tcp_ip6_spec->psrc == htons(0xFFFF))
4303 new_mask |= I40E_L4_SRC_MASK;
4304 else if (!tcp_ip6_spec->psrc)
4305 new_mask &= ~I40E_L4_SRC_MASK;
4306 else
4307 return -EOPNOTSUPP;
4308
4309
4310 if (tcp_ip6_spec->pdst == htons(0xFFFF))
4311 new_mask |= I40E_L4_DST_MASK;
4312 else if (!tcp_ip6_spec->pdst)
4313 new_mask &= ~I40E_L4_DST_MASK;
4314 else
4315 return -EOPNOTSUPP;
4316
4317
4318 if (tcp_ip6_spec->tclass)
4319 return -EOPNOTSUPP;
4320 break;
4321 case IP_USER_FLOW:
4322 usr_ip4_spec = &fsp->m_u.usr_ip4_spec;
4323
4324
4325 if (usr_ip4_spec->ip4src == htonl(0xFFFFFFFF))
4326 new_mask |= I40E_L3_SRC_MASK;
4327 else if (!usr_ip4_spec->ip4src)
4328 new_mask &= ~I40E_L3_SRC_MASK;
4329 else
4330 return -EOPNOTSUPP;
4331
4332
4333 if (usr_ip4_spec->ip4dst == htonl(0xFFFFFFFF))
4334 new_mask |= I40E_L3_DST_MASK;
4335 else if (!usr_ip4_spec->ip4dst)
4336 new_mask &= ~I40E_L3_DST_MASK;
4337 else
4338 return -EOPNOTSUPP;
4339
4340
4341 if (usr_ip4_spec->l4_4_bytes == htonl(0xFFFFFFFF))
4342 new_mask |= I40E_L4_SRC_MASK | I40E_L4_DST_MASK;
4343 else if (!usr_ip4_spec->l4_4_bytes)
4344 new_mask &= ~(I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
4345 else
4346 return -EOPNOTSUPP;
4347
4348
4349 if (usr_ip4_spec->tos)
4350 return -EOPNOTSUPP;
4351
4352
4353 if (usr_ip4_spec->ip_ver)
4354 return -EINVAL;
4355
4356
4357 if (usr_ip4_spec->proto)
4358 return -EINVAL;
4359
4360 break;
4361 case IPV6_USER_FLOW:
4362 usr_ip6_spec = &fsp->m_u.usr_ip6_spec;
4363
4364
4365 if (ipv6_addr_equal((struct in6_addr *)&usr_ip6_spec->ip6src,
4366 (struct in6_addr *)&ipv6_full_mask))
4367 new_mask |= I40E_L3_V6_SRC_MASK;
4368 else if (ipv6_addr_any((struct in6_addr *)
4369 &usr_ip6_spec->ip6src))
4370 new_mask &= ~I40E_L3_V6_SRC_MASK;
4371 else
4372 return -EOPNOTSUPP;
4373
4374
4375 if (ipv6_addr_equal((struct in6_addr *)&usr_ip6_spec->ip6dst,
4376 (struct in6_addr *)&ipv6_full_mask))
4377 new_mask |= I40E_L3_V6_DST_MASK;
4378 else if (ipv6_addr_any((struct in6_addr *)
4379 &usr_ip6_spec->ip6src))
4380 new_mask &= ~I40E_L3_V6_DST_MASK;
4381 else
4382 return -EOPNOTSUPP;
4383
4384 if (usr_ip6_spec->l4_4_bytes == htonl(0xFFFFFFFF))
4385 new_mask |= I40E_L4_SRC_MASK | I40E_L4_DST_MASK;
4386 else if (!usr_ip6_spec->l4_4_bytes)
4387 new_mask &= ~(I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
4388 else
4389 return -EOPNOTSUPP;
4390
4391
4392 if (usr_ip6_spec->tclass)
4393 return -EOPNOTSUPP;
4394
4395
4396 if (usr_ip6_spec->l4_proto)
4397 return -EINVAL;
4398
4399 break;
4400 default:
4401 return -EOPNOTSUPP;
4402 }
4403
4404 if (fsp->flow_type & FLOW_EXT) {
4405
4406
4407
4408 if (fsp->h_ext.vlan_etype != htons(ETH_P_8021Q) &&
4409 fsp->h_ext.vlan_etype != 0)
4410 return -EOPNOTSUPP;
4411 if (fsp->m_ext.vlan_tci == htons(0xFFFF))
4412 new_mask |= I40E_VLAN_SRC_MASK;
4413 else
4414 new_mask &= ~I40E_VLAN_SRC_MASK;
4415 }
4416
4417
4418 new_mask &= ~I40E_FLEX_INPUT_MASK;
4419
4420
4421
4422
4423
4424
4425 if (userdef->flex_filter) {
4426 struct i40e_flex_pit *l3_flex_pit = NULL, *flex_pit = NULL;
4427
4428
4429
4430
4431 if (userdef->flex_offset & 0x1) {
4432 dev_warn(&pf->pdev->dev,
4433 "Flexible data offset must be 2-byte aligned\n");
4434 return -EINVAL;
4435 }
4436
4437 src_offset = userdef->flex_offset >> 1;
4438
4439
4440 if (src_offset > I40E_MAX_FLEX_SRC_OFFSET) {
4441 dev_warn(&pf->pdev->dev,
4442 "Flexible data must reside within first 64 bytes of the packet payload\n");
4443 return -EINVAL;
4444 }
4445
4446
4447
4448
4449
4450
4451 flex_pit = i40e_find_flex_offset(&pf->l4_flex_pit_list,
4452 src_offset);
4453 if (IS_ERR(flex_pit))
4454 return PTR_ERR(flex_pit);
4455
4456
4457
4458
4459
4460
4461
4462
4463 if (flex_l3) {
4464 l3_flex_pit =
4465 i40e_find_flex_offset(&pf->l3_flex_pit_list,
4466 src_offset);
4467 if (IS_ERR(l3_flex_pit))
4468 return PTR_ERR(l3_flex_pit);
4469
4470 if (flex_pit) {
4471
4472
4473
4474
4475 if (l3_flex_pit) {
4476 if (l3_flex_pit->pit_index !=
4477 flex_pit->pit_index) {
4478 return -EINVAL;
4479 }
4480 } else {
4481 new_flex_offset = true;
4482 }
4483 } else {
4484 flex_pit = l3_flex_pit;
4485 }
4486 }
4487
4488
4489
4490
4491
4492
4493 if (!flex_pit) {
4494 new_flex_offset = true;
4495 pit_index = i40e_unused_pit_index(pf);
4496 } else {
4497 pit_index = flex_pit->pit_index;
4498 }
4499
4500
4501 new_mask |= i40e_pit_index_to_mask(pit_index);
4502 }
4503
4504
4505
4506
4507
4508 if (new_mask == current_mask && !new_flex_offset)
4509 return 0;
4510
4511 netif_info(pf, drv, vsi->netdev, "Input set change requested for %s flows:\n",
4512 i40e_flow_str(fsp));
4513 i40e_print_input_set(vsi, current_mask, new_mask);
4514 if (new_flex_offset) {
4515 netif_info(pf, drv, vsi->netdev, "FLEX index %d: Offset -> %d",
4516 pit_index, src_offset);
4517 }
4518
4519
4520
4521
4522
4523 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
4524 netif_err(pf, drv, vsi->netdev, "Cannot change Flow Director input sets while MFP is enabled\n");
4525 return -EOPNOTSUPP;
4526 }
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537 if (*fdir_filter_count) {
4538 netif_err(pf, drv, vsi->netdev, "Cannot change input set for %s flows until %d preexisting filters are removed\n",
4539 i40e_flow_str(fsp),
4540 *fdir_filter_count);
4541 return -EOPNOTSUPP;
4542 }
4543
4544 i40e_write_fd_input_set(pf, index, new_mask);
4545
4546
4547
4548
4549
4550
4551
4552 if (index == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER)
4553 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_FRAG_IPV4,
4554 new_mask);
4555
4556
4557 if (new_flex_offset) {
4558 err = i40e_add_flex_offset(&pf->l4_flex_pit_list, src_offset,
4559 pit_index);
4560 if (err)
4561 return err;
4562
4563 if (flex_l3) {
4564 err = i40e_add_flex_offset(&pf->l3_flex_pit_list,
4565 src_offset,
4566 pit_index);
4567 if (err)
4568 return err;
4569 }
4570
4571 i40e_reprogram_flex_pit(pf);
4572 }
4573
4574 return 0;
4575}
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587static bool i40e_match_fdir_filter(struct i40e_fdir_filter *a,
4588 struct i40e_fdir_filter *b)
4589{
4590
4591 if (a->dst_ip != b->dst_ip ||
4592 a->src_ip != b->src_ip ||
4593 a->dst_port != b->dst_port ||
4594 a->src_port != b->src_port ||
4595 a->flow_type != b->flow_type ||
4596 a->ipl4_proto != b->ipl4_proto ||
4597 a->vlan_tag != b->vlan_tag ||
4598 a->vlan_etype != b->vlan_etype)
4599 return false;
4600
4601 return true;
4602}
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629static int i40e_disallow_matching_filters(struct i40e_vsi *vsi,
4630 struct i40e_fdir_filter *input)
4631{
4632 struct i40e_pf *pf = vsi->back;
4633 struct i40e_fdir_filter *rule;
4634 struct hlist_node *node2;
4635
4636
4637 hlist_for_each_entry_safe(rule, node2,
4638 &pf->fdir_filter_list, fdir_node) {
4639
4640
4641
4642
4643 if (rule->fd_id == input->fd_id)
4644 continue;
4645
4646
4647
4648
4649 if (i40e_match_fdir_filter(rule, input)) {
4650 dev_warn(&pf->pdev->dev,
4651 "Existing user defined filter %d already matches this flow.\n",
4652 rule->fd_id);
4653 return -EINVAL;
4654 }
4655 }
4656
4657 return 0;
4658}
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668static int i40e_add_fdir_ethtool(struct i40e_vsi *vsi,
4669 struct ethtool_rxnfc *cmd)
4670{
4671 struct i40e_rx_flow_userdef userdef;
4672 struct ethtool_rx_flow_spec *fsp;
4673 struct i40e_fdir_filter *input;
4674 u16 dest_vsi = 0, q_index = 0;
4675 struct i40e_pf *pf;
4676 int ret = -EINVAL;
4677 u8 dest_ctl;
4678
4679 if (!vsi)
4680 return -EINVAL;
4681 pf = vsi->back;
4682
4683 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
4684 return -EOPNOTSUPP;
4685
4686 if (test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state))
4687 return -ENOSPC;
4688
4689 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
4690 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
4691 return -EBUSY;
4692
4693 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
4694 return -EBUSY;
4695
4696 fsp = (struct ethtool_rx_flow_spec *)&cmd->fs;
4697
4698
4699 if (i40e_parse_rx_flow_user_data(fsp, &userdef))
4700 return -EINVAL;
4701
4702
4703 if (fsp->flow_type & FLOW_MAC_EXT)
4704 return -EINVAL;
4705
4706 ret = i40e_check_fdir_input_set(vsi, fsp, &userdef);
4707 if (ret)
4708 return ret;
4709
4710 if (fsp->location >= (pf->hw.func_caps.fd_filters_best_effort +
4711 pf->hw.func_caps.fd_filters_guaranteed)) {
4712 return -EINVAL;
4713 }
4714
4715
4716
4717
4718 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
4719 dest_ctl = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
4720 } else {
4721 u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie);
4722 u8 vf = ethtool_get_flow_spec_ring_vf(fsp->ring_cookie);
4723
4724 if (!vf) {
4725 if (ring >= vsi->num_queue_pairs)
4726 return -EINVAL;
4727 dest_vsi = vsi->id;
4728 } else {
4729
4730 vf--;
4731
4732 if (vf >= pf->num_alloc_vfs)
4733 return -EINVAL;
4734 if (ring >= pf->vf[vf].num_queue_pairs)
4735 return -EINVAL;
4736 dest_vsi = pf->vf[vf].lan_vsi_id;
4737 }
4738 dest_ctl = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
4739 q_index = ring;
4740 }
4741
4742 input = kzalloc(sizeof(*input), GFP_KERNEL);
4743
4744 if (!input)
4745 return -ENOMEM;
4746
4747 input->fd_id = fsp->location;
4748 input->q_index = q_index;
4749 input->dest_vsi = dest_vsi;
4750 input->dest_ctl = dest_ctl;
4751 input->fd_status = I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID;
4752 input->cnt_index = I40E_FD_SB_STAT_IDX(pf->hw.pf_id);
4753 input->dst_ip = fsp->h_u.tcp_ip4_spec.ip4src;
4754 input->src_ip = fsp->h_u.tcp_ip4_spec.ip4dst;
4755 input->flow_type = fsp->flow_type & ~FLOW_EXT;
4756
4757 input->vlan_etype = fsp->h_ext.vlan_etype;
4758 if (!fsp->m_ext.vlan_etype && fsp->h_ext.vlan_tci)
4759 input->vlan_etype = cpu_to_be16(ETH_P_8021Q);
4760 if (fsp->m_ext.vlan_tci && input->vlan_etype)
4761 input->vlan_tag = fsp->h_ext.vlan_tci;
4762 if (input->flow_type == IPV6_USER_FLOW ||
4763 input->flow_type == UDP_V6_FLOW ||
4764 input->flow_type == TCP_V6_FLOW ||
4765 input->flow_type == SCTP_V6_FLOW) {
4766
4767
4768
4769
4770 input->ipl4_proto = fsp->h_u.usr_ip6_spec.l4_proto;
4771 input->dst_port = fsp->h_u.tcp_ip6_spec.psrc;
4772 input->src_port = fsp->h_u.tcp_ip6_spec.pdst;
4773 memcpy(input->dst_ip6, fsp->h_u.ah_ip6_spec.ip6src,
4774 sizeof(__be32) * 4);
4775 memcpy(input->src_ip6, fsp->h_u.ah_ip6_spec.ip6dst,
4776 sizeof(__be32) * 4);
4777 } else {
4778
4779
4780
4781
4782 input->ipl4_proto = fsp->h_u.usr_ip4_spec.proto;
4783 input->dst_port = fsp->h_u.tcp_ip4_spec.psrc;
4784 input->src_port = fsp->h_u.tcp_ip4_spec.pdst;
4785 input->dst_ip = fsp->h_u.tcp_ip4_spec.ip4src;
4786 input->src_ip = fsp->h_u.tcp_ip4_spec.ip4dst;
4787 }
4788
4789 if (userdef.flex_filter) {
4790 input->flex_filter = true;
4791 input->flex_word = cpu_to_be16(userdef.flex_word);
4792 input->flex_offset = userdef.flex_offset;
4793 }
4794
4795
4796 ret = i40e_disallow_matching_filters(vsi, input);
4797 if (ret)
4798 goto free_filter_memory;
4799
4800
4801
4802
4803
4804 i40e_update_ethtool_fdir_entry(vsi, input, fsp->location, NULL);
4805 ret = i40e_add_del_fdir(vsi, input, true);
4806 if (ret)
4807 goto remove_sw_rule;
4808 return 0;
4809
4810remove_sw_rule:
4811 hlist_del(&input->fdir_node);
4812 pf->fdir_pf_active_filters--;
4813free_filter_memory:
4814 kfree(input);
4815 return ret;
4816}
4817
4818
4819
4820
4821
4822
4823
4824
4825static int i40e_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
4826{
4827 struct i40e_netdev_priv *np = netdev_priv(netdev);
4828 struct i40e_vsi *vsi = np->vsi;
4829 struct i40e_pf *pf = vsi->back;
4830 int ret = -EOPNOTSUPP;
4831
4832 switch (cmd->cmd) {
4833 case ETHTOOL_SRXFH:
4834 ret = i40e_set_rss_hash_opt(pf, cmd);
4835 break;
4836 case ETHTOOL_SRXCLSRLINS:
4837 ret = i40e_add_fdir_ethtool(vsi, cmd);
4838 break;
4839 case ETHTOOL_SRXCLSRLDEL:
4840 ret = i40e_del_fdir_entry(vsi, cmd);
4841 break;
4842 default:
4843 break;
4844 }
4845
4846 return ret;
4847}
4848
4849
4850
4851
4852
4853static unsigned int i40e_max_channels(struct i40e_vsi *vsi)
4854{
4855
4856 return vsi->alloc_queue_pairs;
4857}
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869static void i40e_get_channels(struct net_device *dev,
4870 struct ethtool_channels *ch)
4871{
4872 struct i40e_netdev_priv *np = netdev_priv(dev);
4873 struct i40e_vsi *vsi = np->vsi;
4874 struct i40e_pf *pf = vsi->back;
4875
4876
4877 ch->max_combined = i40e_max_channels(vsi);
4878
4879
4880 ch->other_count = (pf->flags & I40E_FLAG_FD_SB_ENABLED) ? 1 : 0;
4881 ch->max_other = ch->other_count;
4882
4883
4884 ch->combined_count = vsi->num_queue_pairs;
4885}
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895static int i40e_set_channels(struct net_device *dev,
4896 struct ethtool_channels *ch)
4897{
4898 const u8 drop = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
4899 struct i40e_netdev_priv *np = netdev_priv(dev);
4900 unsigned int count = ch->combined_count;
4901 struct i40e_vsi *vsi = np->vsi;
4902 struct i40e_pf *pf = vsi->back;
4903 struct i40e_fdir_filter *rule;
4904 struct hlist_node *node2;
4905 int new_count;
4906 int err = 0;
4907
4908
4909 if (vsi->type != I40E_VSI_MAIN)
4910 return -EINVAL;
4911
4912
4913
4914
4915 if (pf->flags & I40E_FLAG_TC_MQPRIO)
4916 return -EINVAL;
4917
4918
4919 if (!count || ch->rx_count || ch->tx_count)
4920 return -EINVAL;
4921
4922
4923 if (ch->other_count != ((pf->flags & I40E_FLAG_FD_SB_ENABLED) ? 1 : 0))
4924 return -EINVAL;
4925
4926
4927 if (count > i40e_max_channels(vsi))
4928 return -EINVAL;
4929
4930
4931
4932
4933 hlist_for_each_entry_safe(rule, node2,
4934 &pf->fdir_filter_list, fdir_node) {
4935 if (rule->dest_ctl != drop && count <= rule->q_index) {
4936 dev_warn(&pf->pdev->dev,
4937 "Existing user defined filter %d assigns flow to queue %d\n",
4938 rule->fd_id, rule->q_index);
4939 err = -EINVAL;
4940 }
4941 }
4942
4943 if (err) {
4944 dev_err(&pf->pdev->dev,
4945 "Existing filter rules must be deleted to reduce combined channel count to %d\n",
4946 count);
4947 return err;
4948 }
4949
4950
4951
4952
4953
4954
4955
4956 new_count = i40e_reconfig_rss_queues(pf, count);
4957 if (new_count > 0)
4958 return 0;
4959 else
4960 return -EINVAL;
4961}
4962
4963
4964
4965
4966
4967
4968
4969static u32 i40e_get_rxfh_key_size(struct net_device *netdev)
4970{
4971 return I40E_HKEY_ARRAY_SIZE;
4972}
4973
4974
4975
4976
4977
4978
4979
4980static u32 i40e_get_rxfh_indir_size(struct net_device *netdev)
4981{
4982 return I40E_HLUT_ARRAY_SIZE;
4983}
4984
4985
4986
4987
4988
4989
4990
4991
4992
4993
4994
4995static int i40e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
4996 u8 *hfunc)
4997{
4998 struct i40e_netdev_priv *np = netdev_priv(netdev);
4999 struct i40e_vsi *vsi = np->vsi;
5000 u8 *lut, *seed = NULL;
5001 int ret;
5002 u16 i;
5003
5004 if (hfunc)
5005 *hfunc = ETH_RSS_HASH_TOP;
5006
5007 if (!indir)
5008 return 0;
5009
5010 seed = key;
5011 lut = kzalloc(I40E_HLUT_ARRAY_SIZE, GFP_KERNEL);
5012 if (!lut)
5013 return -ENOMEM;
5014 ret = i40e_get_rss(vsi, seed, lut, I40E_HLUT_ARRAY_SIZE);
5015 if (ret)
5016 goto out;
5017 for (i = 0; i < I40E_HLUT_ARRAY_SIZE; i++)
5018 indir[i] = (u32)(lut[i]);
5019
5020out:
5021 kfree(lut);
5022
5023 return ret;
5024}
5025
5026
5027
5028
5029
5030
5031
5032
5033
5034
5035
5036static int i40e_set_rxfh(struct net_device *netdev, const u32 *indir,
5037 const u8 *key, const u8 hfunc)
5038{
5039 struct i40e_netdev_priv *np = netdev_priv(netdev);
5040 struct i40e_vsi *vsi = np->vsi;
5041 struct i40e_pf *pf = vsi->back;
5042 u8 *seed = NULL;
5043 u16 i;
5044
5045 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)
5046 return -EOPNOTSUPP;
5047
5048 if (key) {
5049 if (!vsi->rss_hkey_user) {
5050 vsi->rss_hkey_user = kzalloc(I40E_HKEY_ARRAY_SIZE,
5051 GFP_KERNEL);
5052 if (!vsi->rss_hkey_user)
5053 return -ENOMEM;
5054 }
5055 memcpy(vsi->rss_hkey_user, key, I40E_HKEY_ARRAY_SIZE);
5056 seed = vsi->rss_hkey_user;
5057 }
5058 if (!vsi->rss_lut_user) {
5059 vsi->rss_lut_user = kzalloc(I40E_HLUT_ARRAY_SIZE, GFP_KERNEL);
5060 if (!vsi->rss_lut_user)
5061 return -ENOMEM;
5062 }
5063
5064
5065 if (indir)
5066 for (i = 0; i < I40E_HLUT_ARRAY_SIZE; i++)
5067 vsi->rss_lut_user[i] = (u8)(indir[i]);
5068 else
5069 i40e_fill_rss_lut(pf, vsi->rss_lut_user, I40E_HLUT_ARRAY_SIZE,
5070 vsi->rss_size);
5071
5072 return i40e_config_rss(vsi, seed, vsi->rss_lut_user,
5073 I40E_HLUT_ARRAY_SIZE);
5074}
5075
5076
5077
5078
5079
5080
5081
5082
5083
5084
5085
5086static u32 i40e_get_priv_flags(struct net_device *dev)
5087{
5088 struct i40e_netdev_priv *np = netdev_priv(dev);
5089 struct i40e_vsi *vsi = np->vsi;
5090 struct i40e_pf *pf = vsi->back;
5091 u32 i, j, ret_flags = 0;
5092
5093 for (i = 0; i < I40E_PRIV_FLAGS_STR_LEN; i++) {
5094 const struct i40e_priv_flags *priv_flags;
5095
5096 priv_flags = &i40e_gstrings_priv_flags[i];
5097
5098 if (priv_flags->flag & pf->flags)
5099 ret_flags |= BIT(i);
5100 }
5101
5102 if (pf->hw.pf_id != 0)
5103 return ret_flags;
5104
5105 for (j = 0; j < I40E_GL_PRIV_FLAGS_STR_LEN; j++) {
5106 const struct i40e_priv_flags *priv_flags;
5107
5108 priv_flags = &i40e_gl_gstrings_priv_flags[j];
5109
5110 if (priv_flags->flag & pf->flags)
5111 ret_flags |= BIT(i + j);
5112 }
5113
5114 return ret_flags;
5115}
5116
5117
5118
5119
5120
5121
5122static int i40e_set_priv_flags(struct net_device *dev, u32 flags)
5123{
5124 struct i40e_netdev_priv *np = netdev_priv(dev);
5125 u64 orig_flags, new_flags, changed_flags;
5126 enum i40e_admin_queue_err adq_err;
5127 struct i40e_vsi *vsi = np->vsi;
5128 struct i40e_pf *pf = vsi->back;
5129 u32 reset_needed = 0;
5130 i40e_status status;
5131 u32 i, j;
5132
5133 orig_flags = READ_ONCE(pf->flags);
5134 new_flags = orig_flags;
5135
5136 for (i = 0; i < I40E_PRIV_FLAGS_STR_LEN; i++) {
5137 const struct i40e_priv_flags *priv_flags;
5138
5139 priv_flags = &i40e_gstrings_priv_flags[i];
5140
5141 if (flags & BIT(i))
5142 new_flags |= priv_flags->flag;
5143 else
5144 new_flags &= ~(priv_flags->flag);
5145
5146
5147 if (priv_flags->read_only &&
5148 ((orig_flags ^ new_flags) & ~BIT(i)))
5149 return -EOPNOTSUPP;
5150 }
5151
5152 if (pf->hw.pf_id != 0)
5153 goto flags_complete;
5154
5155 for (j = 0; j < I40E_GL_PRIV_FLAGS_STR_LEN; j++) {
5156 const struct i40e_priv_flags *priv_flags;
5157
5158 priv_flags = &i40e_gl_gstrings_priv_flags[j];
5159
5160 if (flags & BIT(i + j))
5161 new_flags |= priv_flags->flag;
5162 else
5163 new_flags &= ~(priv_flags->flag);
5164
5165
5166 if (priv_flags->read_only &&
5167 ((orig_flags ^ new_flags) & ~BIT(i)))
5168 return -EOPNOTSUPP;
5169 }
5170
5171flags_complete:
5172 changed_flags = orig_flags ^ new_flags;
5173
5174 if (changed_flags & I40E_FLAG_DISABLE_FW_LLDP)
5175 reset_needed = I40E_PF_RESET_AND_REBUILD_FLAG;
5176 if (changed_flags & (I40E_FLAG_VEB_STATS_ENABLED |
5177 I40E_FLAG_LEGACY_RX | I40E_FLAG_SOURCE_PRUNING_DISABLED))
5178 reset_needed = BIT(__I40E_PF_RESET_REQUESTED);
5179
5180
5181
5182
5183
5184
5185 if ((new_flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) &&
5186 !(pf->hw_features & I40E_HW_ATR_EVICT_CAPABLE))
5187 return -EOPNOTSUPP;
5188
5189
5190
5191
5192
5193
5194
5195
5196
5197 if (changed_flags & I40E_FLAG_DISABLE_FW_LLDP) {
5198 if (!(pf->hw.flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE)) {
5199 dev_warn(&pf->pdev->dev,
5200 "Device does not support changing FW LLDP\n");
5201 return -EOPNOTSUPP;
5202 }
5203 }
5204
5205 if (changed_flags & I40E_FLAG_RS_FEC &&
5206 pf->hw.device_id != I40E_DEV_ID_25G_SFP28 &&
5207 pf->hw.device_id != I40E_DEV_ID_25G_B) {
5208 dev_warn(&pf->pdev->dev,
5209 "Device does not support changing FEC configuration\n");
5210 return -EOPNOTSUPP;
5211 }
5212
5213 if (changed_flags & I40E_FLAG_BASE_R_FEC &&
5214 pf->hw.device_id != I40E_DEV_ID_25G_SFP28 &&
5215 pf->hw.device_id != I40E_DEV_ID_25G_B &&
5216 pf->hw.device_id != I40E_DEV_ID_KX_X722) {
5217 dev_warn(&pf->pdev->dev,
5218 "Device does not support changing FEC configuration\n");
5219 return -EOPNOTSUPP;
5220 }
5221
5222
5223
5224
5225
5226
5227
5228 if ((changed_flags & I40E_FLAG_FD_ATR_ENABLED) &&
5229 !(new_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5230 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
5231 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
5232 }
5233
5234 if (changed_flags & I40E_FLAG_TRUE_PROMISC_SUPPORT) {
5235 u16 sw_flags = 0, valid_flags = 0;
5236 int ret;
5237
5238 if (!(new_flags & I40E_FLAG_TRUE_PROMISC_SUPPORT))
5239 sw_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
5240 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
5241 ret = i40e_aq_set_switch_config(&pf->hw, sw_flags, valid_flags,
5242 0, NULL);
5243 if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
5244 dev_info(&pf->pdev->dev,
5245 "couldn't set switch config bits, err %s aq_err %s\n",
5246 i40e_stat_str(&pf->hw, ret),
5247 i40e_aq_str(&pf->hw,
5248 pf->hw.aq.asq_last_status));
5249
5250 }
5251 }
5252
5253 if ((changed_flags & I40E_FLAG_RS_FEC) ||
5254 (changed_flags & I40E_FLAG_BASE_R_FEC)) {
5255 u8 fec_cfg = 0;
5256
5257 if (new_flags & I40E_FLAG_RS_FEC &&
5258 new_flags & I40E_FLAG_BASE_R_FEC) {
5259 fec_cfg = I40E_AQ_SET_FEC_AUTO;
5260 } else if (new_flags & I40E_FLAG_RS_FEC) {
5261 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_RS |
5262 I40E_AQ_SET_FEC_ABILITY_RS);
5263 } else if (new_flags & I40E_FLAG_BASE_R_FEC) {
5264 fec_cfg = (I40E_AQ_SET_FEC_REQUEST_KR |
5265 I40E_AQ_SET_FEC_ABILITY_KR);
5266 }
5267 if (i40e_set_fec_cfg(dev, fec_cfg))
5268 dev_warn(&pf->pdev->dev, "Cannot change FEC config\n");
5269 }
5270
5271 if ((changed_flags & I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED) &&
5272 (orig_flags & I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED)) {
5273 dev_err(&pf->pdev->dev,
5274 "Setting link-down-on-close not supported on this port (because total-port-shutdown is enabled)\n");
5275 return -EOPNOTSUPP;
5276 }
5277
5278 if ((changed_flags & new_flags &
5279 I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED) &&
5280 (new_flags & I40E_FLAG_MFP_ENABLED))
5281 dev_warn(&pf->pdev->dev,
5282 "Turning on link-down-on-close flag may affect other partitions\n");
5283
5284 if (changed_flags & I40E_FLAG_DISABLE_FW_LLDP) {
5285 if (new_flags & I40E_FLAG_DISABLE_FW_LLDP) {
5286#ifdef CONFIG_I40E_DCB
5287 i40e_dcb_sw_default_config(pf);
5288#endif
5289 i40e_aq_cfg_lldp_mib_change_event(&pf->hw, false, NULL);
5290 i40e_aq_stop_lldp(&pf->hw, true, false, NULL);
5291 } else {
5292 status = i40e_aq_start_lldp(&pf->hw, false, NULL);
5293 if (status) {
5294 adq_err = pf->hw.aq.asq_last_status;
5295 switch (adq_err) {
5296 case I40E_AQ_RC_EEXIST:
5297 dev_warn(&pf->pdev->dev,
5298 "FW LLDP agent is already running\n");
5299 reset_needed = 0;
5300 break;
5301 case I40E_AQ_RC_EPERM:
5302 dev_warn(&pf->pdev->dev,
5303 "Device configuration forbids SW from starting the LLDP agent.\n");
5304 return -EINVAL;
5305 case I40E_AQ_RC_EAGAIN:
5306 dev_warn(&pf->pdev->dev,
5307 "Stop FW LLDP agent command is still being processed, please try again in a second.\n");
5308 return -EBUSY;
5309 default:
5310 dev_warn(&pf->pdev->dev,
5311 "Starting FW LLDP agent failed: error: %s, %s\n",
5312 i40e_stat_str(&pf->hw,
5313 status),
5314 i40e_aq_str(&pf->hw,
5315 adq_err));
5316 return -EINVAL;
5317 }
5318 }
5319 }
5320 }
5321
5322
5323
5324
5325
5326
5327 pf->flags = new_flags;
5328
5329
5330
5331
5332 if (reset_needed)
5333 i40e_do_reset(pf, reset_needed, true);
5334
5335 return 0;
5336}
5337
5338
5339
5340
5341
5342
5343static int i40e_get_module_info(struct net_device *netdev,
5344 struct ethtool_modinfo *modinfo)
5345{
5346 struct i40e_netdev_priv *np = netdev_priv(netdev);
5347 struct i40e_vsi *vsi = np->vsi;
5348 struct i40e_pf *pf = vsi->back;
5349 struct i40e_hw *hw = &pf->hw;
5350 u32 sff8472_comp = 0;
5351 u32 sff8472_swap = 0;
5352 u32 sff8636_rev = 0;
5353 i40e_status status;
5354 u32 type = 0;
5355
5356
5357 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
5358 netdev_err(vsi->netdev, "Module EEPROM memory read not supported. Please update the NVM image.\n");
5359 return -EINVAL;
5360 }
5361
5362 status = i40e_update_link_info(hw);
5363 if (status)
5364 return -EIO;
5365
5366 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
5367 netdev_err(vsi->netdev, "Cannot read module EEPROM memory. No module connected.\n");
5368 return -EINVAL;
5369 }
5370
5371 type = hw->phy.link_info.module_type[0];
5372
5373 switch (type) {
5374 case I40E_MODULE_TYPE_SFP:
5375 status = i40e_aq_get_phy_register(hw,
5376 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5377 I40E_I2C_EEPROM_DEV_ADDR, true,
5378 I40E_MODULE_SFF_8472_COMP,
5379 &sff8472_comp, NULL);
5380 if (status)
5381 return -EIO;
5382
5383 status = i40e_aq_get_phy_register(hw,
5384 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5385 I40E_I2C_EEPROM_DEV_ADDR, true,
5386 I40E_MODULE_SFF_8472_SWAP,
5387 &sff8472_swap, NULL);
5388 if (status)
5389 return -EIO;
5390
5391
5392
5393
5394 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
5395 netdev_warn(vsi->netdev, "Module address swap to access page 0xA2 is not supported.\n");
5396 modinfo->type = ETH_MODULE_SFF_8079;
5397 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
5398 } else if (sff8472_comp == 0x00) {
5399
5400 modinfo->type = ETH_MODULE_SFF_8079;
5401 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
5402 } else if (!(sff8472_swap & I40E_MODULE_SFF_DDM_IMPLEMENTED)) {
5403
5404
5405
5406 modinfo->type = ETH_MODULE_SFF_8079;
5407 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
5408 } else {
5409 modinfo->type = ETH_MODULE_SFF_8472;
5410 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
5411 }
5412 break;
5413 case I40E_MODULE_TYPE_QSFP_PLUS:
5414
5415 status = i40e_aq_get_phy_register(hw,
5416 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5417 0, true,
5418 I40E_MODULE_REVISION_ADDR,
5419 &sff8636_rev, NULL);
5420 if (status)
5421 return -EIO;
5422
5423 if (sff8636_rev > 0x02) {
5424
5425 modinfo->type = ETH_MODULE_SFF_8636;
5426 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
5427 } else {
5428 modinfo->type = ETH_MODULE_SFF_8436;
5429 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
5430 }
5431 break;
5432 case I40E_MODULE_TYPE_QSFP28:
5433 modinfo->type = ETH_MODULE_SFF_8636;
5434 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
5435 break;
5436 default:
5437 netdev_err(vsi->netdev, "Module type unrecognized\n");
5438 return -EINVAL;
5439 }
5440 return 0;
5441}
5442
5443
5444
5445
5446
5447
5448
5449static int i40e_get_module_eeprom(struct net_device *netdev,
5450 struct ethtool_eeprom *ee,
5451 u8 *data)
5452{
5453 struct i40e_netdev_priv *np = netdev_priv(netdev);
5454 struct i40e_vsi *vsi = np->vsi;
5455 struct i40e_pf *pf = vsi->back;
5456 struct i40e_hw *hw = &pf->hw;
5457 bool is_sfp = false;
5458 i40e_status status;
5459 u32 value = 0;
5460 int i;
5461
5462 if (!ee || !ee->len || !data)
5463 return -EINVAL;
5464
5465 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
5466 is_sfp = true;
5467
5468 for (i = 0; i < ee->len; i++) {
5469 u32 offset = i + ee->offset;
5470 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
5471
5472
5473 if (is_sfp) {
5474 if (offset >= ETH_MODULE_SFF_8079_LEN) {
5475 offset -= ETH_MODULE_SFF_8079_LEN;
5476 addr = I40E_I2C_EEPROM_DEV_ADDR2;
5477 }
5478 } else {
5479 while (offset >= ETH_MODULE_SFF_8436_LEN) {
5480
5481 offset -= ETH_MODULE_SFF_8436_LEN / 2;
5482 addr++;
5483 }
5484 }
5485
5486 status = i40e_aq_get_phy_register(hw,
5487 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
5488 addr, true, offset, &value, NULL);
5489 if (status)
5490 return -EIO;
5491 data[i] = value;
5492 }
5493 return 0;
5494}
5495
5496static int i40e_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
5497{
5498 struct i40e_netdev_priv *np = netdev_priv(netdev);
5499 struct i40e_aq_get_phy_abilities_resp phy_cfg;
5500 enum i40e_status_code status = 0;
5501 struct i40e_vsi *vsi = np->vsi;
5502 struct i40e_pf *pf = vsi->back;
5503 struct i40e_hw *hw = &pf->hw;
5504
5505
5506 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_cfg, NULL);
5507 if (status)
5508 return -EAGAIN;
5509
5510
5511
5512
5513 if (phy_cfg.eee_capability == 0)
5514 return -EOPNOTSUPP;
5515
5516 edata->supported = SUPPORTED_Autoneg;
5517 edata->lp_advertised = edata->supported;
5518
5519
5520 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_cfg, NULL);
5521 if (status)
5522 return -EAGAIN;
5523
5524 edata->advertised = phy_cfg.eee_capability ? SUPPORTED_Autoneg : 0U;
5525 edata->eee_enabled = !!edata->advertised;
5526 edata->tx_lpi_enabled = pf->stats.tx_lpi_status;
5527
5528 edata->eee_active = pf->stats.tx_lpi_status && pf->stats.rx_lpi_status;
5529
5530 return 0;
5531}
5532
5533static int i40e_is_eee_param_supported(struct net_device *netdev,
5534 struct ethtool_eee *edata)
5535{
5536 struct i40e_netdev_priv *np = netdev_priv(netdev);
5537 struct i40e_vsi *vsi = np->vsi;
5538 struct i40e_pf *pf = vsi->back;
5539 struct i40e_ethtool_not_used {
5540 u32 value;
5541 const char *name;
5542 } param[] = {
5543 {edata->advertised & ~SUPPORTED_Autoneg, "advertise"},
5544 {edata->tx_lpi_timer, "tx-timer"},
5545 {edata->tx_lpi_enabled != pf->stats.tx_lpi_status, "tx-lpi"}
5546 };
5547 int i;
5548
5549 for (i = 0; i < ARRAY_SIZE(param); i++) {
5550 if (param[i].value) {
5551 netdev_info(netdev,
5552 "EEE setting %s not supported\n",
5553 param[i].name);
5554 return -EOPNOTSUPP;
5555 }
5556 }
5557
5558 return 0;
5559}
5560
5561static int i40e_set_eee(struct net_device *netdev, struct ethtool_eee *edata)
5562{
5563 struct i40e_netdev_priv *np = netdev_priv(netdev);
5564 struct i40e_aq_get_phy_abilities_resp abilities;
5565 enum i40e_status_code status = I40E_SUCCESS;
5566 struct i40e_aq_set_phy_config config;
5567 struct i40e_vsi *vsi = np->vsi;
5568 struct i40e_pf *pf = vsi->back;
5569 struct i40e_hw *hw = &pf->hw;
5570 __le16 eee_capability;
5571
5572
5573 if (i40e_is_eee_param_supported(netdev, edata))
5574 return -EOPNOTSUPP;
5575
5576
5577 status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities,
5578 NULL);
5579 if (status)
5580 return -EAGAIN;
5581
5582
5583
5584
5585 if (abilities.eee_capability == 0)
5586 return -EOPNOTSUPP;
5587
5588
5589 eee_capability = abilities.eee_capability;
5590
5591
5592 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
5593 NULL);
5594 if (status)
5595 return -EAGAIN;
5596
5597
5598 config.phy_type = abilities.phy_type;
5599 config.phy_type_ext = abilities.phy_type_ext;
5600 config.link_speed = abilities.link_speed;
5601 config.abilities = abilities.abilities |
5602 I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
5603 config.eeer = abilities.eeer_val;
5604 config.low_power_ctrl = abilities.d3_lpan;
5605 config.fec_config = abilities.fec_cfg_curr_mod_ext_info &
5606 I40E_AQ_PHY_FEC_CONFIG_MASK;
5607
5608
5609 if (edata->eee_enabled) {
5610 config.eee_capability = eee_capability;
5611 config.eeer |= cpu_to_le32(I40E_PRTPM_EEER_TX_LPI_EN_MASK);
5612 } else {
5613 config.eee_capability = 0;
5614 config.eeer &= cpu_to_le32(~I40E_PRTPM_EEER_TX_LPI_EN_MASK);
5615 }
5616
5617
5618 status = i40e_aq_set_phy_config(hw, &config, NULL);
5619 if (status)
5620 return -EAGAIN;
5621
5622 return 0;
5623}
5624
5625static const struct ethtool_ops i40e_ethtool_recovery_mode_ops = {
5626 .get_drvinfo = i40e_get_drvinfo,
5627 .set_eeprom = i40e_set_eeprom,
5628 .get_eeprom_len = i40e_get_eeprom_len,
5629 .get_eeprom = i40e_get_eeprom,
5630};
5631
5632static const struct ethtool_ops i40e_ethtool_ops = {
5633 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
5634 ETHTOOL_COALESCE_MAX_FRAMES_IRQ |
5635 ETHTOOL_COALESCE_USE_ADAPTIVE |
5636 ETHTOOL_COALESCE_RX_USECS_HIGH |
5637 ETHTOOL_COALESCE_TX_USECS_HIGH,
5638 .get_drvinfo = i40e_get_drvinfo,
5639 .get_regs_len = i40e_get_regs_len,
5640 .get_regs = i40e_get_regs,
5641 .nway_reset = i40e_nway_reset,
5642 .get_link = ethtool_op_get_link,
5643 .get_wol = i40e_get_wol,
5644 .set_wol = i40e_set_wol,
5645 .set_eeprom = i40e_set_eeprom,
5646 .get_eeprom_len = i40e_get_eeprom_len,
5647 .get_eeprom = i40e_get_eeprom,
5648 .get_ringparam = i40e_get_ringparam,
5649 .set_ringparam = i40e_set_ringparam,
5650 .get_pauseparam = i40e_get_pauseparam,
5651 .set_pauseparam = i40e_set_pauseparam,
5652 .get_msglevel = i40e_get_msglevel,
5653 .set_msglevel = i40e_set_msglevel,
5654 .get_rxnfc = i40e_get_rxnfc,
5655 .set_rxnfc = i40e_set_rxnfc,
5656 .self_test = i40e_diag_test,
5657 .get_strings = i40e_get_strings,
5658 .get_eee = i40e_get_eee,
5659 .set_eee = i40e_set_eee,
5660 .set_phys_id = i40e_set_phys_id,
5661 .get_sset_count = i40e_get_sset_count,
5662 .get_ethtool_stats = i40e_get_ethtool_stats,
5663 .get_coalesce = i40e_get_coalesce,
5664 .set_coalesce = i40e_set_coalesce,
5665 .get_rxfh_key_size = i40e_get_rxfh_key_size,
5666 .get_rxfh_indir_size = i40e_get_rxfh_indir_size,
5667 .get_rxfh = i40e_get_rxfh,
5668 .set_rxfh = i40e_set_rxfh,
5669 .get_channels = i40e_get_channels,
5670 .set_channels = i40e_set_channels,
5671 .get_module_info = i40e_get_module_info,
5672 .get_module_eeprom = i40e_get_module_eeprom,
5673 .get_ts_info = i40e_get_ts_info,
5674 .get_priv_flags = i40e_get_priv_flags,
5675 .set_priv_flags = i40e_set_priv_flags,
5676 .get_per_queue_coalesce = i40e_get_per_queue_coalesce,
5677 .set_per_queue_coalesce = i40e_set_per_queue_coalesce,
5678 .get_link_ksettings = i40e_get_link_ksettings,
5679 .set_link_ksettings = i40e_set_link_ksettings,
5680 .get_fecparam = i40e_get_fec_param,
5681 .set_fecparam = i40e_set_fec_param,
5682 .flash_device = i40e_ddp_flash,
5683};
5684
5685void i40e_set_ethtool_ops(struct net_device *netdev)
5686{
5687 struct i40e_netdev_priv *np = netdev_priv(netdev);
5688 struct i40e_pf *pf = np->vsi->back;
5689
5690 if (!test_bit(__I40E_RECOVERY_MODE, pf->state))
5691 netdev->ethtool_ops = &i40e_ethtool_ops;
5692 else
5693 netdev->ethtool_ops = &i40e_ethtool_recovery_mode_ops;
5694}
5695