1
2
3
4#ifndef _IGC_HW_H_
5#define _IGC_HW_H_
6
7#include <linux/types.h>
8#include <linux/if_ether.h>
9#include <linux/netdevice.h>
10
11#include "igc_regs.h"
12#include "igc_defines.h"
13#include "igc_mac.h"
14#include "igc_phy.h"
15#include "igc_nvm.h"
16#include "igc_i225.h"
17#include "igc_base.h"
18
19#define IGC_DEV_ID_I225_LM 0x15F2
20#define IGC_DEV_ID_I225_V 0x15F3
21#define IGC_DEV_ID_I225_I 0x15F8
22#define IGC_DEV_ID_I220_V 0x15F7
23#define IGC_DEV_ID_I225_K 0x3100
24#define IGC_DEV_ID_I225_K2 0x3101
25#define IGC_DEV_ID_I226_K 0x3102
26#define IGC_DEV_ID_I225_LMVP 0x5502
27#define IGC_DEV_ID_I226_LMVP 0x5503
28#define IGC_DEV_ID_I225_IT 0x0D9F
29#define IGC_DEV_ID_I226_LM 0x125B
30#define IGC_DEV_ID_I226_V 0x125C
31#define IGC_DEV_ID_I226_IT 0x125D
32#define IGC_DEV_ID_I221_V 0x125E
33#define IGC_DEV_ID_I226_BLANK_NVM 0x125F
34#define IGC_DEV_ID_I225_BLANK_NVM 0x15FD
35
36
37struct igc_mac_operations {
38 s32 (*check_for_link)(struct igc_hw *hw);
39 s32 (*reset_hw)(struct igc_hw *hw);
40 s32 (*init_hw)(struct igc_hw *hw);
41 s32 (*setup_physical_interface)(struct igc_hw *hw);
42 void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index);
43 s32 (*read_mac_addr)(struct igc_hw *hw);
44 s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed,
45 u16 *duplex);
46 s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask);
47 void (*release_swfw_sync)(struct igc_hw *hw, u16 mask);
48};
49
50enum igc_mac_type {
51 igc_undefined = 0,
52 igc_i225,
53 igc_num_macs
54};
55
56enum igc_phy_type {
57 igc_phy_unknown = 0,
58 igc_phy_none,
59 igc_phy_i225,
60};
61
62enum igc_media_type {
63 igc_media_type_unknown = 0,
64 igc_media_type_copper = 1,
65 igc_num_media_types
66};
67
68enum igc_nvm_type {
69 igc_nvm_unknown = 0,
70 igc_nvm_eeprom_spi,
71 igc_nvm_flash_hw,
72 igc_nvm_invm,
73};
74
75struct igc_info {
76 s32 (*get_invariants)(struct igc_hw *hw);
77 struct igc_mac_operations *mac_ops;
78 const struct igc_phy_operations *phy_ops;
79 struct igc_nvm_operations *nvm_ops;
80};
81
82extern const struct igc_info igc_base_info;
83
84struct igc_mac_info {
85 struct igc_mac_operations ops;
86
87 u8 addr[ETH_ALEN];
88 u8 perm_addr[ETH_ALEN];
89
90 enum igc_mac_type type;
91
92 u32 mc_filter_type;
93
94 u16 mta_reg_count;
95 u16 uta_reg_count;
96
97 u32 mta_shadow[MAX_MTA_REG];
98 u16 rar_entry_count;
99
100 u8 forced_speed_duplex;
101
102 bool asf_firmware_present;
103 bool arc_subsystem_valid;
104
105 bool autoneg;
106 bool autoneg_failed;
107 bool get_link_status;
108};
109
110struct igc_nvm_operations {
111 s32 (*acquire)(struct igc_hw *hw);
112 s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
113 void (*release)(struct igc_hw *hw);
114 s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data);
115 s32 (*update)(struct igc_hw *hw);
116 s32 (*validate)(struct igc_hw *hw);
117};
118
119struct igc_phy_operations {
120 s32 (*acquire)(struct igc_hw *hw);
121 s32 (*check_reset_block)(struct igc_hw *hw);
122 s32 (*force_speed_duplex)(struct igc_hw *hw);
123 s32 (*get_phy_info)(struct igc_hw *hw);
124 s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data);
125 void (*release)(struct igc_hw *hw);
126 s32 (*reset)(struct igc_hw *hw);
127 s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data);
128};
129
130struct igc_nvm_info {
131 struct igc_nvm_operations ops;
132 enum igc_nvm_type type;
133
134 u16 word_size;
135 u16 delay_usec;
136 u16 address_bits;
137 u16 opcode_bits;
138 u16 page_size;
139};
140
141struct igc_phy_info {
142 struct igc_phy_operations ops;
143
144 enum igc_phy_type type;
145
146 u32 addr;
147 u32 id;
148 u32 reset_delay_us;
149 u32 revision;
150
151 enum igc_media_type media_type;
152
153 u16 autoneg_advertised;
154 u16 autoneg_mask;
155
156 u8 mdix;
157
158 bool is_mdix;
159 bool speed_downgraded;
160 bool autoneg_wait_to_complete;
161};
162
163struct igc_bus_info {
164 u16 func;
165 u16 pci_cmd_word;
166};
167
168enum igc_fc_mode {
169 igc_fc_none = 0,
170 igc_fc_rx_pause,
171 igc_fc_tx_pause,
172 igc_fc_full,
173 igc_fc_default = 0xFF
174};
175
176struct igc_fc_info {
177 u32 high_water;
178 u32 low_water;
179 u16 pause_time;
180 bool send_xon;
181 bool strict_ieee;
182 enum igc_fc_mode current_mode;
183 enum igc_fc_mode requested_mode;
184};
185
186struct igc_dev_spec_base {
187 bool clear_semaphore_once;
188 bool eee_enable;
189};
190
191struct igc_hw {
192 void *back;
193
194 u8 __iomem *hw_addr;
195 unsigned long io_base;
196
197 struct igc_mac_info mac;
198 struct igc_fc_info fc;
199 struct igc_nvm_info nvm;
200 struct igc_phy_info phy;
201
202 struct igc_bus_info bus;
203
204 union {
205 struct igc_dev_spec_base _base;
206 } dev_spec;
207
208 u16 device_id;
209 u16 subsystem_vendor_id;
210 u16 subsystem_device_id;
211 u16 vendor_id;
212
213 u8 revision_id;
214};
215
216
217struct igc_hw_stats {
218 u64 crcerrs;
219 u64 algnerrc;
220 u64 symerrs;
221 u64 rxerrc;
222 u64 mpc;
223 u64 scc;
224 u64 ecol;
225 u64 mcc;
226 u64 latecol;
227 u64 colc;
228 u64 dc;
229 u64 tncrs;
230 u64 sec;
231 u64 cexterr;
232 u64 rlec;
233 u64 xonrxc;
234 u64 xontxc;
235 u64 xoffrxc;
236 u64 xofftxc;
237 u64 fcruc;
238 u64 prc64;
239 u64 prc127;
240 u64 prc255;
241 u64 prc511;
242 u64 prc1023;
243 u64 prc1522;
244 u64 tlpic;
245 u64 rlpic;
246 u64 gprc;
247 u64 bprc;
248 u64 mprc;
249 u64 gptc;
250 u64 gorc;
251 u64 gotc;
252 u64 rnbc;
253 u64 ruc;
254 u64 rfc;
255 u64 roc;
256 u64 rjc;
257 u64 mgprc;
258 u64 mgpdc;
259 u64 mgptc;
260 u64 tor;
261 u64 tot;
262 u64 tpr;
263 u64 tpt;
264 u64 ptc64;
265 u64 ptc127;
266 u64 ptc255;
267 u64 ptc511;
268 u64 ptc1023;
269 u64 ptc1522;
270 u64 mptc;
271 u64 bptc;
272 u64 tsctc;
273 u64 tsctfc;
274 u64 iac;
275 u64 htdpmc;
276 u64 rpthc;
277 u64 hgptc;
278 u64 hgorc;
279 u64 hgotc;
280 u64 lenerrs;
281 u64 scvpc;
282 u64 hrmpc;
283 u64 doosync;
284 u64 o2bgptc;
285 u64 o2bspc;
286 u64 b2ospc;
287 u64 b2ogprc;
288};
289
290struct net_device *igc_get_hw_dev(struct igc_hw *hw);
291#define hw_dbg(format, arg...) \
292 netdev_dbg(igc_get_hw_dev(hw), format, ##arg)
293
294s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
295s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
296void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
297void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
298
299#endif
300
