1/* MOXA ART Ethernet (RTL8201CP) driver. 2 * 3 * Copyright (C) 2013 Jonas Jensen 4 * 5 * Jonas Jensen <jonas.jensen@gmail.com> 6 * 7 * Based on code from 8 * Moxa Technology Co., Ltd. <www.moxa.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15#ifndef _MOXART_ETHERNET_H 16#define _MOXART_ETHERNET_H 17 18#define TX_REG_OFFSET_DESC0 0 19#define TX_REG_OFFSET_DESC1 4 20#define TX_REG_OFFSET_DESC2 8 21#define TX_REG_DESC_SIZE 16 22 23#define RX_REG_OFFSET_DESC0 0 24#define RX_REG_OFFSET_DESC1 4 25#define RX_REG_OFFSET_DESC2 8 26#define RX_REG_DESC_SIZE 16 27 28#define TX_DESC0_PKT_LATE_COL 0x1 /* abort, late collision */ 29#define TX_DESC0_RX_PKT_EXS_COL 0x2 /* abort, >16 collisions */ 30#define TX_DESC0_DMA_OWN 0x80000000 /* owned by controller */ 31#define TX_DESC1_BUF_SIZE_MASK 0x7ff 32#define TX_DESC1_LTS 0x8000000 /* last TX packet */ 33#define TX_DESC1_FTS 0x10000000 /* first TX packet */ 34#define TX_DESC1_FIFO_COMPLETE 0x20000000 35#define TX_DESC1_INTR_COMPLETE 0x40000000 36#define TX_DESC1_END 0x80000000 37#define TX_DESC2_ADDRESS_PHYS 0 38#define TX_DESC2_ADDRESS_VIRT 4 39 40#define RX_DESC0_FRAME_LEN 0 41#define RX_DESC0_FRAME_LEN_MASK 0x7FF 42#define RX_DESC0_MULTICAST 0x10000 43#define RX_DESC0_BROADCAST 0x20000 44#define RX_DESC0_ERR 0x40000 45#define RX_DESC0_CRC_ERR 0x80000 46#define RX_DESC0_FTL 0x100000 47#define RX_DESC0_RUNT 0x200000 /* packet less than 64 bytes */ 48#define RX_DESC0_ODD_NB 0x400000 /* receive odd nibbles */ 49#define RX_DESC0_LRS 0x10000000 /* last receive segment */ 50#define RX_DESC0_FRS 0x20000000 /* first receive segment */ 51#define RX_DESC0_DMA_OWN 0x80000000 52#define RX_DESC1_BUF_SIZE_MASK 0x7FF 53#define RX_DESC1_END 0x80000000 54#define RX_DESC2_ADDRESS_PHYS 0 55#define RX_DESC2_ADDRESS_VIRT 4 56 57#define TX_DESC_NUM 64 58#define TX_DESC_NUM_MASK (TX_DESC_NUM - 1) 59#define TX_NEXT(N) (((N) + 1) & (TX_DESC_NUM_MASK)) 60#define TX_BUF_SIZE 1600 61#define TX_BUF_SIZE_MAX (TX_DESC1_BUF_SIZE_MASK + 1) 62#define TX_WAKE_THRESHOLD 16 63 64#define RX_DESC_NUM 64 65#define RX_DESC_NUM_MASK (RX_DESC_NUM - 1) 66#define RX_NEXT(N) (((N) + 1) & (RX_DESC_NUM_MASK)) 67#define RX_BUF_SIZE 1600 68#define RX_BUF_SIZE_MAX (RX_DESC1_BUF_SIZE_MASK + 1) 69 70#define REG_INTERRUPT_STATUS 0 71#define REG_INTERRUPT_MASK 4 72#define REG_MAC_MS_ADDRESS 8 73#define REG_MAC_LS_ADDRESS 12 74#define REG_MCAST_HASH_TABLE0 16 75#define REG_MCAST_HASH_TABLE1 20 76#define REG_TX_POLL_DEMAND 24 77#define REG_RX_POLL_DEMAND 28 78#define REG_TXR_BASE_ADDRESS 32 79#define REG_RXR_BASE_ADDRESS 36 80#define REG_INT_TIMER_CTRL 40 81#define REG_APOLL_TIMER_CTRL 44 82#define REG_DMA_BLEN_CTRL 48 83#define REG_RESERVED1 52 84#define REG_MAC_CTRL 136 85#define REG_MAC_STATUS 140 86#define REG_PHY_CTRL 144 87#define REG_PHY_WRITE_DATA 148 88#define REG_FLOW_CTRL 152 89#define REG_BACK_PRESSURE 156 90#define REG_RESERVED2 160 91#define REG_TEST_SEED 196 92#define REG_DMA_FIFO_STATE 200 93#define REG_TEST_MODE 204 94#define REG_RESERVED3 208 95#define REG_TX_COL_COUNTER 212 96#define REG_RPF_AEP_COUNTER 216 97#define REG_XM_PG_COUNTER 220 98#define REG_RUNT_TLC_COUNTER 224 99#define REG_CRC_FTL_COUNTER 228 100#define REG_RLC_RCC_COUNTER 232 101#define REG_BROC_COUNTER 236 102#define REG_MULCA_COUNTER 240 103#define REG_RP_COUNTER 244 104#define REG_XP_COUNTER 248 105 106#define REG_PHY_CTRL_OFFSET 0x0 107#define REG_PHY_STATUS 0x1 108#define REG_PHY_ID1 0x2 109#define REG_PHY_ID2 0x3 110#define REG_PHY_ANA 0x4 111#define REG_PHY_ANLPAR 0x5 112#define REG_PHY_ANE 0x6 113#define REG_PHY_ECTRL1 0x10 114#define REG_PHY_QPDS 0x11 115#define REG_PHY_10BOP 0x12 116#define REG_PHY_ECTRL2 0x13 117#define REG_PHY_FTMAC100_WRITE 0x8000000 118#define REG_PHY_FTMAC100_READ 0x4000000 119 120/* REG_INTERRUPT_STATUS */ 121#define RPKT_FINISH BIT(0) /* DMA data received */ 122#define NORXBUF BIT(1) /* receive buffer unavailable */ 123#define XPKT_FINISH BIT(2) /* DMA moved data to TX FIFO */ 124#define NOTXBUF BIT(3) /* transmit buffer unavailable */ 125#define XPKT_OK_INT_STS BIT(4) /* transmit to ethernet success */ 126#define XPKT_LOST_INT_STS BIT(5) /* transmit ethernet lost (collision) */ 127#define RPKT_SAV BIT(6) /* FIFO receive success */ 128#define RPKT_LOST_INT_STS BIT(7) /* FIFO full, receive failed */ 129#define AHB_ERR BIT(8) /* AHB error */ 130#define PHYSTS_CHG BIT(9) /* PHY link status change */ 131 132/* REG_INTERRUPT_MASK */ 133#define RPKT_FINISH_M BIT(0) 134#define NORXBUF_M BIT(1) 135#define XPKT_FINISH_M BIT(2) 136#define NOTXBUF_M BIT(3) 137#define XPKT_OK_M BIT(4) 138#define XPKT_LOST_M BIT(5) 139#define RPKT_SAV_M BIT(6) 140#define RPKT_LOST_M BIT(7) 141#define AHB_ERR_M BIT(8) 142#define PHYSTS_CHG_M BIT(9) 143 144/* REG_MAC_MS_ADDRESS */ 145#define MAC_MADR_MASK 0xffff /* 2 MSB MAC address */ 146 147/* REG_INT_TIMER_CTRL */ 148#define TXINT_TIME_SEL BIT(15) /* TX cycle time period */ 149#define TXINT_THR_MASK 0x7000 150#define TXINT_CNT_MASK 0xf00 151#define RXINT_TIME_SEL BIT(7) /* RX cycle time period */ 152#define RXINT_THR_MASK 0x70 153#define RXINT_CNT_MASK 0xF 154 155/* REG_APOLL_TIMER_CTRL */ 156#define TXPOLL_TIME_SEL BIT(12) /* TX poll time period */ 157#define TXPOLL_CNT_MASK 0xf00 158#define TXPOLL_CNT_SHIFT_BIT 8 159#define RXPOLL_TIME_SEL BIT(4) /* RX poll time period */ 160#define RXPOLL_CNT_MASK 0xF 161#define RXPOLL_CNT_SHIFT_BIT 0 162 163/* REG_DMA_BLEN_CTRL */ 164#define RX_THR_EN BIT(9) /* RX FIFO threshold arbitration */ 165#define RXFIFO_HTHR_MASK 0x1c0 166#define RXFIFO_LTHR_MASK 0x38 167#define INCR16_EN BIT(2) /* AHB bus INCR16 burst command */ 168#define INCR8_EN BIT(1) /* AHB bus INCR8 burst command */ 169#define INCR4_EN BIT(0) /* AHB bus INCR4 burst command */ 170 171/* REG_MAC_CTRL */ 172#define RX_BROADPKT BIT(17) /* receive broadcast packets */ 173#define RX_MULTIPKT BIT(16) /* receive all multicast packets */ 174#define FULLDUP BIT(15) /* full duplex */ 175#define CRC_APD BIT(14) /* append CRC to transmitted packet */ 176#define RCV_ALL BIT(12) /* ignore incoming packet destination */ 177#define RX_FTL BIT(11) /* accept packets larger than 1518 B */ 178#define RX_RUNT BIT(10) /* accept packets smaller than 64 B */ 179#define HT_MULTI_EN BIT(9) /* accept on hash and mcast pass */ 180#define RCV_EN BIT(8) /* receiver enable */ 181#define ENRX_IN_HALFTX BIT(6) /* enable receive in half duplex mode */ 182#define XMT_EN BIT(5) /* transmit enable */ 183#define CRC_DIS BIT(4) /* disable CRC check when receiving */ 184#define LOOP_EN BIT(3) /* internal loop-back */ 185#define SW_RST BIT(2) /* software reset, last 64 AHB clocks */ 186#define RDMA_EN BIT(1) /* enable receive DMA chan */ 187#define XDMA_EN BIT(0) /* enable transmit DMA chan */ 188 189/* REG_MAC_STATUS */ 190#define COL_EXCEED BIT(11) /* more than 16 collisions */ 191#define LATE_COL BIT(10) /* transmit late collision detected */ 192#define XPKT_LOST BIT(9) /* transmit to ethernet lost */ 193#define XPKT_OK BIT(8) /* transmit to ethernet success */ 194#define RUNT_MAC_STS BIT(7) /* receive runt detected */ 195#define FTL_MAC_STS BIT(6) /* receive frame too long detected */ 196#define CRC_ERR_MAC_STS BIT(5) 197#define RPKT_LOST BIT(4) /* RX FIFO full, receive failed */ 198#define RPKT_SAVE BIT(3) /* RX FIFO receive success */ 199#define COL BIT(2) /* collision, incoming packet dropped */ 200#define MCPU_BROADCAST BIT(1) 201#define MCPU_MULTICAST BIT(0) 202 203/* REG_PHY_CTRL */ 204#define MIIWR BIT(27) /* init write sequence (auto cleared)*/ 205#define MIIRD BIT(26) 206#define REGAD_MASK 0x3e00000 207#define PHYAD_MASK 0x1f0000 208#define MIIRDATA_MASK 0xffff 209 210/* REG_PHY_WRITE_DATA */ 211#define MIIWDATA_MASK 0xffff 212 213/* REG_FLOW_CTRL */ 214#define PAUSE_TIME_MASK 0xffff0000 215#define FC_HIGH_MASK 0xf000 216#define FC_LOW_MASK 0xf00 217#define RX_PAUSE BIT(4) /* receive pause frame */ 218#define TX_PAUSED BIT(3) /* transmit pause due to receive */ 219#define FCTHR_EN BIT(2) /* enable threshold mode. */ 220#define TX_PAUSE BIT(1) /* transmit pause frame */ 221#define FC_EN BIT(0) /* flow control mode enable */ 222 223/* REG_BACK_PRESSURE */ 224#define BACKP_LOW_MASK 0xf00 225#define BACKP_JAM_LEN_MASK 0xf0 226#define BACKP_MODE BIT(1) /* address mode */ 227#define BACKP_ENABLE BIT(0) 228 229/* REG_TEST_SEED */ 230#define TEST_SEED_MASK 0x3fff 231 232/* REG_DMA_FIFO_STATE */ 233#define TX_DMA_REQUEST BIT(31) 234#define RX_DMA_REQUEST BIT(30) 235#define TX_DMA_GRANT BIT(29) 236#define RX_DMA_GRANT BIT(28) 237#define TX_FIFO_EMPTY BIT(27) 238#define RX_FIFO_EMPTY BIT(26) 239#define TX_DMA2_SM_MASK 0x7000 240#define TX_DMA1_SM_MASK 0xf00 241#define RX_DMA2_SM_MASK 0x70 242#define RX_DMA1_SM_MASK 0xF 243 244/* REG_TEST_MODE */ 245#define SINGLE_PKT BIT(26) /* single packet mode */ 246#define PTIMER_TEST BIT(25) /* automatic polling timer test mode */ 247#define ITIMER_TEST BIT(24) /* interrupt timer test mode */ 248#define TEST_SEED_SELECT BIT(22) 249#define SEED_SELECT BIT(21) 250#define TEST_MODE BIT(20) 251#define TEST_TIME_MASK 0xffc00 252#define TEST_EXCEL_MASK 0x3e0 253 254/* REG_TX_COL_COUNTER */ 255#define TX_MCOL_MASK 0xffff0000 256#define TX_MCOL_SHIFT_BIT 16 257#define TX_SCOL_MASK 0xffff 258#define TX_SCOL_SHIFT_BIT 0 259 260/* REG_RPF_AEP_COUNTER */ 261#define RPF_MASK 0xffff0000 262#define RPF_SHIFT_BIT 16 263#define AEP_MASK 0xffff 264#define AEP_SHIFT_BIT 0 265 266/* REG_XM_PG_COUNTER */ 267#define XM_MASK 0xffff0000 268#define XM_SHIFT_BIT 16 269#define PG_MASK 0xffff 270#define PG_SHIFT_BIT 0 271 272/* REG_RUNT_TLC_COUNTER */ 273#define RUNT_CNT_MASK 0xffff0000 274#define RUNT_CNT_SHIFT_BIT 16 275#define TLCC_MASK 0xffff 276#define TLCC_SHIFT_BIT 0 277 278/* REG_CRC_FTL_COUNTER */ 279#define CRCER_CNT_MASK 0xffff0000 280#define CRCER_CNT_SHIFT_BIT 16 281#define FTL_CNT_MASK 0xffff 282#define FTL_CNT_SHIFT_BIT 0 283 284/* REG_RLC_RCC_COUNTER */ 285#define RLC_MASK 0xffff0000 286#define RLC_SHIFT_BIT 16 287#define RCC_MASK 0xffff 288#define RCC_SHIFT_BIT 0 289 290/* REG_PHY_STATUS */ 291#define AN_COMPLETE 0x20 292#define LINK_STATUS 0x4 293 294struct moxart_mac_priv_t { 295 struct platform_device *pdev; 296 void __iomem *base; 297 unsigned int reg_maccr; 298 unsigned int reg_imr; 299 struct napi_struct napi; 300 struct net_device *ndev; 301 302 dma_addr_t rx_base; 303 dma_addr_t rx_mapping[RX_DESC_NUM]; 304 void *rx_desc_base; 305 unsigned char *rx_buf_base; 306 unsigned char *rx_buf[RX_DESC_NUM]; 307 unsigned int rx_head; 308 unsigned int rx_buf_size; 309 310 dma_addr_t tx_base; 311 dma_addr_t tx_mapping[TX_DESC_NUM]; 312 void *tx_desc_base; 313 unsigned char *tx_buf_base; 314 unsigned char *tx_buf[RX_DESC_NUM]; 315 unsigned int tx_head; 316 unsigned int tx_buf_size; 317 318 spinlock_t txlock; 319 unsigned int tx_len[TX_DESC_NUM]; 320 struct sk_buff *tx_skb[TX_DESC_NUM]; 321 unsigned int tx_tail; 322}; 323 324#if TX_BUF_SIZE >= TX_BUF_SIZE_MAX 325#error MOXA ART Ethernet device driver TX buffer is too large! 326#endif 327#if RX_BUF_SIZE >= RX_BUF_SIZE_MAX 328#error MOXA ART Ethernet device driver RX buffer is too large! 329#endif 330 331#endif 332