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23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/dmapool.h>
26#include <linux/etherdevice.h>
27#include <linux/io.h>
28#include <linux/kernel.h>
29#include <linux/net_tstamp.h>
30#include <linux/of.h>
31#include <linux/of_mdio.h>
32#include <linux/phy.h>
33#include <linux/platform_data/eth_ixp4xx.h>
34#include <linux/platform_device.h>
35#include <linux/ptp_classify.h>
36#include <linux/slab.h>
37#include <linux/module.h>
38#include <linux/soc/ixp4xx/npe.h>
39#include <linux/soc/ixp4xx/qmgr.h>
40#include <linux/soc/ixp4xx/cpu.h>
41
42#include "ixp46x_ts.h"
43
44#define DEBUG_DESC 0
45#define DEBUG_RX 0
46#define DEBUG_TX 0
47#define DEBUG_PKT_BYTES 0
48#define DEBUG_MDIO 0
49#define DEBUG_CLOSE 0
50
51#define DRV_NAME "ixp4xx_eth"
52
53#define MAX_NPES 3
54
55#define RX_DESCS 64
56#define TX_DESCS 16
57#define TXDONE_QUEUE_LEN 64
58
59#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
60#define REGS_SIZE 0x1000
61#define MAX_MRU 1536
62#define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
63
64#define NAPI_WEIGHT 16
65#define MDIO_INTERVAL (3 * HZ)
66#define MAX_MDIO_RETRIES 100
67#define MAX_CLOSE_WAIT 1000
68
69#define NPE_ID(port_id) ((port_id) >> 4)
70#define PHYSICAL_ID(port_id) ((NPE_ID(port_id) + 2) % 3)
71#define TX_QUEUE(port_id) (NPE_ID(port_id) + 23)
72#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
73#define TXDONE_QUEUE 31
74
75#define PTP_SLAVE_MODE 1
76#define PTP_MASTER_MODE 2
77#define PORT2CHANNEL(p) NPE_ID(p->id)
78
79
80#define TX_CNTRL0_TX_EN 0x01
81#define TX_CNTRL0_HALFDUPLEX 0x02
82#define TX_CNTRL0_RETRY 0x04
83#define TX_CNTRL0_PAD_EN 0x08
84#define TX_CNTRL0_APPEND_FCS 0x10
85#define TX_CNTRL0_2DEFER 0x20
86#define TX_CNTRL0_RMII 0x40
87#define TX_CNTRL1_RETRIES 0x0F
88
89
90#define RX_CNTRL0_RX_EN 0x01
91#define RX_CNTRL0_PADSTRIP_EN 0x02
92#define RX_CNTRL0_SEND_FCS 0x04
93#define RX_CNTRL0_PAUSE_EN 0x08
94#define RX_CNTRL0_LOOP_EN 0x10
95#define RX_CNTRL0_ADDR_FLTR_EN 0x20
96#define RX_CNTRL0_RX_RUNT_EN 0x40
97#define RX_CNTRL0_BCAST_DIS 0x80
98#define RX_CNTRL1_DEFER_EN 0x01
99
100
101#define CORE_RESET 0x01
102#define CORE_RX_FIFO_FLUSH 0x02
103#define CORE_TX_FIFO_FLUSH 0x04
104#define CORE_SEND_JAM 0x08
105#define CORE_MDC_EN 0x10
106
107#define DEFAULT_TX_CNTRL0 (TX_CNTRL0_TX_EN | TX_CNTRL0_RETRY | \
108 TX_CNTRL0_PAD_EN | TX_CNTRL0_APPEND_FCS | \
109 TX_CNTRL0_2DEFER)
110#define DEFAULT_RX_CNTRL0 RX_CNTRL0_RX_EN
111#define DEFAULT_CORE_CNTRL CORE_MDC_EN
112
113
114
115#define NPE_GETSTATUS 0x00
116#define NPE_EDB_SETPORTADDRESS 0x01
117#define NPE_EDB_GETMACADDRESSDATABASE 0x02
118#define NPE_EDB_SETMACADDRESSSDATABASE 0x03
119#define NPE_GETSTATS 0x04
120#define NPE_RESETSTATS 0x05
121#define NPE_SETMAXFRAMELENGTHS 0x06
122#define NPE_VLAN_SETRXTAGMODE 0x07
123#define NPE_VLAN_SETDEFAULTRXVID 0x08
124#define NPE_VLAN_SETPORTVLANTABLEENTRY 0x09
125#define NPE_VLAN_SETPORTVLANTABLERANGE 0x0A
126#define NPE_VLAN_SETRXQOSENTRY 0x0B
127#define NPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C
128#define NPE_STP_SETBLOCKINGSTATE 0x0D
129#define NPE_FW_SETFIREWALLMODE 0x0E
130#define NPE_PC_SETFRAMECONTROLDURATIONID 0x0F
131#define NPE_PC_SETAPMACTABLE 0x11
132#define NPE_SETLOOPBACK_MODE 0x12
133#define NPE_PC_SETBSSIDTABLE 0x13
134#define NPE_ADDRESS_FILTER_CONFIG 0x14
135#define NPE_APPENDFCSCONFIG 0x15
136#define NPE_NOTIFY_MAC_RECOVERY_DONE 0x16
137#define NPE_MAC_RECOVERY_START 0x17
138
139
140#ifdef __ARMEB__
141typedef struct sk_buff buffer_t;
142#define free_buffer dev_kfree_skb
143#define free_buffer_irq dev_consume_skb_irq
144#else
145typedef void buffer_t;
146#define free_buffer kfree
147#define free_buffer_irq kfree
148#endif
149
150struct eth_regs {
151 u32 tx_control[2], __res1[2];
152 u32 rx_control[2], __res2[2];
153 u32 random_seed, __res3[3];
154 u32 partial_empty_threshold, __res4;
155 u32 partial_full_threshold, __res5;
156 u32 tx_start_bytes, __res6[3];
157 u32 tx_deferral, rx_deferral, __res7[2];
158 u32 tx_2part_deferral[2], __res8[2];
159 u32 slot_time, __res9[3];
160 u32 mdio_command[4];
161 u32 mdio_status[4];
162 u32 mcast_mask[6], __res10[2];
163 u32 mcast_addr[6], __res11[2];
164 u32 int_clock_threshold, __res12[3];
165 u32 hw_addr[6], __res13[61];
166 u32 core_control;
167};
168
169struct port {
170 struct eth_regs __iomem *regs;
171 struct ixp46x_ts_regs __iomem *timesync_regs;
172 int phc_index;
173 struct npe *npe;
174 struct net_device *netdev;
175 struct napi_struct napi;
176 struct eth_plat_info *plat;
177 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
178 struct desc *desc_tab;
179 dma_addr_t desc_tab_phys;
180 int id;
181 int speed, duplex;
182 u8 firmware[4];
183 int hwts_tx_en;
184 int hwts_rx_en;
185};
186
187
188struct msg {
189#ifdef __ARMEB__
190 u8 cmd, eth_id, byte2, byte3;
191 u8 byte4, byte5, byte6, byte7;
192#else
193 u8 byte3, byte2, eth_id, cmd;
194 u8 byte7, byte6, byte5, byte4;
195#endif
196};
197
198
199struct desc {
200 u32 next;
201
202#ifdef __ARMEB__
203 u16 buf_len;
204 u16 pkt_len;
205 u32 data;
206 u8 dest_id;
207 u8 src_id;
208 u16 flags;
209 u8 qos;
210 u8 padlen;
211 u16 vlan_tci;
212#else
213 u16 pkt_len;
214 u16 buf_len;
215 u32 data;
216 u16 flags;
217 u8 src_id;
218 u8 dest_id;
219 u16 vlan_tci;
220 u8 padlen;
221 u8 qos;
222#endif
223
224#ifdef __ARMEB__
225 u8 dst_mac_0, dst_mac_1, dst_mac_2, dst_mac_3;
226 u8 dst_mac_4, dst_mac_5, src_mac_0, src_mac_1;
227 u8 src_mac_2, src_mac_3, src_mac_4, src_mac_5;
228#else
229 u8 dst_mac_3, dst_mac_2, dst_mac_1, dst_mac_0;
230 u8 src_mac_1, src_mac_0, dst_mac_5, dst_mac_4;
231 u8 src_mac_5, src_mac_4, src_mac_3, src_mac_2;
232#endif
233};
234
235
236#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
237 (n) * sizeof(struct desc))
238#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
239
240#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
241 ((n) + RX_DESCS) * sizeof(struct desc))
242#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
243
244#ifndef __ARMEB__
245static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
246{
247 int i;
248 for (i = 0; i < cnt; i++)
249 dest[i] = swab32(src[i]);
250}
251#endif
252
253static DEFINE_SPINLOCK(mdio_lock);
254static struct eth_regs __iomem *mdio_regs;
255static struct mii_bus *mdio_bus;
256static struct device_node *mdio_bus_np;
257static int ports_open;
258static struct port *npe_port_tab[MAX_NPES];
259static struct dma_pool *dma_pool;
260
261static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
262{
263 u8 *data = skb->data;
264 unsigned int offset;
265 u16 *hi, *id;
266 u32 lo;
267
268 if (ptp_classify_raw(skb) != PTP_CLASS_V1_IPV4)
269 return 0;
270
271 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
272
273 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
274 return 0;
275
276 hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
277 id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
278
279 memcpy(&lo, &hi[1], sizeof(lo));
280
281 return (uid_hi == ntohs(*hi) &&
282 uid_lo == ntohl(lo) &&
283 seqid == ntohs(*id));
284}
285
286static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)
287{
288 struct skb_shared_hwtstamps *shhwtstamps;
289 struct ixp46x_ts_regs *regs;
290 u64 ns;
291 u32 ch, hi, lo, val;
292 u16 uid, seq;
293
294 if (!port->hwts_rx_en)
295 return;
296
297 ch = PORT2CHANNEL(port);
298
299 regs = port->timesync_regs;
300
301 val = __raw_readl(®s->channel[ch].ch_event);
302
303 if (!(val & RX_SNAPSHOT_LOCKED))
304 return;
305
306 lo = __raw_readl(®s->channel[ch].src_uuid_lo);
307 hi = __raw_readl(®s->channel[ch].src_uuid_hi);
308
309 uid = hi & 0xffff;
310 seq = (hi >> 16) & 0xffff;
311
312 if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
313 goto out;
314
315 lo = __raw_readl(®s->channel[ch].rx_snap_lo);
316 hi = __raw_readl(®s->channel[ch].rx_snap_hi);
317 ns = ((u64) hi) << 32;
318 ns |= lo;
319 ns <<= TICKS_NS_SHIFT;
320
321 shhwtstamps = skb_hwtstamps(skb);
322 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
323 shhwtstamps->hwtstamp = ns_to_ktime(ns);
324out:
325 __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
326}
327
328static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)
329{
330 struct skb_shared_hwtstamps shhwtstamps;
331 struct ixp46x_ts_regs *regs;
332 struct skb_shared_info *shtx;
333 u64 ns;
334 u32 ch, cnt, hi, lo, val;
335
336 shtx = skb_shinfo(skb);
337 if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
338 shtx->tx_flags |= SKBTX_IN_PROGRESS;
339 else
340 return;
341
342 ch = PORT2CHANNEL(port);
343
344 regs = port->timesync_regs;
345
346
347
348
349
350 for (cnt = 0; cnt < 100; cnt++) {
351 val = __raw_readl(®s->channel[ch].ch_event);
352 if (val & TX_SNAPSHOT_LOCKED)
353 break;
354 udelay(1);
355 }
356 if (!(val & TX_SNAPSHOT_LOCKED)) {
357 shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
358 return;
359 }
360
361 lo = __raw_readl(®s->channel[ch].tx_snap_lo);
362 hi = __raw_readl(®s->channel[ch].tx_snap_hi);
363 ns = ((u64) hi) << 32;
364 ns |= lo;
365 ns <<= TICKS_NS_SHIFT;
366
367 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
368 shhwtstamps.hwtstamp = ns_to_ktime(ns);
369 skb_tstamp_tx(skb, &shhwtstamps);
370
371 __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
372}
373
374static int hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
375{
376 struct hwtstamp_config cfg;
377 struct ixp46x_ts_regs *regs;
378 struct port *port = netdev_priv(netdev);
379 int ret;
380 int ch;
381
382 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
383 return -EFAULT;
384
385 if (cfg.flags)
386 return -EINVAL;
387
388 ret = ixp46x_ptp_find(&port->timesync_regs, &port->phc_index);
389 if (ret)
390 return ret;
391
392 ch = PORT2CHANNEL(port);
393 regs = port->timesync_regs;
394
395 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
396 return -ERANGE;
397
398 switch (cfg.rx_filter) {
399 case HWTSTAMP_FILTER_NONE:
400 port->hwts_rx_en = 0;
401 break;
402 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
403 port->hwts_rx_en = PTP_SLAVE_MODE;
404 __raw_writel(0, ®s->channel[ch].ch_control);
405 break;
406 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
407 port->hwts_rx_en = PTP_MASTER_MODE;
408 __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control);
409 break;
410 default:
411 return -ERANGE;
412 }
413
414 port->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
415
416
417 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
418 ®s->channel[ch].ch_event);
419
420 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
421}
422
423static int hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
424{
425 struct hwtstamp_config cfg;
426 struct port *port = netdev_priv(netdev);
427
428 cfg.flags = 0;
429 cfg.tx_type = port->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
430
431 switch (port->hwts_rx_en) {
432 case 0:
433 cfg.rx_filter = HWTSTAMP_FILTER_NONE;
434 break;
435 case PTP_SLAVE_MODE:
436 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
437 break;
438 case PTP_MASTER_MODE:
439 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
440 break;
441 default:
442 WARN_ON_ONCE(1);
443 return -ERANGE;
444 }
445
446 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
447}
448
449static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
450 int write, u16 cmd)
451{
452 int cycles = 0;
453
454 if (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80) {
455 printk(KERN_ERR "%s: MII not ready to transmit\n", bus->name);
456 return -1;
457 }
458
459 if (write) {
460 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);
461 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);
462 }
463 __raw_writel(((phy_id << 5) | location) & 0xFF,
464 &mdio_regs->mdio_command[2]);
465 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 ,
466 &mdio_regs->mdio_command[3]);
467
468 while ((cycles < MAX_MDIO_RETRIES) &&
469 (__raw_readl(&mdio_regs->mdio_command[3]) & 0x80)) {
470 udelay(1);
471 cycles++;
472 }
473
474 if (cycles == MAX_MDIO_RETRIES) {
475 printk(KERN_ERR "%s #%i: MII write failed\n", bus->name,
476 phy_id);
477 return -1;
478 }
479
480#if DEBUG_MDIO
481 printk(KERN_DEBUG "%s #%i: mdio_%s() took %i cycles\n", bus->name,
482 phy_id, write ? "write" : "read", cycles);
483#endif
484
485 if (write)
486 return 0;
487
488 if (__raw_readl(&mdio_regs->mdio_status[3]) & 0x80) {
489#if DEBUG_MDIO
490 printk(KERN_DEBUG "%s #%i: MII read failed\n", bus->name,
491 phy_id);
492#endif
493 return 0xFFFF;
494 }
495
496 return (__raw_readl(&mdio_regs->mdio_status[0]) & 0xFF) |
497 ((__raw_readl(&mdio_regs->mdio_status[1]) & 0xFF) << 8);
498}
499
500static int ixp4xx_mdio_read(struct mii_bus *bus, int phy_id, int location)
501{
502 unsigned long flags;
503 int ret;
504
505 spin_lock_irqsave(&mdio_lock, flags);
506 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 0, 0);
507 spin_unlock_irqrestore(&mdio_lock, flags);
508#if DEBUG_MDIO
509 printk(KERN_DEBUG "%s #%i: MII read [%i] -> 0x%X\n", bus->name,
510 phy_id, location, ret);
511#endif
512 return ret;
513}
514
515static int ixp4xx_mdio_write(struct mii_bus *bus, int phy_id, int location,
516 u16 val)
517{
518 unsigned long flags;
519 int ret;
520
521 spin_lock_irqsave(&mdio_lock, flags);
522 ret = ixp4xx_mdio_cmd(bus, phy_id, location, 1, val);
523 spin_unlock_irqrestore(&mdio_lock, flags);
524#if DEBUG_MDIO
525 printk(KERN_DEBUG "%s #%i: MII write [%i] <- 0x%X, err = %i\n",
526 bus->name, phy_id, location, val, ret);
527#endif
528 return ret;
529}
530
531static int ixp4xx_mdio_register(struct eth_regs __iomem *regs)
532{
533 int err;
534
535 if (!(mdio_bus = mdiobus_alloc()))
536 return -ENOMEM;
537
538 mdio_regs = regs;
539 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);
540 mdio_bus->name = "IXP4xx MII Bus";
541 mdio_bus->read = &ixp4xx_mdio_read;
542 mdio_bus->write = &ixp4xx_mdio_write;
543 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "ixp4xx-eth-0");
544
545 err = of_mdiobus_register(mdio_bus, mdio_bus_np);
546 if (err)
547 mdiobus_free(mdio_bus);
548 return err;
549}
550
551static void ixp4xx_mdio_remove(void)
552{
553 mdiobus_unregister(mdio_bus);
554 mdiobus_free(mdio_bus);
555}
556
557
558static void ixp4xx_adjust_link(struct net_device *dev)
559{
560 struct port *port = netdev_priv(dev);
561 struct phy_device *phydev = dev->phydev;
562
563 if (!phydev->link) {
564 if (port->speed) {
565 port->speed = 0;
566 printk(KERN_INFO "%s: link down\n", dev->name);
567 }
568 return;
569 }
570
571 if (port->speed == phydev->speed && port->duplex == phydev->duplex)
572 return;
573
574 port->speed = phydev->speed;
575 port->duplex = phydev->duplex;
576
577 if (port->duplex)
578 __raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,
579 &port->regs->tx_control[0]);
580 else
581 __raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,
582 &port->regs->tx_control[0]);
583
584 netdev_info(dev, "%s: link up, speed %u Mb/s, %s duplex\n",
585 dev->name, port->speed, port->duplex ? "full" : "half");
586}
587
588
589static inline void debug_pkt(struct net_device *dev, const char *func,
590 u8 *data, int len)
591{
592#if DEBUG_PKT_BYTES
593 int i;
594
595 netdev_debug(dev, "%s(%i) ", func, len);
596 for (i = 0; i < len; i++) {
597 if (i >= DEBUG_PKT_BYTES)
598 break;
599 printk("%s%02X",
600 ((i == 6) || (i == 12) || (i >= 14)) ? " " : "",
601 data[i]);
602 }
603 printk("\n");
604#endif
605}
606
607
608static inline void debug_desc(u32 phys, struct desc *desc)
609{
610#if DEBUG_DESC
611 printk(KERN_DEBUG "%X: %X %3X %3X %08X %2X < %2X %4X %X"
612 " %X %X %02X%02X%02X%02X%02X%02X < %02X%02X%02X%02X%02X%02X\n",
613 phys, desc->next, desc->buf_len, desc->pkt_len,
614 desc->data, desc->dest_id, desc->src_id, desc->flags,
615 desc->qos, desc->padlen, desc->vlan_tci,
616 desc->dst_mac_0, desc->dst_mac_1, desc->dst_mac_2,
617 desc->dst_mac_3, desc->dst_mac_4, desc->dst_mac_5,
618 desc->src_mac_0, desc->src_mac_1, desc->src_mac_2,
619 desc->src_mac_3, desc->src_mac_4, desc->src_mac_5);
620#endif
621}
622
623static inline int queue_get_desc(unsigned int queue, struct port *port,
624 int is_tx)
625{
626 u32 phys, tab_phys, n_desc;
627 struct desc *tab;
628
629 if (!(phys = qmgr_get_entry(queue)))
630 return -1;
631
632 phys &= ~0x1F;
633 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
634 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
635 n_desc = (phys - tab_phys) / sizeof(struct desc);
636 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
637 debug_desc(phys, &tab[n_desc]);
638 BUG_ON(tab[n_desc].next);
639 return n_desc;
640}
641
642static inline void queue_put_desc(unsigned int queue, u32 phys,
643 struct desc *desc)
644{
645 debug_desc(phys, desc);
646 BUG_ON(phys & 0x1F);
647 qmgr_put_entry(queue, phys);
648
649
650}
651
652
653static inline void dma_unmap_tx(struct port *port, struct desc *desc)
654{
655#ifdef __ARMEB__
656 dma_unmap_single(&port->netdev->dev, desc->data,
657 desc->buf_len, DMA_TO_DEVICE);
658#else
659 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
660 ALIGN((desc->data & 3) + desc->buf_len, 4),
661 DMA_TO_DEVICE);
662#endif
663}
664
665
666static void eth_rx_irq(void *pdev)
667{
668 struct net_device *dev = pdev;
669 struct port *port = netdev_priv(dev);
670
671#if DEBUG_RX
672 printk(KERN_DEBUG "%s: eth_rx_irq\n", dev->name);
673#endif
674 qmgr_disable_irq(port->plat->rxq);
675 napi_schedule(&port->napi);
676}
677
678static int eth_poll(struct napi_struct *napi, int budget)
679{
680 struct port *port = container_of(napi, struct port, napi);
681 struct net_device *dev = port->netdev;
682 unsigned int rxq = port->plat->rxq, rxfreeq = RXFREE_QUEUE(port->id);
683 int received = 0;
684
685#if DEBUG_RX
686 netdev_debug(dev, "eth_poll\n");
687#endif
688
689 while (received < budget) {
690 struct sk_buff *skb;
691 struct desc *desc;
692 int n;
693#ifdef __ARMEB__
694 struct sk_buff *temp;
695 u32 phys;
696#endif
697
698 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
699#if DEBUG_RX
700 netdev_debug(dev, "eth_poll napi_complete\n");
701#endif
702 napi_complete(napi);
703 qmgr_enable_irq(rxq);
704 if (!qmgr_stat_below_low_watermark(rxq) &&
705 napi_reschedule(napi)) {
706#if DEBUG_RX
707 netdev_debug(dev, "eth_poll napi_reschedule succeeded\n");
708#endif
709 qmgr_disable_irq(rxq);
710 continue;
711 }
712#if DEBUG_RX
713 netdev_debug(dev, "eth_poll all done\n");
714#endif
715 return received;
716 }
717
718 desc = rx_desc_ptr(port, n);
719
720#ifdef __ARMEB__
721 if ((skb = netdev_alloc_skb(dev, RX_BUFF_SIZE))) {
722 phys = dma_map_single(&dev->dev, skb->data,
723 RX_BUFF_SIZE, DMA_FROM_DEVICE);
724 if (dma_mapping_error(&dev->dev, phys)) {
725 dev_kfree_skb(skb);
726 skb = NULL;
727 }
728 }
729#else
730 skb = netdev_alloc_skb(dev,
731 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4));
732#endif
733
734 if (!skb) {
735 dev->stats.rx_dropped++;
736
737 desc->buf_len = MAX_MRU;
738 desc->pkt_len = 0;
739 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
740 continue;
741 }
742
743
744#ifdef __ARMEB__
745 temp = skb;
746 skb = port->rx_buff_tab[n];
747 dma_unmap_single(&dev->dev, desc->data - NET_IP_ALIGN,
748 RX_BUFF_SIZE, DMA_FROM_DEVICE);
749#else
750 dma_sync_single_for_cpu(&dev->dev, desc->data - NET_IP_ALIGN,
751 RX_BUFF_SIZE, DMA_FROM_DEVICE);
752 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
753 ALIGN(NET_IP_ALIGN + desc->pkt_len, 4) / 4);
754#endif
755 skb_reserve(skb, NET_IP_ALIGN);
756 skb_put(skb, desc->pkt_len);
757
758 debug_pkt(dev, "eth_poll", skb->data, skb->len);
759
760 ixp_rx_timestamp(port, skb);
761 skb->protocol = eth_type_trans(skb, dev);
762 dev->stats.rx_packets++;
763 dev->stats.rx_bytes += skb->len;
764 netif_receive_skb(skb);
765
766
767#ifdef __ARMEB__
768 port->rx_buff_tab[n] = temp;
769 desc->data = phys + NET_IP_ALIGN;
770#endif
771 desc->buf_len = MAX_MRU;
772 desc->pkt_len = 0;
773 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
774 received++;
775 }
776
777#if DEBUG_RX
778 netdev_debug(dev, "eth_poll(): end, not all work done\n");
779#endif
780 return received;
781}
782
783
784static void eth_txdone_irq(void *unused)
785{
786 u32 phys;
787
788#if DEBUG_TX
789 printk(KERN_DEBUG DRV_NAME ": eth_txdone_irq\n");
790#endif
791 while ((phys = qmgr_get_entry(TXDONE_QUEUE)) != 0) {
792 u32 npe_id, n_desc;
793 struct port *port;
794 struct desc *desc;
795 int start;
796
797 npe_id = phys & 3;
798 BUG_ON(npe_id >= MAX_NPES);
799 port = npe_port_tab[npe_id];
800 BUG_ON(!port);
801 phys &= ~0x1F;
802 n_desc = (phys - tx_desc_phys(port, 0)) / sizeof(struct desc);
803 BUG_ON(n_desc >= TX_DESCS);
804 desc = tx_desc_ptr(port, n_desc);
805 debug_desc(phys, desc);
806
807 if (port->tx_buff_tab[n_desc]) {
808 port->netdev->stats.tx_packets++;
809 port->netdev->stats.tx_bytes += desc->pkt_len;
810
811 dma_unmap_tx(port, desc);
812#if DEBUG_TX
813 printk(KERN_DEBUG "%s: eth_txdone_irq free %p\n",
814 port->netdev->name, port->tx_buff_tab[n_desc]);
815#endif
816 free_buffer_irq(port->tx_buff_tab[n_desc]);
817 port->tx_buff_tab[n_desc] = NULL;
818 }
819
820 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
821 queue_put_desc(port->plat->txreadyq, phys, desc);
822 if (start) {
823#if DEBUG_TX
824 printk(KERN_DEBUG "%s: eth_txdone_irq xmit ready\n",
825 port->netdev->name);
826#endif
827 netif_wake_queue(port->netdev);
828 }
829 }
830}
831
832static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
833{
834 struct port *port = netdev_priv(dev);
835 unsigned int txreadyq = port->plat->txreadyq;
836 int len, offset, bytes, n;
837 void *mem;
838 u32 phys;
839 struct desc *desc;
840
841#if DEBUG_TX
842 netdev_debug(dev, "eth_xmit\n");
843#endif
844
845 if (unlikely(skb->len > MAX_MRU)) {
846 dev_kfree_skb(skb);
847 dev->stats.tx_errors++;
848 return NETDEV_TX_OK;
849 }
850
851 debug_pkt(dev, "eth_xmit", skb->data, skb->len);
852
853 len = skb->len;
854#ifdef __ARMEB__
855 offset = 0;
856 bytes = len;
857 mem = skb->data;
858#else
859 offset = (uintptr_t)skb->data & 3;
860 bytes = ALIGN(offset + len, 4);
861 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
862 dev_kfree_skb(skb);
863 dev->stats.tx_dropped++;
864 return NETDEV_TX_OK;
865 }
866 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
867#endif
868
869 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
870 if (dma_mapping_error(&dev->dev, phys)) {
871 dev_kfree_skb(skb);
872#ifndef __ARMEB__
873 kfree(mem);
874#endif
875 dev->stats.tx_dropped++;
876 return NETDEV_TX_OK;
877 }
878
879 n = queue_get_desc(txreadyq, port, 1);
880 BUG_ON(n < 0);
881 desc = tx_desc_ptr(port, n);
882
883#ifdef __ARMEB__
884 port->tx_buff_tab[n] = skb;
885#else
886 port->tx_buff_tab[n] = mem;
887#endif
888 desc->data = phys + offset;
889 desc->buf_len = desc->pkt_len = len;
890
891
892 wmb();
893 queue_put_desc(TX_QUEUE(port->id), tx_desc_phys(port, n), desc);
894
895 if (qmgr_stat_below_low_watermark(txreadyq)) {
896#if DEBUG_TX
897 netdev_debug(dev, "eth_xmit queue full\n");
898#endif
899 netif_stop_queue(dev);
900
901
902 if (!qmgr_stat_below_low_watermark(txreadyq)) {
903#if DEBUG_TX
904 netdev_debug(dev, "eth_xmit ready again\n");
905#endif
906 netif_wake_queue(dev);
907 }
908 }
909
910#if DEBUG_TX
911 netdev_debug(dev, "eth_xmit end\n");
912#endif
913
914 ixp_tx_timestamp(port, skb);
915 skb_tx_timestamp(skb);
916
917#ifndef __ARMEB__
918 dev_kfree_skb(skb);
919#endif
920 return NETDEV_TX_OK;
921}
922
923
924static void eth_set_mcast_list(struct net_device *dev)
925{
926 struct port *port = netdev_priv(dev);
927 struct netdev_hw_addr *ha;
928 u8 diffs[ETH_ALEN], *addr;
929 int i;
930 static const u8 allmulti[] = { 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 };
931
932 if ((dev->flags & IFF_ALLMULTI) && !(dev->flags & IFF_PROMISC)) {
933 for (i = 0; i < ETH_ALEN; i++) {
934 __raw_writel(allmulti[i], &port->regs->mcast_addr[i]);
935 __raw_writel(allmulti[i], &port->regs->mcast_mask[i]);
936 }
937 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
938 &port->regs->rx_control[0]);
939 return;
940 }
941
942 if ((dev->flags & IFF_PROMISC) || netdev_mc_empty(dev)) {
943 __raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,
944 &port->regs->rx_control[0]);
945 return;
946 }
947
948 eth_zero_addr(diffs);
949
950 addr = NULL;
951 netdev_for_each_mc_addr(ha, dev) {
952 if (!addr)
953 addr = ha->addr;
954 for (i = 0; i < ETH_ALEN; i++)
955 diffs[i] |= addr[i] ^ ha->addr[i];
956 }
957
958 for (i = 0; i < ETH_ALEN; i++) {
959 __raw_writel(addr[i], &port->regs->mcast_addr[i]);
960 __raw_writel(~diffs[i], &port->regs->mcast_mask[i]);
961 }
962
963 __raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,
964 &port->regs->rx_control[0]);
965}
966
967
968static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
969{
970 if (!netif_running(dev))
971 return -EINVAL;
972
973 if (cpu_is_ixp46x()) {
974 if (cmd == SIOCSHWTSTAMP)
975 return hwtstamp_set(dev, req);
976 if (cmd == SIOCGHWTSTAMP)
977 return hwtstamp_get(dev, req);
978 }
979
980 return phy_mii_ioctl(dev->phydev, req, cmd);
981}
982
983
984
985static void ixp4xx_get_drvinfo(struct net_device *dev,
986 struct ethtool_drvinfo *info)
987{
988 struct port *port = netdev_priv(dev);
989
990 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
991 snprintf(info->fw_version, sizeof(info->fw_version), "%u:%u:%u:%u",
992 port->firmware[0], port->firmware[1],
993 port->firmware[2], port->firmware[3]);
994 strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
995}
996
997static int ixp4xx_get_ts_info(struct net_device *dev,
998 struct ethtool_ts_info *info)
999{
1000 struct port *port = netdev_priv(dev);
1001
1002 if (port->phc_index < 0)
1003 ixp46x_ptp_find(&port->timesync_regs, &port->phc_index);
1004
1005 info->phc_index = port->phc_index;
1006
1007 if (info->phc_index < 0) {
1008 info->so_timestamping =
1009 SOF_TIMESTAMPING_TX_SOFTWARE |
1010 SOF_TIMESTAMPING_RX_SOFTWARE |
1011 SOF_TIMESTAMPING_SOFTWARE;
1012 return 0;
1013 }
1014 info->so_timestamping =
1015 SOF_TIMESTAMPING_TX_HARDWARE |
1016 SOF_TIMESTAMPING_RX_HARDWARE |
1017 SOF_TIMESTAMPING_RAW_HARDWARE;
1018 info->tx_types =
1019 (1 << HWTSTAMP_TX_OFF) |
1020 (1 << HWTSTAMP_TX_ON);
1021 info->rx_filters =
1022 (1 << HWTSTAMP_FILTER_NONE) |
1023 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1024 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ);
1025 return 0;
1026}
1027
1028static const struct ethtool_ops ixp4xx_ethtool_ops = {
1029 .get_drvinfo = ixp4xx_get_drvinfo,
1030 .nway_reset = phy_ethtool_nway_reset,
1031 .get_link = ethtool_op_get_link,
1032 .get_ts_info = ixp4xx_get_ts_info,
1033 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1034 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1035};
1036
1037
1038static int request_queues(struct port *port)
1039{
1040 int err;
1041
1042 err = qmgr_request_queue(RXFREE_QUEUE(port->id), RX_DESCS, 0, 0,
1043 "%s:RX-free", port->netdev->name);
1044 if (err)
1045 return err;
1046
1047 err = qmgr_request_queue(port->plat->rxq, RX_DESCS, 0, 0,
1048 "%s:RX", port->netdev->name);
1049 if (err)
1050 goto rel_rxfree;
1051
1052 err = qmgr_request_queue(TX_QUEUE(port->id), TX_DESCS, 0, 0,
1053 "%s:TX", port->netdev->name);
1054 if (err)
1055 goto rel_rx;
1056
1057 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
1058 "%s:TX-ready", port->netdev->name);
1059 if (err)
1060 goto rel_tx;
1061
1062
1063 if (!ports_open) {
1064 err = qmgr_request_queue(TXDONE_QUEUE, TXDONE_QUEUE_LEN, 0, 0,
1065 "%s:TX-done", DRV_NAME);
1066 if (err)
1067 goto rel_txready;
1068 }
1069 return 0;
1070
1071rel_txready:
1072 qmgr_release_queue(port->plat->txreadyq);
1073rel_tx:
1074 qmgr_release_queue(TX_QUEUE(port->id));
1075rel_rx:
1076 qmgr_release_queue(port->plat->rxq);
1077rel_rxfree:
1078 qmgr_release_queue(RXFREE_QUEUE(port->id));
1079 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
1080 port->netdev->name);
1081 return err;
1082}
1083
1084static void release_queues(struct port *port)
1085{
1086 qmgr_release_queue(RXFREE_QUEUE(port->id));
1087 qmgr_release_queue(port->plat->rxq);
1088 qmgr_release_queue(TX_QUEUE(port->id));
1089 qmgr_release_queue(port->plat->txreadyq);
1090
1091 if (!ports_open)
1092 qmgr_release_queue(TXDONE_QUEUE);
1093}
1094
1095static int init_queues(struct port *port)
1096{
1097 int i;
1098
1099 if (!ports_open) {
1100 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
1101 POOL_ALLOC_SIZE, 32, 0);
1102 if (!dma_pool)
1103 return -ENOMEM;
1104 }
1105
1106 port->desc_tab = dma_pool_zalloc(dma_pool, GFP_KERNEL, &port->desc_tab_phys);
1107 if (!port->desc_tab)
1108 return -ENOMEM;
1109 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab));
1110 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
1111
1112
1113 for (i = 0; i < RX_DESCS; i++) {
1114 struct desc *desc = rx_desc_ptr(port, i);
1115 buffer_t *buff;
1116 void *data;
1117#ifdef __ARMEB__
1118 if (!(buff = netdev_alloc_skb(port->netdev, RX_BUFF_SIZE)))
1119 return -ENOMEM;
1120 data = buff->data;
1121#else
1122 if (!(buff = kmalloc(RX_BUFF_SIZE, GFP_KERNEL)))
1123 return -ENOMEM;
1124 data = buff;
1125#endif
1126 desc->buf_len = MAX_MRU;
1127 desc->data = dma_map_single(&port->netdev->dev, data,
1128 RX_BUFF_SIZE, DMA_FROM_DEVICE);
1129 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1130 free_buffer(buff);
1131 return -EIO;
1132 }
1133 desc->data += NET_IP_ALIGN;
1134 port->rx_buff_tab[i] = buff;
1135 }
1136
1137 return 0;
1138}
1139
1140static void destroy_queues(struct port *port)
1141{
1142 int i;
1143
1144 if (port->desc_tab) {
1145 for (i = 0; i < RX_DESCS; i++) {
1146 struct desc *desc = rx_desc_ptr(port, i);
1147 buffer_t *buff = port->rx_buff_tab[i];
1148 if (buff) {
1149 dma_unmap_single(&port->netdev->dev,
1150 desc->data - NET_IP_ALIGN,
1151 RX_BUFF_SIZE, DMA_FROM_DEVICE);
1152 free_buffer(buff);
1153 }
1154 }
1155 for (i = 0; i < TX_DESCS; i++) {
1156 struct desc *desc = tx_desc_ptr(port, i);
1157 buffer_t *buff = port->tx_buff_tab[i];
1158 if (buff) {
1159 dma_unmap_tx(port, desc);
1160 free_buffer(buff);
1161 }
1162 }
1163 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1164 port->desc_tab = NULL;
1165 }
1166
1167 if (!ports_open && dma_pool) {
1168 dma_pool_destroy(dma_pool);
1169 dma_pool = NULL;
1170 }
1171}
1172
1173static int eth_open(struct net_device *dev)
1174{
1175 struct port *port = netdev_priv(dev);
1176 struct npe *npe = port->npe;
1177 struct msg msg;
1178 int i, err;
1179
1180 if (!npe_running(npe)) {
1181 err = npe_load_firmware(npe, npe_name(npe), &dev->dev);
1182 if (err)
1183 return err;
1184
1185 if (npe_recv_message(npe, &msg, "ETH_GET_STATUS")) {
1186 netdev_err(dev, "%s not responding\n", npe_name(npe));
1187 return -EIO;
1188 }
1189 port->firmware[0] = msg.byte4;
1190 port->firmware[1] = msg.byte5;
1191 port->firmware[2] = msg.byte6;
1192 port->firmware[3] = msg.byte7;
1193 }
1194
1195 memset(&msg, 0, sizeof(msg));
1196 msg.cmd = NPE_VLAN_SETRXQOSENTRY;
1197 msg.eth_id = port->id;
1198 msg.byte5 = port->plat->rxq | 0x80;
1199 msg.byte7 = port->plat->rxq << 4;
1200 for (i = 0; i < 8; i++) {
1201 msg.byte3 = i;
1202 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_RXQ"))
1203 return -EIO;
1204 }
1205
1206 msg.cmd = NPE_EDB_SETPORTADDRESS;
1207 msg.eth_id = PHYSICAL_ID(port->id);
1208 msg.byte2 = dev->dev_addr[0];
1209 msg.byte3 = dev->dev_addr[1];
1210 msg.byte4 = dev->dev_addr[2];
1211 msg.byte5 = dev->dev_addr[3];
1212 msg.byte6 = dev->dev_addr[4];
1213 msg.byte7 = dev->dev_addr[5];
1214 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_MAC"))
1215 return -EIO;
1216
1217 memset(&msg, 0, sizeof(msg));
1218 msg.cmd = NPE_FW_SETFIREWALLMODE;
1219 msg.eth_id = port->id;
1220 if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
1221 return -EIO;
1222
1223 if ((err = request_queues(port)) != 0)
1224 return err;
1225
1226 if ((err = init_queues(port)) != 0) {
1227 destroy_queues(port);
1228 release_queues(port);
1229 return err;
1230 }
1231
1232 port->speed = 0;
1233 phy_start(dev->phydev);
1234
1235 for (i = 0; i < ETH_ALEN; i++)
1236 __raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);
1237 __raw_writel(0x08, &port->regs->random_seed);
1238 __raw_writel(0x12, &port->regs->partial_empty_threshold);
1239 __raw_writel(0x30, &port->regs->partial_full_threshold);
1240 __raw_writel(0x08, &port->regs->tx_start_bytes);
1241 __raw_writel(0x15, &port->regs->tx_deferral);
1242 __raw_writel(0x08, &port->regs->tx_2part_deferral[0]);
1243 __raw_writel(0x07, &port->regs->tx_2part_deferral[1]);
1244 __raw_writel(0x80, &port->regs->slot_time);
1245 __raw_writel(0x01, &port->regs->int_clock_threshold);
1246
1247
1248 for (i = 0; i < TX_DESCS; i++)
1249 queue_put_desc(port->plat->txreadyq,
1250 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1251
1252 for (i = 0; i < RX_DESCS; i++)
1253 queue_put_desc(RXFREE_QUEUE(port->id),
1254 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1255
1256 __raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);
1257 __raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);
1258 __raw_writel(0, &port->regs->rx_control[1]);
1259 __raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);
1260
1261 napi_enable(&port->napi);
1262 eth_set_mcast_list(dev);
1263 netif_start_queue(dev);
1264
1265 qmgr_set_irq(port->plat->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1266 eth_rx_irq, dev);
1267 if (!ports_open) {
1268 qmgr_set_irq(TXDONE_QUEUE, QUEUE_IRQ_SRC_NOT_EMPTY,
1269 eth_txdone_irq, NULL);
1270 qmgr_enable_irq(TXDONE_QUEUE);
1271 }
1272 ports_open++;
1273
1274 napi_schedule(&port->napi);
1275 return 0;
1276}
1277
1278static int eth_close(struct net_device *dev)
1279{
1280 struct port *port = netdev_priv(dev);
1281 struct msg msg;
1282 int buffs = RX_DESCS;
1283 int i;
1284
1285 ports_open--;
1286 qmgr_disable_irq(port->plat->rxq);
1287 napi_disable(&port->napi);
1288 netif_stop_queue(dev);
1289
1290 while (queue_get_desc(RXFREE_QUEUE(port->id), port, 0) >= 0)
1291 buffs--;
1292
1293 memset(&msg, 0, sizeof(msg));
1294 msg.cmd = NPE_SETLOOPBACK_MODE;
1295 msg.eth_id = port->id;
1296 msg.byte3 = 1;
1297 if (npe_send_recv_message(port->npe, &msg, "ETH_ENABLE_LOOPBACK"))
1298 netdev_crit(dev, "unable to enable loopback\n");
1299
1300 i = 0;
1301 do {
1302 while (queue_get_desc(port->plat->rxq, port, 0) >= 0)
1303 buffs--;
1304 if (!buffs)
1305 break;
1306 if (qmgr_stat_empty(TX_QUEUE(port->id))) {
1307
1308 struct desc *desc;
1309 u32 phys;
1310 int n = queue_get_desc(port->plat->txreadyq, port, 1);
1311 BUG_ON(n < 0);
1312 desc = tx_desc_ptr(port, n);
1313 phys = tx_desc_phys(port, n);
1314 desc->buf_len = desc->pkt_len = 1;
1315 wmb();
1316 queue_put_desc(TX_QUEUE(port->id), phys, desc);
1317 }
1318 udelay(1);
1319 } while (++i < MAX_CLOSE_WAIT);
1320
1321 if (buffs)
1322 netdev_crit(dev, "unable to drain RX queue, %i buffer(s)"
1323 " left in NPE\n", buffs);
1324#if DEBUG_CLOSE
1325 if (!buffs)
1326 netdev_debug(dev, "draining RX queue took %i cycles\n", i);
1327#endif
1328
1329 buffs = TX_DESCS;
1330 while (queue_get_desc(TX_QUEUE(port->id), port, 1) >= 0)
1331 buffs--;
1332
1333 i = 0;
1334 do {
1335 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1336 buffs--;
1337 if (!buffs)
1338 break;
1339 } while (++i < MAX_CLOSE_WAIT);
1340
1341 if (buffs)
1342 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) "
1343 "left in NPE\n", buffs);
1344#if DEBUG_CLOSE
1345 if (!buffs)
1346 netdev_debug(dev, "draining TX queues took %i cycles\n", i);
1347#endif
1348
1349 msg.byte3 = 0;
1350 if (npe_send_recv_message(port->npe, &msg, "ETH_DISABLE_LOOPBACK"))
1351 netdev_crit(dev, "unable to disable loopback\n");
1352
1353 phy_stop(dev->phydev);
1354
1355 if (!ports_open)
1356 qmgr_disable_irq(TXDONE_QUEUE);
1357 destroy_queues(port);
1358 release_queues(port);
1359 return 0;
1360}
1361
1362static const struct net_device_ops ixp4xx_netdev_ops = {
1363 .ndo_open = eth_open,
1364 .ndo_stop = eth_close,
1365 .ndo_start_xmit = eth_xmit,
1366 .ndo_set_rx_mode = eth_set_mcast_list,
1367 .ndo_eth_ioctl = eth_ioctl,
1368 .ndo_set_mac_address = eth_mac_addr,
1369 .ndo_validate_addr = eth_validate_addr,
1370};
1371
1372#ifdef CONFIG_OF
1373static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev)
1374{
1375 struct device_node *np = dev->of_node;
1376 struct of_phandle_args queue_spec;
1377 struct of_phandle_args npe_spec;
1378 struct device_node *mdio_np;
1379 struct eth_plat_info *plat;
1380 int ret;
1381
1382 plat = devm_kzalloc(dev, sizeof(*plat), GFP_KERNEL);
1383 if (!plat)
1384 return NULL;
1385
1386 ret = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0,
1387 &npe_spec);
1388 if (ret) {
1389 dev_err(dev, "no NPE engine specified\n");
1390 return NULL;
1391 }
1392
1393 plat->npe = (npe_spec.args[0] << 4);
1394
1395
1396 mdio_np = of_get_child_by_name(np, "mdio");
1397 if (mdio_np) {
1398 plat->has_mdio = true;
1399 mdio_bus_np = mdio_np;
1400
1401 }
1402
1403
1404 ret = of_parse_phandle_with_fixed_args(np, "queue-rx", 1, 0,
1405 &queue_spec);
1406 if (ret) {
1407 dev_err(dev, "no rx queue phandle\n");
1408 return NULL;
1409 }
1410 plat->rxq = queue_spec.args[0];
1411
1412
1413 ret = of_parse_phandle_with_fixed_args(np, "queue-txready", 1, 0,
1414 &queue_spec);
1415 if (ret) {
1416 dev_err(dev, "no txready queue phandle\n");
1417 return NULL;
1418 }
1419 plat->txreadyq = queue_spec.args[0];
1420
1421 return plat;
1422}
1423#else
1424static struct eth_plat_info *ixp4xx_of_get_platdata(struct device *dev)
1425{
1426 return NULL;
1427}
1428#endif
1429
1430static int ixp4xx_eth_probe(struct platform_device *pdev)
1431{
1432 struct phy_device *phydev = NULL;
1433 struct device *dev = &pdev->dev;
1434 struct device_node *np = dev->of_node;
1435 struct eth_plat_info *plat;
1436 struct net_device *ndev;
1437 struct port *port;
1438 int err;
1439
1440 if (np) {
1441 plat = ixp4xx_of_get_platdata(dev);
1442 if (!plat)
1443 return -ENODEV;
1444 } else {
1445 plat = dev_get_platdata(dev);
1446 if (!plat)
1447 return -ENODEV;
1448 plat->npe = pdev->id;
1449 switch (plat->npe) {
1450 case IXP4XX_ETH_NPEA:
1451
1452 break;
1453 case IXP4XX_ETH_NPEB:
1454
1455
1456
1457
1458 if (!cpu_is_ixp43x()) {
1459 if (!(ixp4xx_read_feature_bits() &
1460 IXP4XX_FEATURE_NPEB_ETH0))
1461 return -ENODEV;
1462
1463 plat->has_mdio = true;
1464 }
1465 break;
1466 case IXP4XX_ETH_NPEC:
1467
1468
1469
1470
1471 if (cpu_is_ixp43x()) {
1472 if (!(ixp4xx_read_feature_bits() &
1473 IXP4XX_FEATURE_NPEC_ETH))
1474 return -ENODEV;
1475
1476 plat->has_mdio = true;
1477 }
1478 break;
1479 default:
1480 return -ENODEV;
1481 }
1482 }
1483
1484 if (!(ndev = devm_alloc_etherdev(dev, sizeof(struct port))))
1485 return -ENOMEM;
1486
1487 SET_NETDEV_DEV(ndev, dev);
1488 port = netdev_priv(ndev);
1489 port->netdev = ndev;
1490 port->id = plat->npe;
1491 port->phc_index = -1;
1492
1493
1494 port->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1495 if (IS_ERR(port->regs))
1496 return PTR_ERR(port->regs);
1497
1498
1499 if (plat->has_mdio) {
1500 err = ixp4xx_mdio_register(port->regs);
1501 if (err) {
1502 dev_err(dev, "failed to register MDIO bus\n");
1503 return err;
1504 }
1505 }
1506
1507
1508
1509 if (!mdio_bus)
1510 return -EPROBE_DEFER;
1511
1512 ndev->netdev_ops = &ixp4xx_netdev_ops;
1513 ndev->ethtool_ops = &ixp4xx_ethtool_ops;
1514 ndev->tx_queue_len = 100;
1515
1516 ndev->dev.dma_mask = dev->dma_mask;
1517 ndev->dev.coherent_dma_mask = dev->coherent_dma_mask;
1518
1519 netif_napi_add(ndev, &port->napi, eth_poll, NAPI_WEIGHT);
1520
1521 if (!(port->npe = npe_request(NPE_ID(port->id))))
1522 return -EIO;
1523
1524 port->plat = plat;
1525 npe_port_tab[NPE_ID(port->id)] = port;
1526 eth_hw_addr_set(ndev, plat->hwaddr);
1527
1528 platform_set_drvdata(pdev, ndev);
1529
1530 __raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,
1531 &port->regs->core_control);
1532 udelay(50);
1533 __raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);
1534 udelay(50);
1535
1536 if (np) {
1537 phydev = of_phy_get_and_connect(ndev, np, ixp4xx_adjust_link);
1538 } else {
1539 phydev = mdiobus_get_phy(mdio_bus, plat->phy);
1540 if (!phydev) {
1541 err = -ENODEV;
1542 dev_err(dev, "could not connect phydev (%d)\n", err);
1543 goto err_free_mem;
1544 }
1545 err = phy_connect_direct(ndev, phydev, ixp4xx_adjust_link,
1546 PHY_INTERFACE_MODE_MII);
1547 if (err)
1548 goto err_free_mem;
1549
1550 }
1551 if (!phydev) {
1552 err = -ENODEV;
1553 dev_err(dev, "no phydev\n");
1554 goto err_free_mem;
1555 }
1556
1557 phydev->irq = PHY_POLL;
1558
1559 if ((err = register_netdev(ndev)))
1560 goto err_phy_dis;
1561
1562 netdev_info(ndev, "%s: MII PHY %i on %s\n", ndev->name, plat->phy,
1563 npe_name(port->npe));
1564
1565 return 0;
1566
1567err_phy_dis:
1568 phy_disconnect(phydev);
1569err_free_mem:
1570 npe_port_tab[NPE_ID(port->id)] = NULL;
1571 npe_release(port->npe);
1572 return err;
1573}
1574
1575static int ixp4xx_eth_remove(struct platform_device *pdev)
1576{
1577 struct net_device *ndev = platform_get_drvdata(pdev);
1578 struct phy_device *phydev = ndev->phydev;
1579 struct port *port = netdev_priv(ndev);
1580
1581 unregister_netdev(ndev);
1582 phy_disconnect(phydev);
1583 ixp4xx_mdio_remove();
1584 npe_port_tab[NPE_ID(port->id)] = NULL;
1585 npe_release(port->npe);
1586 return 0;
1587}
1588
1589static const struct of_device_id ixp4xx_eth_of_match[] = {
1590 {
1591 .compatible = "intel,ixp4xx-ethernet",
1592 },
1593 { },
1594};
1595
1596static struct platform_driver ixp4xx_eth_driver = {
1597 .driver = {
1598 .name = DRV_NAME,
1599 .of_match_table = of_match_ptr(ixp4xx_eth_of_match),
1600 },
1601 .probe = ixp4xx_eth_probe,
1602 .remove = ixp4xx_eth_remove,
1603};
1604module_platform_driver(ixp4xx_eth_driver);
1605
1606MODULE_AUTHOR("Krzysztof Halasa");
1607MODULE_DESCRIPTION("Intel IXP4xx Ethernet driver");
1608MODULE_LICENSE("GPL v2");
1609MODULE_ALIAS("platform:ixp4xx_eth");
1610
