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22#include <linux/bitfield.h>
23#include <linux/ethtool_netlink.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
27#include <linux/micrel_phy.h>
28#include <linux/of.h>
29#include <linux/clk.h>
30#include <linux/delay.h>
31
32
33#define MII_KSZPHY_OMSO 0x16
34#define KSZPHY_OMSO_FACTORY_TEST BIT(15)
35#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
36#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
37#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
38#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
39
40
41#define MII_KSZPHY_INTCS 0x1B
42#define KSZPHY_INTCS_JABBER BIT(15)
43#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
44#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
45#define KSZPHY_INTCS_PARELLEL BIT(12)
46#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
47#define KSZPHY_INTCS_LINK_DOWN BIT(10)
48#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
49#define KSZPHY_INTCS_LINK_UP BIT(8)
50#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
51 KSZPHY_INTCS_LINK_DOWN)
52#define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)
53#define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)
54#define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\
55 KSZPHY_INTCS_LINK_UP_STATUS)
56
57
58#define KSZ8081_LMD 0x1d
59#define KSZ8081_LMD_ENABLE_TEST BIT(15)
60#define KSZ8081_LMD_STAT_NORMAL 0
61#define KSZ8081_LMD_STAT_OPEN 1
62#define KSZ8081_LMD_STAT_SHORT 2
63#define KSZ8081_LMD_STAT_FAIL 3
64#define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)
65
66#define KSZ8081_LMD_SHORT_INDICATOR BIT(12)
67#define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)
68
69
70#define MII_KSZPHY_CTRL_1 0x1e
71#define KSZ8081_CTRL1_MDIX_STAT BIT(4)
72
73
74#define MII_KSZPHY_CTRL_2 0x1f
75#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
76
77#define KSZ8081_CTRL2_HP_MDIX BIT(15)
78#define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)
79#define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)
80#define KSZ8081_CTRL2_FORCE_LINK BIT(11)
81#define KSZ8081_CTRL2_POWER_SAVING BIT(10)
82#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
83#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
84
85
86#define MII_KSZPHY_EXTREG 0x0b
87#define KSZPHY_EXTREG_WRITE 0x8000
88
89#define MII_KSZPHY_EXTREG_WRITE 0x0c
90#define MII_KSZPHY_EXTREG_READ 0x0d
91
92
93#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
94#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
95#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
96
97#define PS_TO_REG 200
98
99struct kszphy_hw_stat {
100 const char *string;
101 u8 reg;
102 u8 bits;
103};
104
105static struct kszphy_hw_stat kszphy_hw_stats[] = {
106 { "phy_receive_errors", 21, 16},
107 { "phy_idle_errors", 10, 8 },
108};
109
110struct kszphy_type {
111 u32 led_mode_reg;
112 u16 interrupt_level_mask;
113 bool has_broadcast_disable;
114 bool has_nand_tree_disable;
115 bool has_rmii_ref_clk_sel;
116};
117
118struct kszphy_priv {
119 const struct kszphy_type *type;
120 int led_mode;
121 bool rmii_ref_clk_sel;
122 bool rmii_ref_clk_sel_val;
123 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
124};
125
126static const struct kszphy_type ksz8021_type = {
127 .led_mode_reg = MII_KSZPHY_CTRL_2,
128 .has_broadcast_disable = true,
129 .has_nand_tree_disable = true,
130 .has_rmii_ref_clk_sel = true,
131};
132
133static const struct kszphy_type ksz8041_type = {
134 .led_mode_reg = MII_KSZPHY_CTRL_1,
135};
136
137static const struct kszphy_type ksz8051_type = {
138 .led_mode_reg = MII_KSZPHY_CTRL_2,
139 .has_nand_tree_disable = true,
140};
141
142static const struct kszphy_type ksz8081_type = {
143 .led_mode_reg = MII_KSZPHY_CTRL_2,
144 .has_broadcast_disable = true,
145 .has_nand_tree_disable = true,
146 .has_rmii_ref_clk_sel = true,
147};
148
149static const struct kszphy_type ks8737_type = {
150 .interrupt_level_mask = BIT(14),
151};
152
153static const struct kszphy_type ksz9021_type = {
154 .interrupt_level_mask = BIT(14),
155};
156
157static int kszphy_extended_write(struct phy_device *phydev,
158 u32 regnum, u16 val)
159{
160 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
161 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
162}
163
164static int kszphy_extended_read(struct phy_device *phydev,
165 u32 regnum)
166{
167 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
168 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
169}
170
171static int kszphy_ack_interrupt(struct phy_device *phydev)
172{
173
174 int rc;
175
176 rc = phy_read(phydev, MII_KSZPHY_INTCS);
177
178 return (rc < 0) ? rc : 0;
179}
180
181static int kszphy_config_intr(struct phy_device *phydev)
182{
183 const struct kszphy_type *type = phydev->drv->driver_data;
184 int temp, err;
185 u16 mask;
186
187 if (type && type->interrupt_level_mask)
188 mask = type->interrupt_level_mask;
189 else
190 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
191
192
193 temp = phy_read(phydev, MII_KSZPHY_CTRL);
194 if (temp < 0)
195 return temp;
196 temp &= ~mask;
197 phy_write(phydev, MII_KSZPHY_CTRL, temp);
198
199
200 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
201 err = kszphy_ack_interrupt(phydev);
202 if (err)
203 return err;
204
205 temp = KSZPHY_INTCS_ALL;
206 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
207 } else {
208 temp = 0;
209 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
210 if (err)
211 return err;
212
213 err = kszphy_ack_interrupt(phydev);
214 }
215
216 return err;
217}
218
219static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
220{
221 int irq_status;
222
223 irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
224 if (irq_status < 0) {
225 phy_error(phydev);
226 return IRQ_NONE;
227 }
228
229 if (!(irq_status & KSZPHY_INTCS_STATUS))
230 return IRQ_NONE;
231
232 phy_trigger_machine(phydev);
233
234 return IRQ_HANDLED;
235}
236
237static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
238{
239 int ctrl;
240
241 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
242 if (ctrl < 0)
243 return ctrl;
244
245 if (val)
246 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
247 else
248 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
249
250 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
251}
252
253static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
254{
255 int rc, temp, shift;
256
257 switch (reg) {
258 case MII_KSZPHY_CTRL_1:
259 shift = 14;
260 break;
261 case MII_KSZPHY_CTRL_2:
262 shift = 4;
263 break;
264 default:
265 return -EINVAL;
266 }
267
268 temp = phy_read(phydev, reg);
269 if (temp < 0) {
270 rc = temp;
271 goto out;
272 }
273
274 temp &= ~(3 << shift);
275 temp |= val << shift;
276 rc = phy_write(phydev, reg, temp);
277out:
278 if (rc < 0)
279 phydev_err(phydev, "failed to set led mode\n");
280
281 return rc;
282}
283
284
285
286
287static int kszphy_broadcast_disable(struct phy_device *phydev)
288{
289 int ret;
290
291 ret = phy_read(phydev, MII_KSZPHY_OMSO);
292 if (ret < 0)
293 goto out;
294
295 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
296out:
297 if (ret)
298 phydev_err(phydev, "failed to disable broadcast address\n");
299
300 return ret;
301}
302
303static int kszphy_nand_tree_disable(struct phy_device *phydev)
304{
305 int ret;
306
307 ret = phy_read(phydev, MII_KSZPHY_OMSO);
308 if (ret < 0)
309 goto out;
310
311 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
312 return 0;
313
314 ret = phy_write(phydev, MII_KSZPHY_OMSO,
315 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
316out:
317 if (ret)
318 phydev_err(phydev, "failed to disable NAND tree mode\n");
319
320 return ret;
321}
322
323
324static int kszphy_config_reset(struct phy_device *phydev)
325{
326 struct kszphy_priv *priv = phydev->priv;
327 int ret;
328
329 if (priv->rmii_ref_clk_sel) {
330 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
331 if (ret) {
332 phydev_err(phydev,
333 "failed to set rmii reference clock\n");
334 return ret;
335 }
336 }
337
338 if (priv->led_mode >= 0)
339 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
340
341 return 0;
342}
343
344static int kszphy_config_init(struct phy_device *phydev)
345{
346 struct kszphy_priv *priv = phydev->priv;
347 const struct kszphy_type *type;
348
349 if (!priv)
350 return 0;
351
352 type = priv->type;
353
354 if (type->has_broadcast_disable)
355 kszphy_broadcast_disable(phydev);
356
357 if (type->has_nand_tree_disable)
358 kszphy_nand_tree_disable(phydev);
359
360 return kszphy_config_reset(phydev);
361}
362
363static int ksz8041_fiber_mode(struct phy_device *phydev)
364{
365 struct device_node *of_node = phydev->mdio.dev.of_node;
366
367 return of_property_read_bool(of_node, "micrel,fiber-mode");
368}
369
370static int ksz8041_config_init(struct phy_device *phydev)
371{
372 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
373
374
375 if (ksz8041_fiber_mode(phydev)) {
376 phydev->dev_flags |= MICREL_PHY_FXEN;
377 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
378 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
379
380 linkmode_and(phydev->supported, phydev->supported, mask);
381 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
382 phydev->supported);
383 linkmode_and(phydev->advertising, phydev->advertising, mask);
384 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
385 phydev->advertising);
386 phydev->autoneg = AUTONEG_DISABLE;
387 }
388
389 return kszphy_config_init(phydev);
390}
391
392static int ksz8041_config_aneg(struct phy_device *phydev)
393{
394
395 if (phydev->dev_flags & MICREL_PHY_FXEN) {
396 phydev->speed = SPEED_100;
397 return 0;
398 }
399
400 return genphy_config_aneg(phydev);
401}
402
403static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
404 const bool ksz_8051)
405{
406 int ret;
407
408 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
409 return 0;
410
411 ret = phy_read(phydev, MII_BMSR);
412 if (ret < 0)
413 return ret;
414
415
416
417
418
419
420 ret &= BMSR_ERCAP;
421 if (ksz_8051)
422 return ret;
423 else
424 return !ret;
425}
426
427static int ksz8051_match_phy_device(struct phy_device *phydev)
428{
429 return ksz8051_ksz8795_match_phy_device(phydev, true);
430}
431
432static int ksz8081_config_init(struct phy_device *phydev)
433{
434
435
436
437
438
439 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
440
441 return kszphy_config_init(phydev);
442}
443
444static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
445{
446 u16 val;
447
448 switch (ctrl) {
449 case ETH_TP_MDI:
450 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
451 break;
452 case ETH_TP_MDI_X:
453 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
454 KSZ8081_CTRL2_MDI_MDI_X_SELECT;
455 break;
456 case ETH_TP_MDI_AUTO:
457 val = 0;
458 break;
459 default:
460 return 0;
461 }
462
463 return phy_modify(phydev, MII_KSZPHY_CTRL_2,
464 KSZ8081_CTRL2_HP_MDIX |
465 KSZ8081_CTRL2_MDI_MDI_X_SELECT |
466 KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
467 KSZ8081_CTRL2_HP_MDIX | val);
468}
469
470static int ksz8081_config_aneg(struct phy_device *phydev)
471{
472 int ret;
473
474 ret = genphy_config_aneg(phydev);
475 if (ret)
476 return ret;
477
478
479
480
481
482 return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
483}
484
485static int ksz8081_mdix_update(struct phy_device *phydev)
486{
487 int ret;
488
489 ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
490 if (ret < 0)
491 return ret;
492
493 if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
494 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
495 phydev->mdix_ctrl = ETH_TP_MDI_X;
496 else
497 phydev->mdix_ctrl = ETH_TP_MDI;
498 } else {
499 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
500 }
501
502 ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
503 if (ret < 0)
504 return ret;
505
506 if (ret & KSZ8081_CTRL1_MDIX_STAT)
507 phydev->mdix = ETH_TP_MDI;
508 else
509 phydev->mdix = ETH_TP_MDI_X;
510
511 return 0;
512}
513
514static int ksz8081_read_status(struct phy_device *phydev)
515{
516 int ret;
517
518 ret = ksz8081_mdix_update(phydev);
519 if (ret < 0)
520 return ret;
521
522 return genphy_read_status(phydev);
523}
524
525static int ksz8061_config_init(struct phy_device *phydev)
526{
527 int ret;
528
529 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
530 if (ret)
531 return ret;
532
533 return kszphy_config_init(phydev);
534}
535
536static int ksz8795_match_phy_device(struct phy_device *phydev)
537{
538 return ksz8051_ksz8795_match_phy_device(phydev, false);
539}
540
541static int ksz9021_load_values_from_of(struct phy_device *phydev,
542 const struct device_node *of_node,
543 u16 reg,
544 const char *field1, const char *field2,
545 const char *field3, const char *field4)
546{
547 int val1 = -1;
548 int val2 = -2;
549 int val3 = -3;
550 int val4 = -4;
551 int newval;
552 int matches = 0;
553
554 if (!of_property_read_u32(of_node, field1, &val1))
555 matches++;
556
557 if (!of_property_read_u32(of_node, field2, &val2))
558 matches++;
559
560 if (!of_property_read_u32(of_node, field3, &val3))
561 matches++;
562
563 if (!of_property_read_u32(of_node, field4, &val4))
564 matches++;
565
566 if (!matches)
567 return 0;
568
569 if (matches < 4)
570 newval = kszphy_extended_read(phydev, reg);
571 else
572 newval = 0;
573
574 if (val1 != -1)
575 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
576
577 if (val2 != -2)
578 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
579
580 if (val3 != -3)
581 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
582
583 if (val4 != -4)
584 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
585
586 return kszphy_extended_write(phydev, reg, newval);
587}
588
589static int ksz9021_config_init(struct phy_device *phydev)
590{
591 const struct device_node *of_node;
592 const struct device *dev_walker;
593
594
595
596
597
598 dev_walker = &phydev->mdio.dev;
599 do {
600 of_node = dev_walker->of_node;
601 dev_walker = dev_walker->parent;
602
603 } while (!of_node && dev_walker);
604
605 if (of_node) {
606 ksz9021_load_values_from_of(phydev, of_node,
607 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
608 "txen-skew-ps", "txc-skew-ps",
609 "rxdv-skew-ps", "rxc-skew-ps");
610 ksz9021_load_values_from_of(phydev, of_node,
611 MII_KSZPHY_RX_DATA_PAD_SKEW,
612 "rxd0-skew-ps", "rxd1-skew-ps",
613 "rxd2-skew-ps", "rxd3-skew-ps");
614 ksz9021_load_values_from_of(phydev, of_node,
615 MII_KSZPHY_TX_DATA_PAD_SKEW,
616 "txd0-skew-ps", "txd1-skew-ps",
617 "txd2-skew-ps", "txd3-skew-ps");
618 }
619 return 0;
620}
621
622#define KSZ9031_PS_TO_REG 60
623
624
625
626#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
627#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
628
629
630#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
631#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
632#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
633
634#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
635#define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
636#define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
637#define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
638#define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
639
640#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
641#define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
642#define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
643#define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
644#define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
645
646#define MII_KSZ9031RN_CLK_PAD_SKEW 8
647#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
648#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
649
650
651
652
653
654
655
656
657#define RX_ID 0x7
658#define RX_CLK_ID 0x19
659
660
661
662
663#define RX_ND 0xc
664#define RX_CLK_ND 0x0
665
666
667#define TX_ID 0x0
668#define TX_CLK_ID 0x1f
669
670
671
672
673#define TX_ND 0x7
674#define TX_CLK_ND 0xf
675
676
677#define MII_KSZ9031RN_EDPD 0x23
678#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
679
680static int ksz9031_of_load_skew_values(struct phy_device *phydev,
681 const struct device_node *of_node,
682 u16 reg, size_t field_sz,
683 const char *field[], u8 numfields,
684 bool *update)
685{
686 int val[4] = {-1, -2, -3, -4};
687 int matches = 0;
688 u16 mask;
689 u16 maxval;
690 u16 newval;
691 int i;
692
693 for (i = 0; i < numfields; i++)
694 if (!of_property_read_u32(of_node, field[i], val + i))
695 matches++;
696
697 if (!matches)
698 return 0;
699
700 *update |= true;
701
702 if (matches < numfields)
703 newval = phy_read_mmd(phydev, 2, reg);
704 else
705 newval = 0;
706
707 maxval = (field_sz == 4) ? 0xf : 0x1f;
708 for (i = 0; i < numfields; i++)
709 if (val[i] != -(i + 1)) {
710 mask = 0xffff;
711 mask ^= maxval << (field_sz * i);
712 newval = (newval & mask) |
713 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
714 << (field_sz * i));
715 }
716
717 return phy_write_mmd(phydev, 2, reg, newval);
718}
719
720
721static int ksz9031_center_flp_timing(struct phy_device *phydev)
722{
723 int result;
724
725 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
726 0x0006);
727 if (result)
728 return result;
729
730 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
731 0x1A80);
732 if (result)
733 return result;
734
735 return genphy_restart_aneg(phydev);
736}
737
738
739static int ksz9031_enable_edpd(struct phy_device *phydev)
740{
741 int reg;
742
743 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
744 if (reg < 0)
745 return reg;
746 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
747 reg | MII_KSZ9031RN_EDPD_ENABLE);
748}
749
750static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
751{
752 u16 rx, tx, rx_clk, tx_clk;
753 int ret;
754
755 switch (phydev->interface) {
756 case PHY_INTERFACE_MODE_RGMII:
757 tx = TX_ND;
758 tx_clk = TX_CLK_ND;
759 rx = RX_ND;
760 rx_clk = RX_CLK_ND;
761 break;
762 case PHY_INTERFACE_MODE_RGMII_ID:
763 tx = TX_ID;
764 tx_clk = TX_CLK_ID;
765 rx = RX_ID;
766 rx_clk = RX_CLK_ID;
767 break;
768 case PHY_INTERFACE_MODE_RGMII_RXID:
769 tx = TX_ND;
770 tx_clk = TX_CLK_ND;
771 rx = RX_ID;
772 rx_clk = RX_CLK_ID;
773 break;
774 case PHY_INTERFACE_MODE_RGMII_TXID:
775 tx = TX_ID;
776 tx_clk = TX_CLK_ID;
777 rx = RX_ND;
778 rx_clk = RX_CLK_ND;
779 break;
780 default:
781 return 0;
782 }
783
784 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
785 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
786 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
787 if (ret < 0)
788 return ret;
789
790 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
791 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
792 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
793 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
794 FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
795 if (ret < 0)
796 return ret;
797
798 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
799 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
800 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
801 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
802 FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
803 if (ret < 0)
804 return ret;
805
806 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
807 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
808 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
809}
810
811static int ksz9031_config_init(struct phy_device *phydev)
812{
813 const struct device_node *of_node;
814 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
815 static const char *rx_data_skews[4] = {
816 "rxd0-skew-ps", "rxd1-skew-ps",
817 "rxd2-skew-ps", "rxd3-skew-ps"
818 };
819 static const char *tx_data_skews[4] = {
820 "txd0-skew-ps", "txd1-skew-ps",
821 "txd2-skew-ps", "txd3-skew-ps"
822 };
823 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
824 const struct device *dev_walker;
825 int result;
826
827 result = ksz9031_enable_edpd(phydev);
828 if (result < 0)
829 return result;
830
831
832
833
834
835 dev_walker = &phydev->mdio.dev;
836 do {
837 of_node = dev_walker->of_node;
838 dev_walker = dev_walker->parent;
839 } while (!of_node && dev_walker);
840
841 if (of_node) {
842 bool update = false;
843
844 if (phy_interface_is_rgmii(phydev)) {
845 result = ksz9031_config_rgmii_delay(phydev);
846 if (result < 0)
847 return result;
848 }
849
850 ksz9031_of_load_skew_values(phydev, of_node,
851 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
852 clk_skews, 2, &update);
853
854 ksz9031_of_load_skew_values(phydev, of_node,
855 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
856 control_skews, 2, &update);
857
858 ksz9031_of_load_skew_values(phydev, of_node,
859 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
860 rx_data_skews, 4, &update);
861
862 ksz9031_of_load_skew_values(phydev, of_node,
863 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
864 tx_data_skews, 4, &update);
865
866 if (update && !phy_interface_is_rgmii(phydev))
867 phydev_warn(phydev,
868 "*-skew-ps values should be used only with RGMII PHY modes\n");
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885 if (of_property_read_bool(of_node, "micrel,force-master")) {
886 result = phy_read(phydev, MII_CTRL1000);
887 if (result < 0)
888 goto err_force_master;
889
890
891 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
892 result = phy_write(phydev, MII_CTRL1000, result);
893 if (result < 0)
894 goto err_force_master;
895 }
896 }
897
898 return ksz9031_center_flp_timing(phydev);
899
900err_force_master:
901 phydev_err(phydev, "failed to force the phy to master mode\n");
902 return result;
903}
904
905#define KSZ9131_SKEW_5BIT_MAX 2400
906#define KSZ9131_SKEW_4BIT_MAX 800
907#define KSZ9131_OFFSET 700
908#define KSZ9131_STEP 100
909
910static int ksz9131_of_load_skew_values(struct phy_device *phydev,
911 struct device_node *of_node,
912 u16 reg, size_t field_sz,
913 char *field[], u8 numfields)
914{
915 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
916 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
917 int skewval, skewmax = 0;
918 int matches = 0;
919 u16 maxval;
920 u16 newval;
921 u16 mask;
922 int i;
923
924
925 if (field_sz == 5)
926 skewmax = KSZ9131_SKEW_5BIT_MAX;
927 else
928 skewmax = KSZ9131_SKEW_4BIT_MAX;
929
930 for (i = 0; i < numfields; i++)
931 if (!of_property_read_s32(of_node, field[i], &skewval)) {
932 if (skewval < -KSZ9131_OFFSET)
933 skewval = -KSZ9131_OFFSET;
934 else if (skewval > skewmax)
935 skewval = skewmax;
936
937 val[i] = skewval + KSZ9131_OFFSET;
938 matches++;
939 }
940
941 if (!matches)
942 return 0;
943
944 if (matches < numfields)
945 newval = phy_read_mmd(phydev, 2, reg);
946 else
947 newval = 0;
948
949 maxval = (field_sz == 4) ? 0xf : 0x1f;
950 for (i = 0; i < numfields; i++)
951 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
952 mask = 0xffff;
953 mask ^= maxval << (field_sz * i);
954 newval = (newval & mask) |
955 (((val[i] / KSZ9131_STEP) & maxval)
956 << (field_sz * i));
957 }
958
959 return phy_write_mmd(phydev, 2, reg, newval);
960}
961
962#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
963#define KSZ9131RN_RXC_DLL_CTRL 76
964#define KSZ9131RN_TXC_DLL_CTRL 77
965#define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
966#define KSZ9131RN_DLL_ENABLE_DELAY 0
967#define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
968
969static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
970{
971 u16 rxcdll_val, txcdll_val;
972 int ret;
973
974 switch (phydev->interface) {
975 case PHY_INTERFACE_MODE_RGMII:
976 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
977 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
978 break;
979 case PHY_INTERFACE_MODE_RGMII_ID:
980 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
981 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
982 break;
983 case PHY_INTERFACE_MODE_RGMII_RXID:
984 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
985 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
986 break;
987 case PHY_INTERFACE_MODE_RGMII_TXID:
988 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
989 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
990 break;
991 default:
992 return 0;
993 }
994
995 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
996 KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
997 rxcdll_val);
998 if (ret < 0)
999 return ret;
1000
1001 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1002 KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1003 txcdll_val);
1004}
1005
1006
1007
1008
1009
1010
1011
1012static int ksz9131_led_errata(struct phy_device *phydev)
1013{
1014 int reg;
1015
1016 reg = phy_read_mmd(phydev, 2, 0);
1017 if (reg < 0)
1018 return reg;
1019
1020 if (!(reg & BIT(4)))
1021 return 0;
1022
1023 return phy_set_bits(phydev, 0x1e, BIT(9));
1024}
1025
1026static int ksz9131_config_init(struct phy_device *phydev)
1027{
1028 struct device_node *of_node;
1029 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1030 char *rx_data_skews[4] = {
1031 "rxd0-skew-psec", "rxd1-skew-psec",
1032 "rxd2-skew-psec", "rxd3-skew-psec"
1033 };
1034 char *tx_data_skews[4] = {
1035 "txd0-skew-psec", "txd1-skew-psec",
1036 "txd2-skew-psec", "txd3-skew-psec"
1037 };
1038 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1039 const struct device *dev_walker;
1040 int ret;
1041
1042 dev_walker = &phydev->mdio.dev;
1043 do {
1044 of_node = dev_walker->of_node;
1045 dev_walker = dev_walker->parent;
1046 } while (!of_node && dev_walker);
1047
1048 if (!of_node)
1049 return 0;
1050
1051 if (phy_interface_is_rgmii(phydev)) {
1052 ret = ksz9131_config_rgmii_delay(phydev);
1053 if (ret < 0)
1054 return ret;
1055 }
1056
1057 ret = ksz9131_of_load_skew_values(phydev, of_node,
1058 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1059 clk_skews, 2);
1060 if (ret < 0)
1061 return ret;
1062
1063 ret = ksz9131_of_load_skew_values(phydev, of_node,
1064 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1065 control_skews, 2);
1066 if (ret < 0)
1067 return ret;
1068
1069 ret = ksz9131_of_load_skew_values(phydev, of_node,
1070 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1071 rx_data_skews, 4);
1072 if (ret < 0)
1073 return ret;
1074
1075 ret = ksz9131_of_load_skew_values(phydev, of_node,
1076 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1077 tx_data_skews, 4);
1078 if (ret < 0)
1079 return ret;
1080
1081 ret = ksz9131_led_errata(phydev);
1082 if (ret < 0)
1083 return ret;
1084
1085 return 0;
1086}
1087
1088#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
1089#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
1090#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
1091static int ksz8873mll_read_status(struct phy_device *phydev)
1092{
1093 int regval;
1094
1095
1096 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1097
1098 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1099
1100 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1101 phydev->duplex = DUPLEX_HALF;
1102 else
1103 phydev->duplex = DUPLEX_FULL;
1104
1105 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1106 phydev->speed = SPEED_10;
1107 else
1108 phydev->speed = SPEED_100;
1109
1110 phydev->link = 1;
1111 phydev->pause = phydev->asym_pause = 0;
1112
1113 return 0;
1114}
1115
1116static int ksz9031_get_features(struct phy_device *phydev)
1117{
1118 int ret;
1119
1120 ret = genphy_read_abilities(phydev);
1121 if (ret < 0)
1122 return ret;
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1134
1135
1136
1137
1138 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1139
1140 return 0;
1141}
1142
1143static int ksz9031_read_status(struct phy_device *phydev)
1144{
1145 int err;
1146 int regval;
1147
1148 err = genphy_read_status(phydev);
1149 if (err)
1150 return err;
1151
1152
1153
1154
1155 regval = phy_read(phydev, MII_STAT1000);
1156 if ((regval & 0xFF) == 0xFF) {
1157 phy_init_hw(phydev);
1158 phydev->link = 0;
1159 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1160 phydev->drv->config_intr(phydev);
1161 return genphy_config_aneg(phydev);
1162 }
1163
1164 return 0;
1165}
1166
1167static int ksz8873mll_config_aneg(struct phy_device *phydev)
1168{
1169 return 0;
1170}
1171
1172static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1173{
1174 u16 val;
1175
1176 switch (ctrl) {
1177 case ETH_TP_MDI:
1178 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1179 break;
1180 case ETH_TP_MDI_X:
1181
1182
1183
1184
1185
1186
1187 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1188 break;
1189 case ETH_TP_MDI_AUTO:
1190 val = 0;
1191 break;
1192 default:
1193 return 0;
1194 }
1195
1196 return phy_modify(phydev, MII_BMCR,
1197 KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1198 KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1199 KSZ886X_BMCR_HP_MDIX | val);
1200}
1201
1202static int ksz886x_config_aneg(struct phy_device *phydev)
1203{
1204 int ret;
1205
1206 ret = genphy_config_aneg(phydev);
1207 if (ret)
1208 return ret;
1209
1210
1211
1212
1213
1214 return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1215}
1216
1217static int ksz886x_mdix_update(struct phy_device *phydev)
1218{
1219 int ret;
1220
1221 ret = phy_read(phydev, MII_BMCR);
1222 if (ret < 0)
1223 return ret;
1224
1225 if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1226 if (ret & KSZ886X_BMCR_FORCE_MDI)
1227 phydev->mdix_ctrl = ETH_TP_MDI_X;
1228 else
1229 phydev->mdix_ctrl = ETH_TP_MDI;
1230 } else {
1231 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1232 }
1233
1234 ret = phy_read(phydev, MII_KSZPHY_CTRL);
1235 if (ret < 0)
1236 return ret;
1237
1238
1239 if (ret & KSZ886X_CTRL_MDIX_STAT)
1240 phydev->mdix = ETH_TP_MDI_X;
1241 else
1242 phydev->mdix = ETH_TP_MDI;
1243
1244 return 0;
1245}
1246
1247static int ksz886x_read_status(struct phy_device *phydev)
1248{
1249 int ret;
1250
1251 ret = ksz886x_mdix_update(phydev);
1252 if (ret < 0)
1253 return ret;
1254
1255 return genphy_read_status(phydev);
1256}
1257
1258static int kszphy_get_sset_count(struct phy_device *phydev)
1259{
1260 return ARRAY_SIZE(kszphy_hw_stats);
1261}
1262
1263static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1264{
1265 int i;
1266
1267 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1268 strlcpy(data + i * ETH_GSTRING_LEN,
1269 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1270 }
1271}
1272
1273static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1274{
1275 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1276 struct kszphy_priv *priv = phydev->priv;
1277 int val;
1278 u64 ret;
1279
1280 val = phy_read(phydev, stat.reg);
1281 if (val < 0) {
1282 ret = U64_MAX;
1283 } else {
1284 val = val & ((1 << stat.bits) - 1);
1285 priv->stats[i] += val;
1286 ret = priv->stats[i];
1287 }
1288
1289 return ret;
1290}
1291
1292static void kszphy_get_stats(struct phy_device *phydev,
1293 struct ethtool_stats *stats, u64 *data)
1294{
1295 int i;
1296
1297 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1298 data[i] = kszphy_get_stat(phydev, i);
1299}
1300
1301static int kszphy_suspend(struct phy_device *phydev)
1302{
1303
1304 if (phy_interrupt_is_valid(phydev)) {
1305 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1306 if (phydev->drv->config_intr)
1307 phydev->drv->config_intr(phydev);
1308 }
1309
1310 return genphy_suspend(phydev);
1311}
1312
1313static int kszphy_resume(struct phy_device *phydev)
1314{
1315 int ret;
1316
1317 genphy_resume(phydev);
1318
1319
1320
1321
1322
1323 usleep_range(1000, 2000);
1324
1325 ret = kszphy_config_reset(phydev);
1326 if (ret)
1327 return ret;
1328
1329
1330 if (phy_interrupt_is_valid(phydev)) {
1331 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1332 if (phydev->drv->config_intr)
1333 phydev->drv->config_intr(phydev);
1334 }
1335
1336 return 0;
1337}
1338
1339static int kszphy_probe(struct phy_device *phydev)
1340{
1341 const struct kszphy_type *type = phydev->drv->driver_data;
1342 const struct device_node *np = phydev->mdio.dev.of_node;
1343 struct kszphy_priv *priv;
1344 struct clk *clk;
1345 int ret;
1346
1347 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1348 if (!priv)
1349 return -ENOMEM;
1350
1351 phydev->priv = priv;
1352
1353 priv->type = type;
1354
1355 if (type->led_mode_reg) {
1356 ret = of_property_read_u32(np, "micrel,led-mode",
1357 &priv->led_mode);
1358 if (ret)
1359 priv->led_mode = -1;
1360
1361 if (priv->led_mode > 3) {
1362 phydev_err(phydev, "invalid led mode: 0x%02x\n",
1363 priv->led_mode);
1364 priv->led_mode = -1;
1365 }
1366 } else {
1367 priv->led_mode = -1;
1368 }
1369
1370 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1371
1372 if (!IS_ERR_OR_NULL(clk)) {
1373 unsigned long rate = clk_get_rate(clk);
1374 bool rmii_ref_clk_sel_25_mhz;
1375
1376 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1377 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1378 "micrel,rmii-reference-clock-select-25-mhz");
1379
1380 if (rate > 24500000 && rate < 25500000) {
1381 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1382 } else if (rate > 49500000 && rate < 50500000) {
1383 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1384 } else {
1385 phydev_err(phydev, "Clock rate out of range: %ld\n",
1386 rate);
1387 return -EINVAL;
1388 }
1389 }
1390
1391 if (ksz8041_fiber_mode(phydev))
1392 phydev->port = PORT_FIBRE;
1393
1394
1395 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
1396 priv->rmii_ref_clk_sel = true;
1397 priv->rmii_ref_clk_sel_val = true;
1398 }
1399
1400 return 0;
1401}
1402
1403static int ksz886x_cable_test_start(struct phy_device *phydev)
1404{
1405 if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
1406 return -EOPNOTSUPP;
1407
1408
1409
1410
1411
1412
1413 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
1414}
1415
1416static int ksz886x_cable_test_result_trans(u16 status)
1417{
1418 switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1419 case KSZ8081_LMD_STAT_NORMAL:
1420 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1421 case KSZ8081_LMD_STAT_SHORT:
1422 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1423 case KSZ8081_LMD_STAT_OPEN:
1424 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1425 case KSZ8081_LMD_STAT_FAIL:
1426 fallthrough;
1427 default:
1428 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1429 }
1430}
1431
1432static bool ksz886x_cable_test_failed(u16 status)
1433{
1434 return FIELD_GET(KSZ8081_LMD_STAT_MASK, status) ==
1435 KSZ8081_LMD_STAT_FAIL;
1436}
1437
1438static bool ksz886x_cable_test_fault_length_valid(u16 status)
1439{
1440 switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1441 case KSZ8081_LMD_STAT_OPEN:
1442 fallthrough;
1443 case KSZ8081_LMD_STAT_SHORT:
1444 return true;
1445 }
1446 return false;
1447}
1448
1449static int ksz886x_cable_test_fault_length(u16 status)
1450{
1451 int dt;
1452
1453
1454
1455
1456 dt = FIELD_GET(KSZ8081_LMD_DELTA_TIME_MASK, status);
1457
1458 return (dt * 400) / 10;
1459}
1460
1461static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
1462{
1463 int val, ret;
1464
1465 ret = phy_read_poll_timeout(phydev, KSZ8081_LMD, val,
1466 !(val & KSZ8081_LMD_ENABLE_TEST),
1467 30000, 100000, true);
1468
1469 return ret < 0 ? ret : 0;
1470}
1471
1472static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
1473{
1474 static const int ethtool_pair[] = {
1475 ETHTOOL_A_CABLE_PAIR_A,
1476 ETHTOOL_A_CABLE_PAIR_B,
1477 };
1478 int ret, val, mdix;
1479
1480
1481
1482
1483 if (pair == 0)
1484 mdix = ETH_TP_MDI;
1485 else
1486 mdix = ETH_TP_MDI_X;
1487
1488 switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
1489 case PHY_ID_KSZ8081:
1490 ret = ksz8081_config_mdix(phydev, mdix);
1491 break;
1492 case PHY_ID_KSZ886X:
1493 ret = ksz886x_config_mdix(phydev, mdix);
1494 break;
1495 default:
1496 ret = -ENODEV;
1497 }
1498
1499 if (ret)
1500 return ret;
1501
1502
1503
1504
1505 ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
1506 if (ret)
1507 return ret;
1508
1509 ret = ksz886x_cable_test_wait_for_completion(phydev);
1510 if (ret)
1511 return ret;
1512
1513 val = phy_read(phydev, KSZ8081_LMD);
1514 if (val < 0)
1515 return val;
1516
1517 if (ksz886x_cable_test_failed(val))
1518 return -EAGAIN;
1519
1520 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
1521 ksz886x_cable_test_result_trans(val));
1522 if (ret)
1523 return ret;
1524
1525 if (!ksz886x_cable_test_fault_length_valid(val))
1526 return 0;
1527
1528 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1529 ksz886x_cable_test_fault_length(val));
1530}
1531
1532static int ksz886x_cable_test_get_status(struct phy_device *phydev,
1533 bool *finished)
1534{
1535 unsigned long pair_mask = 0x3;
1536 int retries = 20;
1537 int pair, ret;
1538
1539 *finished = false;
1540
1541
1542 while (pair_mask && retries--) {
1543 for_each_set_bit(pair, &pair_mask, 4) {
1544 ret = ksz886x_cable_test_one_pair(phydev, pair);
1545 if (ret == -EAGAIN)
1546 continue;
1547 if (ret < 0)
1548 return ret;
1549 clear_bit(pair, &pair_mask);
1550 }
1551
1552
1553
1554
1555 if (pair_mask)
1556 msleep(2);
1557 }
1558
1559 *finished = true;
1560
1561 return ret;
1562}
1563
1564#define LAN_EXT_PAGE_ACCESS_CONTROL 0x16
1565#define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17
1566#define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000
1567
1568#define LAN8804_ALIGN_SWAP 0x4a
1569#define LAN8804_ALIGN_TX_A_B_SWAP 0x1
1570#define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
1571#define LAN8814_CLOCK_MANAGEMENT 0xd
1572#define LAN8814_LINK_QUALITY 0x8e
1573
1574static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
1575{
1576 u32 data;
1577
1578 phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
1579 phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
1580 phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
1581 (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
1582 data = phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
1583
1584 return data;
1585}
1586
1587static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
1588 u16 val)
1589{
1590 phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
1591 phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
1592 phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
1593 (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
1594
1595 val = phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
1596 if (val) {
1597 phydev_err(phydev, "Error: phy_write has returned error %d\n",
1598 val);
1599 return val;
1600 }
1601 return 0;
1602}
1603
1604static int lan8804_config_init(struct phy_device *phydev)
1605{
1606 int val;
1607
1608
1609 val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
1610 val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
1611 val |= LAN8804_ALIGN_TX_A_B_SWAP;
1612 lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
1613
1614
1615
1616
1617 lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
1618 lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
1619
1620 return 0;
1621}
1622
1623static struct phy_driver ksphy_driver[] = {
1624{
1625 .phy_id = PHY_ID_KS8737,
1626 .phy_id_mask = MICREL_PHY_ID_MASK,
1627 .name = "Micrel KS8737",
1628
1629 .driver_data = &ks8737_type,
1630 .config_init = kszphy_config_init,
1631 .config_intr = kszphy_config_intr,
1632 .handle_interrupt = kszphy_handle_interrupt,
1633 .suspend = genphy_suspend,
1634 .resume = genphy_resume,
1635}, {
1636 .phy_id = PHY_ID_KSZ8021,
1637 .phy_id_mask = 0x00ffffff,
1638 .name = "Micrel KSZ8021 or KSZ8031",
1639
1640 .driver_data = &ksz8021_type,
1641 .probe = kszphy_probe,
1642 .config_init = kszphy_config_init,
1643 .config_intr = kszphy_config_intr,
1644 .handle_interrupt = kszphy_handle_interrupt,
1645 .get_sset_count = kszphy_get_sset_count,
1646 .get_strings = kszphy_get_strings,
1647 .get_stats = kszphy_get_stats,
1648 .suspend = genphy_suspend,
1649 .resume = genphy_resume,
1650}, {
1651 .phy_id = PHY_ID_KSZ8031,
1652 .phy_id_mask = 0x00ffffff,
1653 .name = "Micrel KSZ8031",
1654
1655 .driver_data = &ksz8021_type,
1656 .probe = kszphy_probe,
1657 .config_init = kszphy_config_init,
1658 .config_intr = kszphy_config_intr,
1659 .handle_interrupt = kszphy_handle_interrupt,
1660 .get_sset_count = kszphy_get_sset_count,
1661 .get_strings = kszphy_get_strings,
1662 .get_stats = kszphy_get_stats,
1663 .suspend = genphy_suspend,
1664 .resume = genphy_resume,
1665}, {
1666 .phy_id = PHY_ID_KSZ8041,
1667 .phy_id_mask = MICREL_PHY_ID_MASK,
1668 .name = "Micrel KSZ8041",
1669
1670 .driver_data = &ksz8041_type,
1671 .probe = kszphy_probe,
1672 .config_init = ksz8041_config_init,
1673 .config_aneg = ksz8041_config_aneg,
1674 .config_intr = kszphy_config_intr,
1675 .handle_interrupt = kszphy_handle_interrupt,
1676 .get_sset_count = kszphy_get_sset_count,
1677 .get_strings = kszphy_get_strings,
1678 .get_stats = kszphy_get_stats,
1679
1680
1681
1682}, {
1683 .phy_id = PHY_ID_KSZ8041RNLI,
1684 .phy_id_mask = MICREL_PHY_ID_MASK,
1685 .name = "Micrel KSZ8041RNLI",
1686
1687 .driver_data = &ksz8041_type,
1688 .probe = kszphy_probe,
1689 .config_init = kszphy_config_init,
1690 .config_intr = kszphy_config_intr,
1691 .handle_interrupt = kszphy_handle_interrupt,
1692 .get_sset_count = kszphy_get_sset_count,
1693 .get_strings = kszphy_get_strings,
1694 .get_stats = kszphy_get_stats,
1695 .suspend = genphy_suspend,
1696 .resume = genphy_resume,
1697}, {
1698 .name = "Micrel KSZ8051",
1699
1700 .driver_data = &ksz8051_type,
1701 .probe = kszphy_probe,
1702 .config_init = kszphy_config_init,
1703 .config_intr = kszphy_config_intr,
1704 .handle_interrupt = kszphy_handle_interrupt,
1705 .get_sset_count = kszphy_get_sset_count,
1706 .get_strings = kszphy_get_strings,
1707 .get_stats = kszphy_get_stats,
1708 .match_phy_device = ksz8051_match_phy_device,
1709 .suspend = genphy_suspend,
1710 .resume = genphy_resume,
1711}, {
1712 .phy_id = PHY_ID_KSZ8001,
1713 .name = "Micrel KSZ8001 or KS8721",
1714 .phy_id_mask = 0x00fffffc,
1715
1716 .driver_data = &ksz8041_type,
1717 .probe = kszphy_probe,
1718 .config_init = kszphy_config_init,
1719 .config_intr = kszphy_config_intr,
1720 .handle_interrupt = kszphy_handle_interrupt,
1721 .get_sset_count = kszphy_get_sset_count,
1722 .get_strings = kszphy_get_strings,
1723 .get_stats = kszphy_get_stats,
1724 .suspend = genphy_suspend,
1725 .resume = genphy_resume,
1726}, {
1727 .phy_id = PHY_ID_KSZ8081,
1728 .name = "Micrel KSZ8081 or KSZ8091",
1729 .phy_id_mask = MICREL_PHY_ID_MASK,
1730 .flags = PHY_POLL_CABLE_TEST,
1731
1732 .driver_data = &ksz8081_type,
1733 .probe = kszphy_probe,
1734 .config_init = ksz8081_config_init,
1735 .soft_reset = genphy_soft_reset,
1736 .config_aneg = ksz8081_config_aneg,
1737 .read_status = ksz8081_read_status,
1738 .config_intr = kszphy_config_intr,
1739 .handle_interrupt = kszphy_handle_interrupt,
1740 .get_sset_count = kszphy_get_sset_count,
1741 .get_strings = kszphy_get_strings,
1742 .get_stats = kszphy_get_stats,
1743 .suspend = kszphy_suspend,
1744 .resume = kszphy_resume,
1745 .cable_test_start = ksz886x_cable_test_start,
1746 .cable_test_get_status = ksz886x_cable_test_get_status,
1747}, {
1748 .phy_id = PHY_ID_KSZ8061,
1749 .name = "Micrel KSZ8061",
1750 .phy_id_mask = MICREL_PHY_ID_MASK,
1751
1752 .config_init = ksz8061_config_init,
1753 .config_intr = kszphy_config_intr,
1754 .handle_interrupt = kszphy_handle_interrupt,
1755 .suspend = genphy_suspend,
1756 .resume = genphy_resume,
1757}, {
1758 .phy_id = PHY_ID_KSZ9021,
1759 .phy_id_mask = 0x000ffffe,
1760 .name = "Micrel KSZ9021 Gigabit PHY",
1761
1762 .driver_data = &ksz9021_type,
1763 .probe = kszphy_probe,
1764 .get_features = ksz9031_get_features,
1765 .config_init = ksz9021_config_init,
1766 .config_intr = kszphy_config_intr,
1767 .handle_interrupt = kszphy_handle_interrupt,
1768 .get_sset_count = kszphy_get_sset_count,
1769 .get_strings = kszphy_get_strings,
1770 .get_stats = kszphy_get_stats,
1771 .suspend = genphy_suspend,
1772 .resume = genphy_resume,
1773 .read_mmd = genphy_read_mmd_unsupported,
1774 .write_mmd = genphy_write_mmd_unsupported,
1775}, {
1776 .phy_id = PHY_ID_KSZ9031,
1777 .phy_id_mask = MICREL_PHY_ID_MASK,
1778 .name = "Micrel KSZ9031 Gigabit PHY",
1779 .driver_data = &ksz9021_type,
1780 .probe = kszphy_probe,
1781 .get_features = ksz9031_get_features,
1782 .config_init = ksz9031_config_init,
1783 .soft_reset = genphy_soft_reset,
1784 .read_status = ksz9031_read_status,
1785 .config_intr = kszphy_config_intr,
1786 .handle_interrupt = kszphy_handle_interrupt,
1787 .get_sset_count = kszphy_get_sset_count,
1788 .get_strings = kszphy_get_strings,
1789 .get_stats = kszphy_get_stats,
1790 .suspend = genphy_suspend,
1791 .resume = kszphy_resume,
1792}, {
1793 .phy_id = PHY_ID_LAN8814,
1794 .phy_id_mask = MICREL_PHY_ID_MASK,
1795 .name = "Microchip INDY Gigabit Quad PHY",
1796 .driver_data = &ksz9021_type,
1797 .probe = kszphy_probe,
1798 .soft_reset = genphy_soft_reset,
1799 .read_status = ksz9031_read_status,
1800 .get_sset_count = kszphy_get_sset_count,
1801 .get_strings = kszphy_get_strings,
1802 .get_stats = kszphy_get_stats,
1803 .suspend = genphy_suspend,
1804 .resume = kszphy_resume,
1805}, {
1806 .phy_id = PHY_ID_LAN8804,
1807 .phy_id_mask = MICREL_PHY_ID_MASK,
1808 .name = "Microchip LAN966X Gigabit PHY",
1809 .config_init = lan8804_config_init,
1810 .driver_data = &ksz9021_type,
1811 .probe = kszphy_probe,
1812 .soft_reset = genphy_soft_reset,
1813 .read_status = ksz9031_read_status,
1814 .get_sset_count = kszphy_get_sset_count,
1815 .get_strings = kszphy_get_strings,
1816 .get_stats = kszphy_get_stats,
1817 .suspend = genphy_suspend,
1818 .resume = kszphy_resume,
1819}, {
1820 .phy_id = PHY_ID_KSZ9131,
1821 .phy_id_mask = MICREL_PHY_ID_MASK,
1822 .name = "Microchip KSZ9131 Gigabit PHY",
1823
1824 .driver_data = &ksz9021_type,
1825 .probe = kszphy_probe,
1826 .config_init = ksz9131_config_init,
1827 .config_intr = kszphy_config_intr,
1828 .handle_interrupt = kszphy_handle_interrupt,
1829 .get_sset_count = kszphy_get_sset_count,
1830 .get_strings = kszphy_get_strings,
1831 .get_stats = kszphy_get_stats,
1832 .suspend = genphy_suspend,
1833 .resume = kszphy_resume,
1834}, {
1835 .phy_id = PHY_ID_KSZ8873MLL,
1836 .phy_id_mask = MICREL_PHY_ID_MASK,
1837 .name = "Micrel KSZ8873MLL Switch",
1838
1839 .config_init = kszphy_config_init,
1840 .config_aneg = ksz8873mll_config_aneg,
1841 .read_status = ksz8873mll_read_status,
1842 .suspend = genphy_suspend,
1843 .resume = genphy_resume,
1844}, {
1845 .phy_id = PHY_ID_KSZ886X,
1846 .phy_id_mask = MICREL_PHY_ID_MASK,
1847 .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
1848
1849 .flags = PHY_POLL_CABLE_TEST,
1850 .config_init = kszphy_config_init,
1851 .config_aneg = ksz886x_config_aneg,
1852 .read_status = ksz886x_read_status,
1853 .suspend = genphy_suspend,
1854 .resume = genphy_resume,
1855 .cable_test_start = ksz886x_cable_test_start,
1856 .cable_test_get_status = ksz886x_cable_test_get_status,
1857}, {
1858 .name = "Micrel KSZ87XX Switch",
1859
1860 .config_init = kszphy_config_init,
1861 .match_phy_device = ksz8795_match_phy_device,
1862 .suspend = genphy_suspend,
1863 .resume = genphy_resume,
1864}, {
1865 .phy_id = PHY_ID_KSZ9477,
1866 .phy_id_mask = MICREL_PHY_ID_MASK,
1867 .name = "Microchip KSZ9477",
1868
1869 .config_init = kszphy_config_init,
1870 .suspend = genphy_suspend,
1871 .resume = genphy_resume,
1872} };
1873
1874module_phy_driver(ksphy_driver);
1875
1876MODULE_DESCRIPTION("Micrel PHY driver");
1877MODULE_AUTHOR("David J. Choi");
1878MODULE_LICENSE("GPL");
1879
1880static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1881 { PHY_ID_KSZ9021, 0x000ffffe },
1882 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1883 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
1884 { PHY_ID_KSZ8001, 0x00fffffc },
1885 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1886 { PHY_ID_KSZ8021, 0x00ffffff },
1887 { PHY_ID_KSZ8031, 0x00ffffff },
1888 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1889 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1890 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1891 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1892 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1893 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1894 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
1895 { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
1896 { }
1897};
1898
1899MODULE_DEVICE_TABLE(mdio, micrel_tbl);
1900
