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6#ifndef DEBUG_HTT_STATS_H
7#define DEBUG_HTT_STATS_H
8
9#define HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0)
10#define HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32)
11#define HTT_STATS_MAGIC_VALUE 0xF0F0F0F0
12
13enum htt_tlv_tag_t {
14 HTT_STATS_TX_PDEV_CMN_TAG = 0,
15 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1,
16 HTT_STATS_TX_PDEV_SIFS_TAG = 2,
17 HTT_STATS_TX_PDEV_FLUSH_TAG = 3,
18 HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4,
19 HTT_STATS_STRING_TAG = 5,
20 HTT_STATS_TX_HWQ_CMN_TAG = 6,
21 HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7,
22 HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8,
23 HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9,
24 HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10,
25 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11,
26 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12,
27 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13,
28 HTT_STATS_TX_TQM_CMN_TAG = 14,
29 HTT_STATS_TX_TQM_PDEV_TAG = 15,
30 HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16,
31 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17,
32 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18,
33 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19,
34 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20,
35 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21,
36 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22,
37 HTT_STATS_TX_DE_CMN_TAG = 23,
38 HTT_STATS_RING_IF_TAG = 24,
39 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25,
40 HTT_STATS_SFM_CMN_TAG = 26,
41 HTT_STATS_SRING_STATS_TAG = 27,
42 HTT_STATS_RX_PDEV_FW_STATS_TAG = 28,
43 HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29,
44 HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30,
45 HTT_STATS_RX_SOC_FW_STATS_TAG = 31,
46 HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32,
47 HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33,
48 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34,
49 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35,
50 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36,
51 HTT_STATS_TX_SCHED_CMN_TAG = 37,
52 HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38,
53 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39,
54 HTT_STATS_RING_IF_CMN_TAG = 40,
55 HTT_STATS_SFM_CLIENT_USER_TAG = 41,
56 HTT_STATS_SFM_CLIENT_TAG = 42,
57 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43,
58 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44,
59 HTT_STATS_SRING_CMN_TAG = 45,
60 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46,
61 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47,
62 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48,
63 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49,
64 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50,
65 HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51,
66 HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52,
67 HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53,
68 HTT_STATS_HW_INTR_MISC_TAG = 54,
69 HTT_STATS_HW_WD_TIMEOUT_TAG = 55,
70 HTT_STATS_HW_PDEV_ERRS_TAG = 56,
71 HTT_STATS_COUNTER_NAME_TAG = 57,
72 HTT_STATS_TX_TID_DETAILS_TAG = 58,
73 HTT_STATS_RX_TID_DETAILS_TAG = 59,
74 HTT_STATS_PEER_STATS_CMN_TAG = 60,
75 HTT_STATS_PEER_DETAILS_TAG = 61,
76 HTT_STATS_PEER_TX_RATE_STATS_TAG = 62,
77 HTT_STATS_PEER_RX_RATE_STATS_TAG = 63,
78 HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64,
79 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65,
80 HTT_STATS_WHAL_TX_TAG = 66,
81 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67,
82 HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68,
83 HTT_STATS_TX_TID_DETAILS_V1_TAG = 69,
84 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70,
85 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71,
86 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72,
87 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73,
88 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74,
89 HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75,
90 HTT_STATS_PDEV_TWT_SESSION_TAG = 76,
91 HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77,
92 HTT_STATS_RX_REFILL_REO_ERR_TAG = 78,
93 HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79,
94 HTT_STATS_TX_SOUNDING_STATS_TAG = 80,
95 HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG = 81,
96 HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG = 82,
97 HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG = 83,
98 HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG = 84,
99 HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG = 85,
100 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86,
101 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87,
102 HTT_STATS_PDEV_OBSS_PD_TAG = 88,
103 HTT_STATS_HW_WAR_TAG = 89,
104 HTT_STATS_RING_BACKPRESSURE_STATS_TAG = 90,
105 HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG = 101,
106 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108,
107 HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG = 113,
108 HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG = 114,
109 HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG = 115,
110 HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116,
111 HTT_STATS_PHY_COUNTERS_TAG = 121,
112 HTT_STATS_PHY_STATS_TAG = 122,
113
114 HTT_STATS_MAX_TAG,
115};
116
117#define HTT_STATS_MAX_STRING_SZ32 4
118#define HTT_STATS_MACID_INVALID 0xff
119#define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10
120#define HTT_TX_HWQ_MAX_CMD_RESULT_STATS 13
121#define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5
122#define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10
123
124enum htt_tx_pdev_underrun_enum {
125 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0,
126 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1,
127 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2,
128 HTT_TX_PDEV_MAX_URRN_STATS = 3,
129};
130
131#define HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 71
132#define HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9
133#define HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10
134#define HTT_TX_PDEV_MAX_PHY_ERR_STATS 18
135#define HTT_TX_PDEV_SCHED_TX_MODE_MAX 4
136#define HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20
137
138#define HTT_RX_STATS_REFILL_MAX_RING 4
139#define HTT_RX_STATS_RXDMA_MAX_ERR 16
140#define HTT_RX_STATS_FW_DROP_REASON_MAX 16
141
142
143
144struct htt_stats_string_tlv {
145 u32 data[0];
146} __packed;
147
148#define HTT_STATS_MAC_ID GENMASK(7, 0)
149
150
151struct htt_tx_pdev_stats_cmn_tlv {
152 u32 mac_id__word;
153 u32 hw_queued;
154 u32 hw_reaped;
155 u32 underrun;
156 u32 hw_paused;
157 u32 hw_flush;
158 u32 hw_filt;
159 u32 tx_abort;
160 u32 mpdu_requeued;
161 u32 tx_xretry;
162 u32 data_rc;
163 u32 mpdu_dropped_xretry;
164 u32 illgl_rate_phy_err;
165 u32 cont_xretry;
166 u32 tx_timeout;
167 u32 pdev_resets;
168 u32 phy_underrun;
169 u32 txop_ovf;
170 u32 seq_posted;
171 u32 seq_failed_queueing;
172 u32 seq_completed;
173 u32 seq_restarted;
174 u32 mu_seq_posted;
175 u32 seq_switch_hw_paused;
176 u32 next_seq_posted_dsr;
177 u32 seq_posted_isr;
178 u32 seq_ctrl_cached;
179 u32 mpdu_count_tqm;
180 u32 msdu_count_tqm;
181 u32 mpdu_removed_tqm;
182 u32 msdu_removed_tqm;
183 u32 mpdus_sw_flush;
184 u32 mpdus_hw_filter;
185 u32 mpdus_truncated;
186 u32 mpdus_ack_failed;
187 u32 mpdus_expired;
188 u32 mpdus_seq_hw_retry;
189 u32 ack_tlv_proc;
190 u32 coex_abort_mpdu_cnt_valid;
191 u32 coex_abort_mpdu_cnt;
192 u32 num_total_ppdus_tried_ota;
193 u32 num_data_ppdus_tried_ota;
194 u32 local_ctrl_mgmt_enqued;
195 u32 local_ctrl_mgmt_freed;
196 u32 local_data_enqued;
197 u32 local_data_freed;
198 u32 mpdu_tried;
199 u32 isr_wait_seq_posted;
200
201 u32 tx_active_dur_us_low;
202 u32 tx_active_dur_us_high;
203};
204
205
206struct htt_tx_pdev_stats_urrn_tlv_v {
207 u32 urrn_stats[0];
208};
209
210
211struct htt_tx_pdev_stats_flush_tlv_v {
212 u32 flush_errs[0];
213};
214
215
216struct htt_tx_pdev_stats_sifs_tlv_v {
217 u32 sifs_status[0];
218};
219
220
221struct htt_tx_pdev_stats_phy_err_tlv_v {
222 u32 phy_errs[0];
223};
224
225
226struct htt_tx_pdev_stats_sifs_hist_tlv_v {
227 u32 sifs_hist_status[0];
228};
229
230struct htt_tx_pdev_stats_tx_ppdu_stats_tlv_v {
231 u32 num_data_ppdus_legacy_su;
232 u32 num_data_ppdus_ac_su;
233 u32 num_data_ppdus_ax_su;
234 u32 num_data_ppdus_ac_su_txbf;
235 u32 num_data_ppdus_ax_su_txbf;
236};
237
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246
247
248
249
250struct htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v {
251 u32 hist_bin_size;
252 u32 tried_mpdu_cnt_hist[];
253};
254
255
256
257
258#define HTT_STATS_MAX_HW_INTR_NAME_LEN 8
259struct htt_hw_stats_intr_misc_tlv {
260
261 u8 hw_intr_name[HTT_STATS_MAX_HW_INTR_NAME_LEN];
262 u32 mask;
263 u32 count;
264};
265
266#define HTT_STATS_MAX_HW_MODULE_NAME_LEN 8
267struct htt_hw_stats_wd_timeout_tlv {
268
269 u8 hw_module_name[HTT_STATS_MAX_HW_MODULE_NAME_LEN];
270 u32 count;
271};
272
273struct htt_hw_stats_pdev_errs_tlv {
274 u32 mac_id__word;
275 u32 tx_abort;
276 u32 tx_abort_fail_count;
277 u32 rx_abort;
278 u32 rx_abort_fail_count;
279 u32 warm_reset;
280 u32 cold_reset;
281 u32 tx_flush;
282 u32 tx_glb_reset;
283 u32 tx_txq_reset;
284 u32 rx_timeout_reset;
285};
286
287struct htt_hw_stats_whal_tx_tlv {
288 u32 mac_id__word;
289 u32 last_unpause_ppdu_id;
290 u32 hwsch_unpause_wait_tqm_write;
291 u32 hwsch_dummy_tlv_skipped;
292 u32 hwsch_misaligned_offset_received;
293 u32 hwsch_reset_count;
294 u32 hwsch_dev_reset_war;
295 u32 hwsch_delayed_pause;
296 u32 hwsch_long_delayed_pause;
297 u32 sch_rx_ppdu_no_response;
298 u32 sch_selfgen_response;
299 u32 sch_rx_sifs_resp_trigger;
300};
301
302
303#define HTT_MSDU_FLOW_STATS_TX_FLOW_NO GENMASK(15, 0)
304#define HTT_MSDU_FLOW_STATS_TID_NUM GENMASK(19, 16)
305#define HTT_MSDU_FLOW_STATS_DROP_RULE BIT(20)
306
307struct htt_msdu_flow_stats_tlv {
308 u32 last_update_timestamp;
309 u32 last_add_timestamp;
310 u32 last_remove_timestamp;
311 u32 total_processed_msdu_count;
312 u32 cur_msdu_count_in_flowq;
313 u32 sw_peer_id;
314 u32 tx_flow_no__tid_num__drop_rule;
315 u32 last_cycle_enqueue_count;
316 u32 last_cycle_dequeue_count;
317 u32 last_cycle_drop_count;
318 u32 current_drop_th;
319};
320
321#define MAX_HTT_TID_NAME 8
322
323#define HTT_TX_TID_STATS_SW_PEER_ID GENMASK(15, 0)
324#define HTT_TX_TID_STATS_TID_NUM GENMASK(31, 16)
325#define HTT_TX_TID_STATS_NUM_SCHED_PENDING GENMASK(7, 0)
326#define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ GENMASK(15, 8)
327
328
329struct htt_tx_tid_stats_tlv {
330
331 u8 tid_name[MAX_HTT_TID_NAME];
332 u32 sw_peer_id__tid_num;
333 u32 num_sched_pending__num_ppdu_in_hwq;
334 u32 tid_flags;
335 u32 hw_queued;
336 u32 hw_reaped;
337 u32 mpdus_hw_filter;
338
339 u32 qdepth_bytes;
340 u32 qdepth_num_msdu;
341 u32 qdepth_num_mpdu;
342 u32 last_scheduled_tsmp;
343 u32 pause_module_id;
344 u32 block_module_id;
345 u32 tid_tx_airtime;
346};
347
348#define HTT_TX_TID_STATS_V1_SW_PEER_ID GENMASK(15, 0)
349#define HTT_TX_TID_STATS_V1_TID_NUM GENMASK(31, 16)
350#define HTT_TX_TID_STATS_V1_NUM_SCHED_PENDING GENMASK(7, 0)
351#define HTT_TX_TID_STATS_V1_NUM_PPDU_IN_HWQ GENMASK(15, 8)
352
353
354struct htt_tx_tid_stats_v1_tlv {
355
356 u8 tid_name[MAX_HTT_TID_NAME];
357 u32 sw_peer_id__tid_num;
358 u32 num_sched_pending__num_ppdu_in_hwq;
359 u32 tid_flags;
360 u32 max_qdepth_bytes;
361 u32 max_qdepth_n_msdus;
362 u32 rsvd;
363
364 u32 qdepth_bytes;
365 u32 qdepth_num_msdu;
366 u32 qdepth_num_mpdu;
367 u32 last_scheduled_tsmp;
368 u32 pause_module_id;
369 u32 block_module_id;
370 u32 tid_tx_airtime;
371 u32 allow_n_flags;
372 u32 sendn_frms_allowed;
373};
374
375#define HTT_RX_TID_STATS_SW_PEER_ID GENMASK(15, 0)
376#define HTT_RX_TID_STATS_TID_NUM GENMASK(31, 16)
377
378struct htt_rx_tid_stats_tlv {
379 u32 sw_peer_id__tid_num;
380 u8 tid_name[MAX_HTT_TID_NAME];
381 u32 dup_in_reorder;
382 u32 dup_past_outside_window;
383 u32 dup_past_within_window;
384 u32 rxdesc_err_decrypt;
385 u32 tid_rx_airtime;
386};
387
388#define HTT_MAX_COUNTER_NAME 8
389struct htt_counter_tlv {
390 u8 counter_name[HTT_MAX_COUNTER_NAME];
391 u32 count;
392};
393
394struct htt_peer_stats_cmn_tlv {
395 u32 ppdu_cnt;
396 u32 mpdu_cnt;
397 u32 msdu_cnt;
398 u32 pause_bitmap;
399 u32 block_bitmap;
400 u32 current_timestamp;
401 u32 peer_tx_airtime;
402 u32 peer_rx_airtime;
403 s32 rssi;
404 u32 peer_enqueued_count_low;
405 u32 peer_enqueued_count_high;
406 u32 peer_dequeued_count_low;
407 u32 peer_dequeued_count_high;
408 u32 peer_dropped_count_low;
409 u32 peer_dropped_count_high;
410 u32 ppdu_transmitted_bytes_low;
411 u32 ppdu_transmitted_bytes_high;
412 u32 peer_ttl_removed_count;
413 u32 inactive_time;
414};
415
416#define HTT_PEER_DETAILS_VDEV_ID GENMASK(7, 0)
417#define HTT_PEER_DETAILS_PDEV_ID GENMASK(15, 8)
418#define HTT_PEER_DETAILS_AST_IDX GENMASK(31, 16)
419
420struct htt_peer_details_tlv {
421 u32 peer_type;
422 u32 sw_peer_id;
423 u32 vdev_pdev_ast_idx;
424 struct htt_mac_addr mac_addr;
425 u32 peer_flags;
426 u32 qpeer_flags;
427};
428
429enum htt_stats_param_type {
430 HTT_STATS_PREAM_OFDM,
431 HTT_STATS_PREAM_CCK,
432 HTT_STATS_PREAM_HT,
433 HTT_STATS_PREAM_VHT,
434 HTT_STATS_PREAM_HE,
435 HTT_STATS_PREAM_RSVD,
436 HTT_STATS_PREAM_RSVD1,
437
438 HTT_STATS_PREAM_COUNT,
439};
440
441#define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12
442#define HTT_TX_PEER_STATS_NUM_GI_COUNTERS 4
443#define HTT_TX_PEER_STATS_NUM_DCM_COUNTERS 5
444#define HTT_TX_PEER_STATS_NUM_BW_COUNTERS 4
445#define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8
446#define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
447
448struct htt_tx_peer_rate_stats_tlv {
449 u32 tx_ldpc;
450 u32 rts_cnt;
451 u32 ack_rssi;
452
453 u32 tx_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
454 u32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
455 u32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
456
457 u32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS];
458
459 u32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS];
460 u32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
461 u32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES];
462
463
464
465
466 u32 tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
467
468
469 u32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS];
470
471};
472
473#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12
474#define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4
475#define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5
476#define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4
477#define HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS 8
478#define HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
479
480struct htt_rx_peer_rate_stats_tlv {
481 u32 nsts;
482
483
484 u32 rx_ldpc;
485
486 u32 rts_cnt;
487
488 u32 rssi_mgmt;
489 u32 rssi_data;
490 u32 rssi_comb;
491 u32 rx_mcs[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS];
492
493 u32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS];
494 u32 rx_dcm[HTT_RX_PEER_STATS_NUM_DCM_COUNTERS];
495 u32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS];
496
497 u32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS];
498 u32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES];
499
500 u8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]
501 [HTT_RX_PEER_STATS_NUM_BW_COUNTERS];
502
503
504 u32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS]
505 [HTT_RX_PEER_STATS_NUM_MCS_COUNTERS];
506};
507
508enum htt_peer_stats_req_mode {
509 HTT_PEER_STATS_REQ_MODE_NO_QUERY,
510 HTT_PEER_STATS_REQ_MODE_QUERY_TQM,
511 HTT_PEER_STATS_REQ_MODE_FLUSH_TQM,
512};
513
514enum htt_peer_stats_tlv_enum {
515 HTT_PEER_STATS_CMN_TLV = 0,
516 HTT_PEER_DETAILS_TLV = 1,
517 HTT_TX_PEER_RATE_STATS_TLV = 2,
518 HTT_RX_PEER_RATE_STATS_TLV = 3,
519 HTT_TX_TID_STATS_TLV = 4,
520 HTT_RX_TID_STATS_TLV = 5,
521 HTT_MSDU_FLOW_STATS_TLV = 6,
522
523 HTT_PEER_STATS_MAX_TLV = 31,
524};
525
526
527
528struct htt_tx_hwq_mu_mimo_sch_stats_tlv {
529 u32 mu_mimo_sch_posted;
530 u32 mu_mimo_sch_failed;
531 u32 mu_mimo_ppdu_posted;
532};
533
534struct htt_tx_hwq_mu_mimo_mpdu_stats_tlv {
535 u32 mu_mimo_mpdus_queued_usr;
536 u32 mu_mimo_mpdus_tried_usr;
537 u32 mu_mimo_mpdus_failed_usr;
538 u32 mu_mimo_mpdus_requeued_usr;
539 u32 mu_mimo_err_no_ba_usr;
540 u32 mu_mimo_mpdu_underrun_usr;
541 u32 mu_mimo_ampdu_underrun_usr;
542};
543
544#define HTT_TX_HWQ_STATS_MAC_ID GENMASK(7, 0)
545#define HTT_TX_HWQ_STATS_HWQ_ID GENMASK(15, 8)
546
547struct htt_tx_hwq_mu_mimo_cmn_stats_tlv {
548 u32 mac_id__hwq_id__word;
549};
550
551
552struct htt_tx_hwq_stats_cmn_tlv {
553 u32 mac_id__hwq_id__word;
554
555
556 u32 xretry;
557 u32 underrun_cnt;
558 u32 flush_cnt;
559 u32 filt_cnt;
560 u32 null_mpdu_bmap;
561 u32 user_ack_failure;
562 u32 ack_tlv_proc;
563 u32 sched_id_proc;
564 u32 null_mpdu_tx_count;
565 u32 mpdu_bmap_not_recvd;
566
567
568 u32 num_bar;
569 u32 rts;
570 u32 cts2self;
571 u32 qos_null;
572
573
574 u32 mpdu_tried_cnt;
575 u32 mpdu_queued_cnt;
576 u32 mpdu_ack_fail_cnt;
577 u32 mpdu_filt_cnt;
578 u32 false_mpdu_ack_count;
579
580 u32 txq_timeout;
581};
582
583
584struct htt_tx_hwq_difs_latency_stats_tlv_v {
585 u32 hist_intvl;
586
587 u32 difs_latency_hist[];
588};
589
590
591struct htt_tx_hwq_cmd_result_stats_tlv_v {
592
593 u32 cmd_result[0];
594};
595
596
597struct htt_tx_hwq_cmd_stall_stats_tlv_v {
598
599 u32 cmd_stall_status[0];
600};
601
602
603struct htt_tx_hwq_fes_result_stats_tlv_v {
604
605 u32 fes_result[0];
606};
607
608
609
610
611
612
613
614
615
616
617
618
619
620struct htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v {
621 u32 hist_bin_size;
622
623 u32 tried_mpdu_cnt_hist[];
624};
625
626
627
628
629
630
631
632
633
634
635
636struct htt_tx_hwq_txop_used_cnt_hist_tlv_v {
637
638 u32 txop_used_cnt_hist[0];
639};
640
641
642struct htt_tx_selfgen_cmn_stats_tlv {
643 u32 mac_id__word;
644 u32 su_bar;
645 u32 rts;
646 u32 cts2self;
647 u32 qos_null;
648 u32 delayed_bar_1;
649 u32 delayed_bar_2;
650 u32 delayed_bar_3;
651 u32 delayed_bar_4;
652 u32 delayed_bar_5;
653 u32 delayed_bar_6;
654 u32 delayed_bar_7;
655};
656
657struct htt_tx_selfgen_ac_stats_tlv {
658
659 u32 ac_su_ndpa;
660 u32 ac_su_ndp;
661 u32 ac_mu_mimo_ndpa;
662 u32 ac_mu_mimo_ndp;
663 u32 ac_mu_mimo_brpoll_1;
664 u32 ac_mu_mimo_brpoll_2;
665 u32 ac_mu_mimo_brpoll_3;
666};
667
668struct htt_tx_selfgen_ax_stats_tlv {
669
670 u32 ax_su_ndpa;
671 u32 ax_su_ndp;
672 u32 ax_mu_mimo_ndpa;
673 u32 ax_mu_mimo_ndp;
674 u32 ax_mu_mimo_brpoll_1;
675 u32 ax_mu_mimo_brpoll_2;
676 u32 ax_mu_mimo_brpoll_3;
677 u32 ax_mu_mimo_brpoll_4;
678 u32 ax_mu_mimo_brpoll_5;
679 u32 ax_mu_mimo_brpoll_6;
680 u32 ax_mu_mimo_brpoll_7;
681 u32 ax_basic_trigger;
682 u32 ax_bsr_trigger;
683 u32 ax_mu_bar_trigger;
684 u32 ax_mu_rts_trigger;
685};
686
687struct htt_tx_selfgen_ac_err_stats_tlv {
688
689 u32 ac_su_ndp_err;
690 u32 ac_su_ndpa_err;
691 u32 ac_mu_mimo_ndpa_err;
692 u32 ac_mu_mimo_ndp_err;
693 u32 ac_mu_mimo_brp1_err;
694 u32 ac_mu_mimo_brp2_err;
695 u32 ac_mu_mimo_brp3_err;
696};
697
698struct htt_tx_selfgen_ax_err_stats_tlv {
699
700 u32 ax_su_ndp_err;
701 u32 ax_su_ndpa_err;
702 u32 ax_mu_mimo_ndpa_err;
703 u32 ax_mu_mimo_ndp_err;
704 u32 ax_mu_mimo_brp1_err;
705 u32 ax_mu_mimo_brp2_err;
706 u32 ax_mu_mimo_brp3_err;
707 u32 ax_mu_mimo_brp4_err;
708 u32 ax_mu_mimo_brp5_err;
709 u32 ax_mu_mimo_brp6_err;
710 u32 ax_mu_mimo_brp7_err;
711 u32 ax_basic_trigger_err;
712 u32 ax_bsr_trigger_err;
713 u32 ax_mu_bar_trigger_err;
714 u32 ax_mu_rts_trigger_err;
715};
716
717
718#define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4
719#define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8
720#define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74
721
722struct htt_tx_pdev_mu_mimo_sch_stats_tlv {
723
724 u32 mu_mimo_sch_posted;
725 u32 mu_mimo_sch_failed;
726
727 u32 mu_mimo_ppdu_posted;
728
729
730
731
732
733
734 u32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS];
735 u32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS];
736 u32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
737};
738
739struct htt_tx_pdev_mu_mimo_mpdu_stats_tlv {
740 u32 mu_mimo_mpdus_queued_usr;
741 u32 mu_mimo_mpdus_tried_usr;
742 u32 mu_mimo_mpdus_failed_usr;
743 u32 mu_mimo_mpdus_requeued_usr;
744 u32 mu_mimo_err_no_ba_usr;
745 u32 mu_mimo_mpdu_underrun_usr;
746 u32 mu_mimo_ampdu_underrun_usr;
747
748 u32 ax_mu_mimo_mpdus_queued_usr;
749 u32 ax_mu_mimo_mpdus_tried_usr;
750 u32 ax_mu_mimo_mpdus_failed_usr;
751 u32 ax_mu_mimo_mpdus_requeued_usr;
752 u32 ax_mu_mimo_err_no_ba_usr;
753 u32 ax_mu_mimo_mpdu_underrun_usr;
754 u32 ax_mu_mimo_ampdu_underrun_usr;
755
756 u32 ax_ofdma_mpdus_queued_usr;
757 u32 ax_ofdma_mpdus_tried_usr;
758 u32 ax_ofdma_mpdus_failed_usr;
759 u32 ax_ofdma_mpdus_requeued_usr;
760 u32 ax_ofdma_err_no_ba_usr;
761 u32 ax_ofdma_mpdu_underrun_usr;
762 u32 ax_ofdma_ampdu_underrun_usr;
763};
764
765#define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC 1
766#define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX 2
767#define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3
768
769struct htt_tx_pdev_mpdu_stats_tlv {
770
771 u32 mpdus_queued_usr;
772 u32 mpdus_tried_usr;
773 u32 mpdus_failed_usr;
774 u32 mpdus_requeued_usr;
775 u32 err_no_ba_usr;
776 u32 mpdu_underrun_usr;
777 u32 ampdu_underrun_usr;
778 u32 user_index;
779 u32 tx_sched_mode;
780};
781
782
783
784struct htt_sched_txq_cmd_posted_tlv_v {
785 u32 sched_cmd_posted[0];
786};
787
788
789struct htt_sched_txq_cmd_reaped_tlv_v {
790 u32 sched_cmd_reaped[0];
791};
792
793
794struct htt_sched_txq_sched_order_su_tlv_v {
795 u32 sched_order_su[0];
796};
797
798enum htt_sched_txq_sched_ineligibility_tlv_enum {
799 HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0,
800 HTT_SCHED_TID_SKIP_NOTIFY_MPDU,
801 HTT_SCHED_TID_SKIP_MPDU_STATE_INVALID,
802 HTT_SCHED_TID_SKIP_SCHED_DISABLED,
803 HTT_SCHED_TID_SKIP_TQM_BYPASS_CMD_PENDING,
804 HTT_SCHED_TID_SKIP_SECOND_SU_SCHEDULE,
805
806 HTT_SCHED_TID_SKIP_CMD_SLOT_NOT_AVAIL,
807 HTT_SCHED_TID_SKIP_NO_ENQ,
808 HTT_SCHED_TID_SKIP_LOW_ENQ,
809 HTT_SCHED_TID_SKIP_PAUSED,
810 HTT_SCHED_TID_SKIP_UL,
811 HTT_SCHED_TID_REMOVE_PAUSED,
812 HTT_SCHED_TID_REMOVE_NO_ENQ,
813 HTT_SCHED_TID_REMOVE_UL,
814 HTT_SCHED_TID_QUERY,
815 HTT_SCHED_TID_SU_ONLY,
816 HTT_SCHED_TID_ELIGIBLE,
817 HTT_SCHED_INELIGIBILITY_MAX,
818};
819
820
821struct htt_sched_txq_sched_ineligibility_tlv_v {
822
823 u32 sched_ineligibility[0];
824};
825
826#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0)
827#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8)
828
829struct htt_tx_pdev_stats_sched_per_txq_tlv {
830 u32 mac_id__txq_id__word;
831 u32 sched_policy;
832 u32 last_sched_cmd_posted_timestamp;
833 u32 last_sched_cmd_compl_timestamp;
834 u32 sched_2_tac_lwm_count;
835 u32 sched_2_tac_ring_full;
836 u32 sched_cmd_post_failure;
837 u32 num_active_tids;
838 u32 num_ps_schedules;
839 u32 sched_cmds_pending;
840 u32 num_tid_register;
841 u32 num_tid_unregister;
842 u32 num_qstats_queried;
843 u32 qstats_update_pending;
844 u32 last_qstats_query_timestamp;
845 u32 num_tqm_cmdq_full;
846 u32 num_de_sched_algo_trigger;
847 u32 num_rt_sched_algo_trigger;
848 u32 num_tqm_sched_algo_trigger;
849 u32 notify_sched;
850 u32 dur_based_sendn_term;
851};
852
853struct htt_stats_tx_sched_cmn_tlv {
854
855
856
857 u32 mac_id__word;
858
859 u32 current_timestamp;
860};
861
862
863#define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 16
864#define HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16
865#define HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16
866
867
868struct htt_tx_tqm_gen_mpdu_stats_tlv_v {
869 u32 gen_mpdu_end_reason[0];
870};
871
872
873struct htt_tx_tqm_list_mpdu_stats_tlv_v {
874 u32 list_mpdu_end_reason[0];
875};
876
877
878struct htt_tx_tqm_list_mpdu_cnt_tlv_v {
879 u32 list_mpdu_cnt_hist[0];
880
881};
882
883struct htt_tx_tqm_pdev_stats_tlv_v {
884 u32 msdu_count;
885 u32 mpdu_count;
886 u32 remove_msdu;
887 u32 remove_mpdu;
888 u32 remove_msdu_ttl;
889 u32 send_bar;
890 u32 bar_sync;
891 u32 notify_mpdu;
892 u32 sync_cmd;
893 u32 write_cmd;
894 u32 hwsch_trigger;
895 u32 ack_tlv_proc;
896 u32 gen_mpdu_cmd;
897 u32 gen_list_cmd;
898 u32 remove_mpdu_cmd;
899 u32 remove_mpdu_tried_cmd;
900 u32 mpdu_queue_stats_cmd;
901 u32 mpdu_head_info_cmd;
902 u32 msdu_flow_stats_cmd;
903 u32 remove_msdu_cmd;
904 u32 remove_msdu_ttl_cmd;
905 u32 flush_cache_cmd;
906 u32 update_mpduq_cmd;
907 u32 enqueue;
908 u32 enqueue_notify;
909 u32 notify_mpdu_at_head;
910 u32 notify_mpdu_state_valid;
911
912
913
914
915
916
917
918
919
920
921
922
923 u32 sched_udp_notify1;
924 u32 sched_udp_notify2;
925 u32 sched_nonudp_notify1;
926 u32 sched_nonudp_notify2;
927};
928
929struct htt_tx_tqm_cmn_stats_tlv {
930 u32 mac_id__word;
931 u32 max_cmdq_id;
932 u32 list_mpdu_cnt_hist_intvl;
933
934
935 u32 add_msdu;
936 u32 q_empty;
937 u32 q_not_empty;
938 u32 drop_notification;
939 u32 desc_threshold;
940};
941
942struct htt_tx_tqm_error_stats_tlv {
943
944 u32 q_empty_failure;
945 u32 q_not_empty_failure;
946 u32 add_msdu_failure;
947};
948
949
950#define HTT_TX_TQM_CMDQ_STATUS_MAC_ID GENMASK(7, 0)
951#define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID GENMASK(15, 8)
952
953struct htt_tx_tqm_cmdq_status_tlv {
954 u32 mac_id__cmdq_id__word;
955 u32 sync_cmd;
956 u32 write_cmd;
957 u32 gen_mpdu_cmd;
958 u32 mpdu_queue_stats_cmd;
959 u32 mpdu_head_info_cmd;
960 u32 msdu_flow_stats_cmd;
961 u32 remove_mpdu_cmd;
962 u32 remove_msdu_cmd;
963 u32 flush_cache_cmd;
964 u32 update_mpduq_cmd;
965 u32 update_msduq_cmd;
966};
967
968
969
970struct htt_tx_de_eapol_packets_stats_tlv {
971 u32 m1_packets;
972 u32 m2_packets;
973 u32 m3_packets;
974 u32 m4_packets;
975 u32 g1_packets;
976 u32 g2_packets;
977};
978
979struct htt_tx_de_classify_failed_stats_tlv {
980 u32 ap_bss_peer_not_found;
981 u32 ap_bcast_mcast_no_peer;
982 u32 sta_delete_in_progress;
983 u32 ibss_no_bss_peer;
984 u32 invalid_vdev_type;
985 u32 invalid_ast_peer_entry;
986 u32 peer_entry_invalid;
987 u32 ethertype_not_ip;
988 u32 eapol_lookup_failed;
989 u32 qpeer_not_allow_data;
990 u32 fse_tid_override;
991 u32 ipv6_jumbogram_zero_length;
992 u32 qos_to_non_qos_in_prog;
993};
994
995struct htt_tx_de_classify_stats_tlv {
996 u32 arp_packets;
997 u32 igmp_packets;
998 u32 dhcp_packets;
999 u32 host_inspected;
1000 u32 htt_included;
1001 u32 htt_valid_mcs;
1002 u32 htt_valid_nss;
1003 u32 htt_valid_preamble_type;
1004 u32 htt_valid_chainmask;
1005 u32 htt_valid_guard_interval;
1006 u32 htt_valid_retries;
1007 u32 htt_valid_bw_info;
1008 u32 htt_valid_power;
1009 u32 htt_valid_key_flags;
1010 u32 htt_valid_no_encryption;
1011 u32 fse_entry_count;
1012 u32 fse_priority_be;
1013 u32 fse_priority_high;
1014 u32 fse_priority_low;
1015 u32 fse_traffic_ptrn_be;
1016 u32 fse_traffic_ptrn_over_sub;
1017 u32 fse_traffic_ptrn_bursty;
1018 u32 fse_traffic_ptrn_interactive;
1019 u32 fse_traffic_ptrn_periodic;
1020 u32 fse_hwqueue_alloc;
1021 u32 fse_hwqueue_created;
1022 u32 fse_hwqueue_send_to_host;
1023 u32 mcast_entry;
1024 u32 bcast_entry;
1025 u32 htt_update_peer_cache;
1026 u32 htt_learning_frame;
1027 u32 fse_invalid_peer;
1028
1029
1030
1031
1032
1033 u32 mec_notify;
1034};
1035
1036struct htt_tx_de_classify_status_stats_tlv {
1037 u32 eok;
1038 u32 classify_done;
1039 u32 lookup_failed;
1040 u32 send_host_dhcp;
1041 u32 send_host_mcast;
1042 u32 send_host_unknown_dest;
1043 u32 send_host;
1044 u32 status_invalid;
1045};
1046
1047struct htt_tx_de_enqueue_packets_stats_tlv {
1048 u32 enqueued_pkts;
1049 u32 to_tqm;
1050 u32 to_tqm_bypass;
1051};
1052
1053struct htt_tx_de_enqueue_discard_stats_tlv {
1054 u32 discarded_pkts;
1055 u32 local_frames;
1056 u32 is_ext_msdu;
1057};
1058
1059struct htt_tx_de_compl_stats_tlv {
1060 u32 tcl_dummy_frame;
1061 u32 tqm_dummy_frame;
1062 u32 tqm_notify_frame;
1063 u32 fw2wbm_enq;
1064 u32 tqm_bypass_frame;
1065};
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078struct htt_tx_de_fw2wbm_ring_full_hist_tlv {
1079 u32 fw2wbm_ring_full_hist[0];
1080};
1081
1082struct htt_tx_de_cmn_stats_tlv {
1083 u32 mac_id__word;
1084
1085
1086 u32 tcl2fw_entry_count;
1087 u32 not_to_fw;
1088 u32 invalid_pdev_vdev_peer;
1089 u32 tcl_res_invalid_addrx;
1090 u32 wbm2fw_entry_count;
1091 u32 invalid_pdev;
1092};
1093
1094
1095#define HTT_STATS_LOW_WM_BINS 5
1096#define HTT_STATS_HIGH_WM_BINS 5
1097
1098#define HTT_RING_IF_STATS_NUM_ELEMS GENMASK(15, 0)
1099#define HTT_RING_IF_STATS_PREFETCH_TAIL_INDEX GENMASK(31, 16)
1100#define HTT_RING_IF_STATS_HEAD_IDX GENMASK(15, 0)
1101#define HTT_RING_IF_STATS_TAIL_IDX GENMASK(31, 16)
1102#define HTT_RING_IF_STATS_SHADOW_HEAD_IDX GENMASK(15, 0)
1103#define HTT_RING_IF_STATS_SHADOW_TAIL_IDX GENMASK(31, 16)
1104#define HTT_RING_IF_STATS_LWM_THRESH GENMASK(15, 0)
1105#define HTT_RING_IF_STATS_HWM_THRESH GENMASK(31, 16)
1106
1107struct htt_ring_if_stats_tlv {
1108 u32 base_addr;
1109 u32 elem_size;
1110 u32 num_elems__prefetch_tail_idx;
1111 u32 head_idx__tail_idx;
1112 u32 shadow_head_idx__shadow_tail_idx;
1113 u32 num_tail_incr;
1114 u32 lwm_thresh__hwm_thresh;
1115 u32 overrun_hit_count;
1116 u32 underrun_hit_count;
1117 u32 prod_blockwait_count;
1118 u32 cons_blockwait_count;
1119 u32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS];
1120 u32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS];
1121};
1122
1123struct htt_ring_if_cmn_tlv {
1124 u32 mac_id__word;
1125 u32 num_records;
1126};
1127
1128
1129
1130struct htt_sfm_client_user_tlv_v {
1131
1132 u32 dwords_used_by_user_n[0];
1133};
1134
1135struct htt_sfm_client_tlv {
1136
1137 u32 client_id;
1138
1139 u32 buf_min;
1140
1141 u32 buf_max;
1142
1143 u32 buf_busy;
1144
1145 u32 buf_alloc;
1146
1147 u32 buf_avail;
1148
1149 u32 num_users;
1150};
1151
1152struct htt_sfm_cmn_tlv {
1153 u32 mac_id__word;
1154
1155
1156
1157 u32 buf_total;
1158
1159
1160
1161 u32 mem_empty;
1162
1163 u32 deallocate_bufs;
1164
1165 u32 num_records;
1166};
1167
1168
1169#define HTT_SRING_STATS_MAC_ID GENMASK(7, 0)
1170#define HTT_SRING_STATS_RING_ID GENMASK(15, 8)
1171#define HTT_SRING_STATS_ARENA GENMASK(23, 16)
1172#define HTT_SRING_STATS_EP BIT(24)
1173#define HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0)
1174#define HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16)
1175#define HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0)
1176#define HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16)
1177#define HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0)
1178#define HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16)
1179#define HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0)
1180#define HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16)
1181
1182struct htt_sring_stats_tlv {
1183 u32 mac_id__ring_id__arena__ep;
1184 u32 base_addr_lsb;
1185 u32 base_addr_msb;
1186 u32 ring_size;
1187 u32 elem_size;
1188
1189 u32 num_avail_words__num_valid_words;
1190 u32 head_ptr__tail_ptr;
1191 u32 consumer_empty__producer_full;
1192 u32 prefetch_count__internal_tail_ptr;
1193};
1194
1195struct htt_sring_cmn_tlv {
1196 u32 num_records;
1197};
1198
1199
1200#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12
1201#define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4
1202#define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5
1203#define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4
1204#define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
1205#define HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
1206#define HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4
1207#define HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8
1208#define HTT_TX_PDEV_STATS_NUM_LTF 4
1209
1210#define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \
1211 (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \
1212 HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS)
1213
1214struct htt_tx_pdev_rate_stats_tlv {
1215 u32 mac_id__word;
1216 u32 tx_ldpc;
1217 u32 rts_cnt;
1218
1219 u32 ack_rssi;
1220
1221 u32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1222
1223 u32 tx_su_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1224 u32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1225
1226
1227 u32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1228
1229 u32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1230 u32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1231 u32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES];
1232
1233
1234
1235
1236 u32 tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1237
1238
1239 u32 tx_dcm[HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS];
1240
1241 u32 rts_success;
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253 u32 tx_legacy_cck_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS];
1254 u32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
1255
1256 u32 ac_mu_mimo_tx_ldpc;
1257 u32 ax_mu_mimo_tx_ldpc;
1258 u32 ofdma_tx_ldpc;
1259
1260
1261
1262
1263
1264
1265
1266
1267 u32 tx_he_ltf[HTT_TX_PDEV_STATS_NUM_LTF];
1268
1269 u32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1270 u32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1271 u32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1272
1273 u32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1274 u32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1275 u32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1276
1277 u32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1278 u32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1279 u32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1280
1281 u32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1282 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1283 u32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1284 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1285 u32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1286 [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
1287};
1288
1289
1290#define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4
1291#define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8
1292#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12
1293#define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4
1294#define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5
1295#define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4
1296#define HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
1297#define HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
1298#define HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8
1299#define HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS 16
1300
1301struct htt_rx_pdev_rate_stats_tlv {
1302 u32 mac_id__word;
1303 u32 nsts;
1304
1305 u32 rx_ldpc;
1306 u32 rts_cnt;
1307
1308 u32 rssi_mgmt;
1309 u32 rssi_data;
1310 u32 rssi_comb;
1311 u32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1312
1313 u32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1314 u32 rx_dcm[HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS];
1315 u32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1316
1317 u32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
1318 u32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES];
1319 u8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
1320 [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
1321
1322
1323
1324
1325
1326 u32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1327 s32 rssi_in_dbm;
1328
1329 u32 rx_11ax_su_ext;
1330 u32 rx_11ac_mumimo;
1331 u32 rx_11ax_mumimo;
1332 u32 rx_11ax_ofdma;
1333 u32 txbf;
1334 u32 rx_legacy_cck_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS];
1335 u32 rx_legacy_ofdm_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
1336 u32 rx_active_dur_us_low;
1337 u32 rx_active_dur_us_high;
1338
1339 u32 rx_11ax_ul_ofdma;
1340
1341 u32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1342 u32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS]
1343 [HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
1344 u32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1345 u32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
1346 u32 ul_ofdma_rx_stbc;
1347 u32 ul_ofdma_rx_ldpc;
1348
1349
1350 u32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
1351 u32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
1352 u32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
1353 u32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
1354
1355 u32 nss_count;
1356 u32 pilot_count;
1357
1358 s32 rx_pilot_evm_db[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
1359 [HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS];
1360
1361
1362
1363
1364 s32 rx_pilot_evm_db_mean[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1365 s8 rx_ul_fd_rssi[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
1366 [HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
1367
1368
1369
1370
1371
1372
1373
1374
1375 u32 per_chain_rssi_pkt_type;
1376 s8 rx_per_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]
1377 [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
1378};
1379
1380
1381struct htt_rx_soc_fw_stats_tlv {
1382 u32 fw_reo_ring_data_msdu;
1383 u32 fw_to_host_data_msdu_bcmc;
1384 u32 fw_to_host_data_msdu_uc;
1385 u32 ofld_remote_data_buf_recycle_cnt;
1386 u32 ofld_remote_free_buf_indication_cnt;
1387
1388 u32 ofld_buf_to_host_data_msdu_uc;
1389 u32 reo_fw_ring_to_host_data_msdu_uc;
1390
1391 u32 wbm_sw_ring_reap;
1392 u32 wbm_forward_to_host_cnt;
1393 u32 wbm_target_recycle_cnt;
1394
1395 u32 target_refill_ring_recycle_cnt;
1396};
1397
1398
1399struct htt_rx_soc_fw_refill_ring_empty_tlv_v {
1400 u32 refill_ring_empty_cnt[0];
1401};
1402
1403
1404struct htt_rx_soc_fw_refill_ring_num_refill_tlv_v {
1405 u32 refill_ring_num_refill[0];
1406};
1407
1408
1409enum htt_rx_rxdma_error_code_enum {
1410 HTT_RX_RXDMA_OVERFLOW_ERR = 0,
1411 HTT_RX_RXDMA_MPDU_LENGTH_ERR = 1,
1412 HTT_RX_RXDMA_FCS_ERR = 2,
1413 HTT_RX_RXDMA_DECRYPT_ERR = 3,
1414 HTT_RX_RXDMA_TKIP_MIC_ERR = 4,
1415 HTT_RX_RXDMA_UNECRYPTED_ERR = 5,
1416 HTT_RX_RXDMA_MSDU_LEN_ERR = 6,
1417 HTT_RX_RXDMA_MSDU_LIMIT_ERR = 7,
1418 HTT_RX_RXDMA_WIFI_PARSE_ERR = 8,
1419 HTT_RX_RXDMA_AMSDU_PARSE_ERR = 9,
1420 HTT_RX_RXDMA_SA_TIMEOUT_ERR = 10,
1421 HTT_RX_RXDMA_DA_TIMEOUT_ERR = 11,
1422 HTT_RX_RXDMA_FLOW_TIMEOUT_ERR = 12,
1423 HTT_RX_RXDMA_FLUSH_REQUEST = 13,
1424 HTT_RX_RXDMA_ERR_CODE_RVSD0 = 14,
1425 HTT_RX_RXDMA_ERR_CODE_RVSD1 = 15,
1426
1427
1428
1429
1430
1431
1432 HTT_RX_RXDMA_MAX_ERR_CODE
1433};
1434
1435
1436struct htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v {
1437 u32 rxdma_err[0];
1438};
1439
1440
1441enum htt_rx_reo_error_code_enum {
1442 HTT_RX_REO_QUEUE_DESC_ADDR_ZERO = 0,
1443 HTT_RX_REO_QUEUE_DESC_NOT_VALID = 1,
1444 HTT_RX_AMPDU_IN_NON_BA = 2,
1445 HTT_RX_NON_BA_DUPLICATE = 3,
1446 HTT_RX_BA_DUPLICATE = 4,
1447 HTT_RX_REGULAR_FRAME_2K_JUMP = 5,
1448 HTT_RX_BAR_FRAME_2K_JUMP = 6,
1449 HTT_RX_REGULAR_FRAME_OOR = 7,
1450 HTT_RX_BAR_FRAME_OOR = 8,
1451 HTT_RX_BAR_FRAME_NO_BA_SESSION = 9,
1452 HTT_RX_BAR_FRAME_SN_EQUALS_SSN = 10,
1453 HTT_RX_PN_CHECK_FAILED = 11,
1454 HTT_RX_2K_ERROR_HANDLING_FLAG_SET = 12,
1455 HTT_RX_PN_ERROR_HANDLING_FLAG_SET = 13,
1456 HTT_RX_QUEUE_DESCRIPTOR_BLOCKED_SET = 14,
1457 HTT_RX_REO_ERR_CODE_RVSD = 15,
1458
1459
1460
1461
1462
1463
1464 HTT_RX_REO_MAX_ERR_CODE
1465};
1466
1467
1468struct htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v {
1469 u32 reo_err[0];
1470};
1471
1472
1473#define HTT_STATS_SUBTYPE_MAX 16
1474
1475struct htt_rx_pdev_fw_stats_tlv {
1476 u32 mac_id__word;
1477 u32 ppdu_recvd;
1478 u32 mpdu_cnt_fcs_ok;
1479 u32 mpdu_cnt_fcs_err;
1480 u32 tcp_msdu_cnt;
1481 u32 tcp_ack_msdu_cnt;
1482 u32 udp_msdu_cnt;
1483 u32 other_msdu_cnt;
1484 u32 fw_ring_mpdu_ind;
1485 u32 fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX];
1486 u32 fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX];
1487 u32 fw_ring_mcast_data_msdu;
1488 u32 fw_ring_bcast_data_msdu;
1489 u32 fw_ring_ucast_data_msdu;
1490 u32 fw_ring_null_data_msdu;
1491 u32 fw_ring_mpdu_drop;
1492 u32 ofld_local_data_ind_cnt;
1493 u32 ofld_local_data_buf_recycle_cnt;
1494 u32 drx_local_data_ind_cnt;
1495 u32 drx_local_data_buf_recycle_cnt;
1496 u32 local_nondata_ind_cnt;
1497 u32 local_nondata_buf_recycle_cnt;
1498
1499 u32 fw_status_buf_ring_refill_cnt;
1500 u32 fw_status_buf_ring_empty_cnt;
1501 u32 fw_pkt_buf_ring_refill_cnt;
1502 u32 fw_pkt_buf_ring_empty_cnt;
1503 u32 fw_link_buf_ring_refill_cnt;
1504 u32 fw_link_buf_ring_empty_cnt;
1505
1506 u32 host_pkt_buf_ring_refill_cnt;
1507 u32 host_pkt_buf_ring_empty_cnt;
1508 u32 mon_pkt_buf_ring_refill_cnt;
1509 u32 mon_pkt_buf_ring_empty_cnt;
1510 u32 mon_status_buf_ring_refill_cnt;
1511 u32 mon_status_buf_ring_empty_cnt;
1512 u32 mon_desc_buf_ring_refill_cnt;
1513 u32 mon_desc_buf_ring_empty_cnt;
1514 u32 mon_dest_ring_update_cnt;
1515 u32 mon_dest_ring_full_cnt;
1516
1517 u32 rx_suspend_cnt;
1518 u32 rx_suspend_fail_cnt;
1519 u32 rx_resume_cnt;
1520 u32 rx_resume_fail_cnt;
1521 u32 rx_ring_switch_cnt;
1522 u32 rx_ring_restore_cnt;
1523 u32 rx_flush_cnt;
1524 u32 rx_recovery_reset_cnt;
1525};
1526
1527#define HTT_STATS_PHY_ERR_MAX 43
1528
1529struct htt_rx_pdev_fw_stats_phy_err_tlv {
1530 u32 mac_id__word;
1531 u32 total_phy_err_cnt;
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580 u32 phy_err[HTT_STATS_PHY_ERR_MAX];
1581};
1582
1583
1584struct htt_rx_pdev_fw_ring_mpdu_err_tlv_v {
1585
1586 u32 fw_ring_mpdu_err[0];
1587};
1588
1589
1590struct htt_rx_pdev_fw_mpdu_drop_tlv_v {
1591
1592 u32 fw_mpdu_drop[0];
1593};
1594
1595#define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1)
1596#define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2)
1597#define HTT_PDEV_CCA_STATS_RX_CLEAR_INFO_PRESENT (0x4)
1598#define HTT_PDEV_CCA_STATS_MY_RX_FRAME_INFO_PRESENT (0x8)
1599#define HTT_PDEV_CCA_STATS_USEC_CNT_INFO_PRESENT (0x10)
1600#define HTT_PDEV_CCA_STATS_MED_RX_IDLE_INFO_PRESENT (0x20)
1601#define HTT_PDEV_CCA_STATS_MED_TX_IDLE_GLOBAL_INFO_PRESENT (0x40)
1602#define HTT_PDEV_CCA_STATS_CCA_OBBS_USEC_INFO_PRESENT (0x80)
1603
1604struct htt_pdev_stats_cca_counters_tlv {
1605
1606 u32 tx_frame_usec;
1607 u32 rx_frame_usec;
1608 u32 rx_clear_usec;
1609 u32 my_rx_frame_usec;
1610 u32 usec_cnt;
1611 u32 med_rx_idle_usec;
1612 u32 med_tx_idle_global_usec;
1613 u32 cca_obss_usec;
1614};
1615
1616struct htt_pdev_cca_stats_hist_v1_tlv {
1617 u32 chan_num;
1618
1619 u32 num_records;
1620 u32 valid_cca_counters_bitmap;
1621 u32 collection_interval;
1622
1623
1624
1625
1626
1627
1628
1629
1630};
1631
1632struct htt_pdev_stats_twt_session_tlv {
1633 u32 vdev_id;
1634 struct htt_mac_addr peer_mac;
1635 u32 flow_id_flags;
1636
1637
1638
1639
1640 u32 dialog_id;
1641 u32 wake_dura_us;
1642 u32 wake_intvl_us;
1643 u32 sp_offset_us;
1644};
1645
1646struct htt_pdev_stats_twt_sessions_tlv {
1647 u32 pdev_id;
1648 u32 num_sessions;
1649 struct htt_pdev_stats_twt_session_tlv twt_session[];
1650};
1651
1652enum htt_rx_reo_resource_sample_id_enum {
1653
1654 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_0 = 0,
1655 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_1 = 1,
1656 HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_2 = 2,
1657
1658 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC0 = 3,
1659 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC1 = 4,
1660 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC2 = 5,
1661 HTT_RX_REO_RESOURCE_BUFFERS_USED_AC3 = 6,
1662
1663 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC0 = 7,
1664 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC1 = 8,
1665 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC2 = 9,
1666 HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC3 = 10,
1667
1668 HTT_RX_REO_RESOURCE_STATS_MAX = 16
1669};
1670
1671struct htt_rx_reo_resource_stats_tlv_v {
1672
1673 u32 sample_id;
1674 u32 total_max;
1675 u32 total_avg;
1676 u32 total_sample;
1677 u32 non_zeros_avg;
1678 u32 non_zeros_sample;
1679 u32 last_non_zeros_max;
1680 u32 last_non_zeros_min;
1681 u32 last_non_zeros_avg;
1682 u32 last_non_zeros_sample;
1683};
1684
1685
1686
1687enum htt_txbf_sound_steer_modes {
1688 HTT_IMPLICIT_TXBF_STEER_STATS = 0,
1689 HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS = 1,
1690 HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS = 2,
1691 HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS = 3,
1692 HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS = 4,
1693 HTT_TXBF_MAX_NUM_OF_MODES = 5
1694};
1695
1696enum htt_stats_sounding_tx_mode {
1697 HTT_TX_AC_SOUNDING_MODE = 0,
1698 HTT_TX_AX_SOUNDING_MODE = 1,
1699};
1700
1701struct htt_tx_sounding_stats_tlv {
1702 u32 tx_sounding_mode;
1703
1704 u32 cbf_20[HTT_TXBF_MAX_NUM_OF_MODES];
1705 u32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES];
1706 u32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES];
1707 u32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES];
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717 u32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS];
1718};
1719
1720struct htt_pdev_obss_pd_stats_tlv {
1721 u32 num_obss_tx_ppdu_success;
1722 u32 num_obss_tx_ppdu_failure;
1723 u32 num_sr_tx_transmissions;
1724 u32 num_spatial_reuse_opportunities;
1725 u32 num_non_srg_opportunities;
1726 u32 num_non_srg_ppdu_tried;
1727 u32 num_non_srg_ppdu_success;
1728 u32 num_srg_opportunities;
1729 u32 num_srg_ppdu_tried;
1730 u32 num_srg_ppdu_success;
1731 u32 num_psr_opportunities;
1732 u32 num_psr_ppdu_tried;
1733 u32 num_psr_ppdu_success;
1734};
1735
1736struct htt_ring_backpressure_stats_tlv {
1737 u32 pdev_id;
1738 u32 current_head_idx;
1739 u32 current_tail_idx;
1740 u32 num_htt_msgs_sent;
1741
1742
1743
1744 u32 backpressure_time_ms;
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758 u32 backpressure_hist[5];
1759};
1760
1761#define HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS 14
1762#define HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS 5
1763#define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
1764
1765struct htt_pdev_txrate_txbf_stats_tlv {
1766
1767 u32 tx_su_txbf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
1768
1769 u32 tx_su_ibf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
1770
1771 u32 tx_su_ol_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS];
1772
1773 u32 tx_su_txbf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1774
1775 u32 tx_su_ibf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1776
1777 u32 tx_su_ol_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
1778
1779 u32 tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
1780
1781 u32 tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
1782
1783 u32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS];
1784};
1785
1786struct htt_txbf_ofdma_ndpa_stats_tlv {
1787
1788 u32 ax_ofdma_ndpa_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1789
1790 u32 ax_ofdma_ndpa_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1791
1792 u32 ax_ofdma_ndpa_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1793
1794 u32 ax_ofdma_ndpa_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1795};
1796
1797struct htt_txbf_ofdma_ndp_stats_tlv {
1798
1799 u32 ax_ofdma_ndp_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1800
1801 u32 ax_ofdma_ndp_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1802
1803 u32 ax_ofdma_ndp_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1804
1805 u32 ax_ofdma_ndp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1806};
1807
1808struct htt_txbf_ofdma_brp_stats_tlv {
1809
1810 u32 ax_ofdma_brpoll_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1811
1812 u32 ax_ofdma_brpoll_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1813
1814 u32 ax_ofdma_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1815
1816 u32 ax_ofdma_brp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1817
1818
1819
1820 u32 ax_ofdma_brp_err_num_cbf_rcvd[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS + 1];
1821};
1822
1823struct htt_txbf_ofdma_steer_stats_tlv {
1824
1825 u32 ax_ofdma_num_ppdu_steer[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1826
1827 u32 ax_ofdma_num_ppdu_ol[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1828
1829
1830
1831 u32 ax_ofdma_num_usrs_prefetch[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1832
1833 u32 ax_ofdma_num_usrs_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1834
1835 u32 ax_ofdma_num_usrs_force_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
1836};
1837
1838#define HTT_MAX_RX_PKT_CNT 8
1839#define HTT_MAX_RX_PKT_CRC_PASS_CNT 8
1840#define HTT_MAX_PER_BLK_ERR_CNT 20
1841#define HTT_MAX_RX_OTA_ERR_CNT 14
1842#define HTT_STATS_MAX_CHAINS 8
1843#define ATH11K_STATS_MGMT_FRM_TYPE_MAX 16
1844
1845struct htt_phy_counters_tlv {
1846
1847 u32 rx_ofdma_timing_err_cnt;
1848
1849
1850
1851
1852 u32 rx_cck_fail_cnt;
1853
1854 u32 mactx_abort_cnt;
1855
1856 u32 macrx_abort_cnt;
1857
1858 u32 phytx_abort_cnt;
1859
1860 u32 phyrx_abort_cnt;
1861
1862 u32 phyrx_defer_abort_cnt;
1863
1864 u32 rx_gain_adj_lstf_event_cnt;
1865
1866 u32 rx_gain_adj_non_legacy_cnt;
1867
1868
1869
1870
1871
1872 u32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT];
1873
1874
1875
1876
1877
1878 u32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT];
1879
1880
1881
1882
1883
1884
1885
1886 u32 per_blk_err_cnt[HTT_MAX_PER_BLK_ERR_CNT];
1887
1888
1889
1890
1891
1892
1893
1894
1895 u32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT];
1896};
1897
1898struct htt_phy_stats_tlv {
1899
1900 s32 nf_chain[HTT_STATS_MAX_CHAINS];
1901
1902 u32 false_radar_cnt;
1903
1904 u32 radar_cs_cnt;
1905
1906
1907
1908
1909
1910 s32 ani_level;
1911
1912 u32 fw_run_time;
1913};
1914
1915struct htt_peer_ctrl_path_txrx_stats_tlv {
1916
1917 u8 peer_mac_addr[ETH_ALEN];
1918 u8 rsvd[2];
1919
1920 u32 peer_tx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX];
1921
1922 u32 peer_rx_mgmt_subtype[ATH11K_STATS_MGMT_FRM_TYPE_MAX];
1923};
1924
1925#ifdef CONFIG_ATH11K_DEBUGFS
1926
1927void ath11k_debugfs_htt_stats_init(struct ath11k *ar);
1928void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab,
1929 struct sk_buff *skb);
1930int ath11k_debugfs_htt_stats_req(struct ath11k *ar);
1931
1932#else
1933
1934static inline void ath11k_debugfs_htt_stats_init(struct ath11k *ar)
1935{
1936}
1937
1938static inline void ath11k_debugfs_htt_ext_stats_handler(struct ath11k_base *ab,
1939 struct sk_buff *skb)
1940{
1941}
1942
1943static inline int ath11k_debugfs_htt_stats_req(struct ath11k *ar)
1944{
1945 return 0;
1946}
1947
1948#endif
1949
1950#endif
1951