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6#ifndef __iwl_fw_api_rs_h__
7#define __iwl_fw_api_rs_h__
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9#include "mac.h"
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25enum iwl_tlc_mng_cfg_flags {
26 IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0),
27 IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(1),
28 IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK = BIT(2),
29 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK = BIT(3),
30 IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK = BIT(4),
31};
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41enum iwl_tlc_mng_cfg_cw {
42 IWL_TLC_MNG_CH_WIDTH_20MHZ,
43 IWL_TLC_MNG_CH_WIDTH_40MHZ,
44 IWL_TLC_MNG_CH_WIDTH_80MHZ,
45 IWL_TLC_MNG_CH_WIDTH_160MHZ,
46 IWL_TLC_MNG_CH_WIDTH_LAST = IWL_TLC_MNG_CH_WIDTH_160MHZ,
47};
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54enum iwl_tlc_mng_cfg_chains {
55 IWL_TLC_MNG_CHAIN_A_MSK = BIT(0),
56 IWL_TLC_MNG_CHAIN_B_MSK = BIT(1),
57};
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70enum iwl_tlc_mng_cfg_mode {
71 IWL_TLC_MNG_MODE_CCK = 0,
72 IWL_TLC_MNG_MODE_OFDM_NON_HT = IWL_TLC_MNG_MODE_CCK,
73 IWL_TLC_MNG_MODE_NON_HT = IWL_TLC_MNG_MODE_CCK,
74 IWL_TLC_MNG_MODE_HT,
75 IWL_TLC_MNG_MODE_VHT,
76 IWL_TLC_MNG_MODE_HE,
77 IWL_TLC_MNG_MODE_INVALID,
78 IWL_TLC_MNG_MODE_NUM = IWL_TLC_MNG_MODE_INVALID,
79};
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97enum iwl_tlc_mng_ht_rates {
98 IWL_TLC_MNG_HT_RATE_MCS0 = 0,
99 IWL_TLC_MNG_HT_RATE_MCS1,
100 IWL_TLC_MNG_HT_RATE_MCS2,
101 IWL_TLC_MNG_HT_RATE_MCS3,
102 IWL_TLC_MNG_HT_RATE_MCS4,
103 IWL_TLC_MNG_HT_RATE_MCS5,
104 IWL_TLC_MNG_HT_RATE_MCS6,
105 IWL_TLC_MNG_HT_RATE_MCS7,
106 IWL_TLC_MNG_HT_RATE_MCS8,
107 IWL_TLC_MNG_HT_RATE_MCS9,
108 IWL_TLC_MNG_HT_RATE_MCS10,
109 IWL_TLC_MNG_HT_RATE_MCS11,
110 IWL_TLC_MNG_HT_RATE_MAX = IWL_TLC_MNG_HT_RATE_MCS11,
111};
112
113enum IWL_TLC_MNG_NSS {
114 IWL_TLC_NSS_1,
115 IWL_TLC_NSS_2,
116 IWL_TLC_NSS_MAX
117};
118
119enum IWL_TLC_HT_BW_RATES {
120 IWL_TLC_HT_BW_NONE_160,
121 IWL_TLC_HT_BW_160,
122};
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143struct iwl_tlc_config_cmd {
144 u8 sta_id;
145 u8 reserved1[3];
146 u8 max_ch_width;
147 u8 mode;
148 u8 chains;
149 u8 amsdu;
150 __le16 flags;
151 __le16 non_ht_rates;
152 __le16 ht_rates[IWL_TLC_NSS_MAX][2];
153 __le16 max_mpdu_len;
154 u8 sgi_ch_width_supp;
155 u8 reserved2;
156 __le32 max_tx_op;
157} __packed;
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164enum iwl_tlc_update_flags {
165 IWL_TLC_NOTIF_FLAG_RATE = BIT(0),
166 IWL_TLC_NOTIF_FLAG_AMSDU = BIT(1),
167};
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178struct iwl_tlc_update_notif {
179 u8 sta_id;
180 u8 reserved[3];
181 __le32 flags;
182 __le32 rate;
183 __le32 amsdu_size;
184 __le32 amsdu_enabled;
185} __packed;
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187
188#define IWL_MAX_MCS_DISPLAY_SIZE 12
189
190struct iwl_rate_mcs_info {
191 char mbps[IWL_MAX_MCS_DISPLAY_SIZE];
192 char mcs[IWL_MAX_MCS_DISPLAY_SIZE];
193};
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200enum {
201 IWL_RATE_1M_INDEX = 0,
202 IWL_FIRST_CCK_RATE = IWL_RATE_1M_INDEX,
203 IWL_RATE_2M_INDEX,
204 IWL_RATE_5M_INDEX,
205 IWL_RATE_11M_INDEX,
206 IWL_LAST_CCK_RATE = IWL_RATE_11M_INDEX,
207 IWL_RATE_6M_INDEX,
208 IWL_FIRST_OFDM_RATE = IWL_RATE_6M_INDEX,
209 IWL_RATE_MCS_0_INDEX = IWL_RATE_6M_INDEX,
210 IWL_FIRST_HT_RATE = IWL_RATE_MCS_0_INDEX,
211 IWL_FIRST_VHT_RATE = IWL_RATE_MCS_0_INDEX,
212 IWL_RATE_9M_INDEX,
213 IWL_RATE_12M_INDEX,
214 IWL_RATE_MCS_1_INDEX = IWL_RATE_12M_INDEX,
215 IWL_RATE_18M_INDEX,
216 IWL_RATE_MCS_2_INDEX = IWL_RATE_18M_INDEX,
217 IWL_RATE_24M_INDEX,
218 IWL_RATE_MCS_3_INDEX = IWL_RATE_24M_INDEX,
219 IWL_RATE_36M_INDEX,
220 IWL_RATE_MCS_4_INDEX = IWL_RATE_36M_INDEX,
221 IWL_RATE_48M_INDEX,
222 IWL_RATE_MCS_5_INDEX = IWL_RATE_48M_INDEX,
223 IWL_RATE_54M_INDEX,
224 IWL_RATE_MCS_6_INDEX = IWL_RATE_54M_INDEX,
225 IWL_LAST_NON_HT_RATE = IWL_RATE_54M_INDEX,
226 IWL_RATE_60M_INDEX,
227 IWL_RATE_MCS_7_INDEX = IWL_RATE_60M_INDEX,
228 IWL_LAST_HT_RATE = IWL_RATE_MCS_7_INDEX,
229 IWL_RATE_MCS_8_INDEX,
230 IWL_RATE_MCS_9_INDEX,
231 IWL_LAST_VHT_RATE = IWL_RATE_MCS_9_INDEX,
232 IWL_RATE_MCS_10_INDEX,
233 IWL_RATE_MCS_11_INDEX,
234 IWL_LAST_HE_RATE = IWL_RATE_MCS_11_INDEX,
235 IWL_RATE_COUNT_LEGACY = IWL_LAST_NON_HT_RATE + 1,
236 IWL_RATE_COUNT = IWL_LAST_HE_RATE + 1,
237 IWL_RATE_INVM_INDEX = IWL_RATE_COUNT,
238 IWL_RATE_INVALID = IWL_RATE_COUNT,
239};
240
241#define IWL_RATE_BIT_MSK(r) BIT(IWL_RATE_##r##M_INDEX)
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244enum {
245 IWL_RATE_6M_PLCP = 13,
246 IWL_RATE_9M_PLCP = 15,
247 IWL_RATE_12M_PLCP = 5,
248 IWL_RATE_18M_PLCP = 7,
249 IWL_RATE_24M_PLCP = 9,
250 IWL_RATE_36M_PLCP = 11,
251 IWL_RATE_48M_PLCP = 1,
252 IWL_RATE_54M_PLCP = 3,
253 IWL_RATE_1M_PLCP = 10,
254 IWL_RATE_2M_PLCP = 20,
255 IWL_RATE_5M_PLCP = 55,
256 IWL_RATE_11M_PLCP = 110,
257 IWL_RATE_INVM_PLCP = -1,
258};
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278#define RATE_MCS_HT_POS 8
279#define RATE_MCS_HT_MSK_V1 BIT(RATE_MCS_HT_POS)
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282#define RATE_MCS_CCK_POS_V1 9
283#define RATE_MCS_CCK_MSK_V1 BIT(RATE_MCS_CCK_POS_V1)
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286#define RATE_MCS_VHT_POS_V1 26
287#define RATE_MCS_VHT_MSK_V1 BIT(RATE_MCS_VHT_POS_V1)
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313#define RATE_HT_MCS_RATE_CODE_MSK_V1 0x7
314#define RATE_HT_MCS_NSS_POS_V1 3
315#define RATE_HT_MCS_NSS_MSK_V1 (3 << RATE_HT_MCS_NSS_POS_V1)
316#define RATE_HT_MCS_MIMO2_MSK BIT(RATE_HT_MCS_NSS_POS_V1)
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319#define RATE_HT_MCS_GF_POS 10
320#define RATE_HT_MCS_GF_MSK (1 << RATE_HT_MCS_GF_POS)
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322#define RATE_HT_MCS_INDEX_MSK_V1 0x3f
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335#define RATE_VHT_MCS_RATE_CODE_MSK 0xf
336#define RATE_VHT_MCS_NSS_POS 4
337#define RATE_VHT_MCS_NSS_MSK (3 << RATE_VHT_MCS_NSS_POS)
338#define RATE_VHT_MCS_MIMO2_MSK BIT(RATE_VHT_MCS_NSS_POS)
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362#define RATE_LEGACY_RATE_MSK_V1 0xff
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365#define RATE_MCS_HE_POS_V1 10
366#define RATE_MCS_HE_MSK_V1 BIT(RATE_MCS_HE_POS_V1)
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372#define RATE_MCS_CHAN_WIDTH_POS 11
373#define RATE_MCS_CHAN_WIDTH_MSK_V1 (3 << RATE_MCS_CHAN_WIDTH_POS)
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376#define RATE_MCS_SGI_POS_V1 13
377#define RATE_MCS_SGI_MSK_V1 BIT(RATE_MCS_SGI_POS_V1)
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380#define RATE_MCS_ANT_POS 14
381#define RATE_MCS_ANT_A_MSK (1 << RATE_MCS_ANT_POS)
382#define RATE_MCS_ANT_B_MSK (2 << RATE_MCS_ANT_POS)
383#define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | \
384 RATE_MCS_ANT_B_MSK)
385#define RATE_MCS_ANT_MSK RATE_MCS_ANT_AB_MSK
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388#define RATE_MCS_STBC_POS 17
389#define RATE_MCS_STBC_MSK BIT(RATE_MCS_STBC_POS)
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392#define RATE_HE_DUAL_CARRIER_MODE 18
393#define RATE_HE_DUAL_CARRIER_MODE_MSK BIT(RATE_HE_DUAL_CARRIER_MODE)
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396#define RATE_MCS_BF_POS 19
397#define RATE_MCS_BF_MSK (1 << RATE_MCS_BF_POS)
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418#define RATE_MCS_HE_GI_LTF_POS 20
419#define RATE_MCS_HE_GI_LTF_MSK_V1 (3 << RATE_MCS_HE_GI_LTF_POS)
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422#define RATE_MCS_HE_TYPE_POS_V1 22
423#define RATE_MCS_HE_TYPE_SU_V1 (0 << RATE_MCS_HE_TYPE_POS_V1)
424#define RATE_MCS_HE_TYPE_EXT_SU_V1 BIT(RATE_MCS_HE_TYPE_POS_V1)
425#define RATE_MCS_HE_TYPE_MU_V1 (2 << RATE_MCS_HE_TYPE_POS_V1)
426#define RATE_MCS_HE_TYPE_TRIG_V1 (3 << RATE_MCS_HE_TYPE_POS_V1)
427#define RATE_MCS_HE_TYPE_MSK_V1 (3 << RATE_MCS_HE_TYPE_POS_V1)
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430#define RATE_MCS_DUP_POS_V1 24
431#define RATE_MCS_DUP_MSK_V1 (3 << RATE_MCS_DUP_POS_V1)
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434#define RATE_MCS_LDPC_POS_V1 27
435#define RATE_MCS_LDPC_MSK_V1 BIT(RATE_MCS_LDPC_POS_V1)
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438#define RATE_MCS_HE_106T_POS_V1 28
439#define RATE_MCS_HE_106T_MSK_V1 BIT(RATE_MCS_HE_106T_POS_V1)
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442#define RATE_MCS_RTS_REQUIRED_POS (30)
443#define RATE_MCS_RTS_REQUIRED_MSK (0x1 << RATE_MCS_RTS_REQUIRED_POS)
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445#define RATE_MCS_CTS_REQUIRED_POS (31)
446#define RATE_MCS_CTS_REQUIRED_MSK (0x1 << RATE_MCS_CTS_REQUIRED_POS)
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461#define RATE_MCS_MOD_TYPE_POS 8
462#define RATE_MCS_MOD_TYPE_MSK (0x7 << RATE_MCS_MOD_TYPE_POS)
463#define RATE_MCS_CCK_MSK (0 << RATE_MCS_MOD_TYPE_POS)
464#define RATE_MCS_LEGACY_OFDM_MSK (1 << RATE_MCS_MOD_TYPE_POS)
465#define RATE_MCS_HT_MSK (2 << RATE_MCS_MOD_TYPE_POS)
466#define RATE_MCS_VHT_MSK (3 << RATE_MCS_MOD_TYPE_POS)
467#define RATE_MCS_HE_MSK (4 << RATE_MCS_MOD_TYPE_POS)
468#define RATE_MCS_EHT_MSK (5 << RATE_MCS_MOD_TYPE_POS)
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490#define RATE_LEGACY_RATE_MSK 0x7
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497#define RATE_HT_MCS_CODE_MSK 0x7
498#define RATE_MCS_NSS_POS 4
499#define RATE_MCS_NSS_MSK (1 << RATE_MCS_NSS_POS)
500#define RATE_MCS_CODE_MSK 0xf
501#define RATE_HT_MCS_INDEX(r) ((((r) & RATE_MCS_NSS_MSK) >> 1) | \
502 ((r) & RATE_HT_MCS_CODE_MSK))
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509#define RATE_MCS_CHAN_WIDTH_MSK (0x7 << RATE_MCS_CHAN_WIDTH_POS)
510#define RATE_MCS_CHAN_WIDTH_20 (0 << RATE_MCS_CHAN_WIDTH_POS)
511#define RATE_MCS_CHAN_WIDTH_40 (1 << RATE_MCS_CHAN_WIDTH_POS)
512#define RATE_MCS_CHAN_WIDTH_80 (2 << RATE_MCS_CHAN_WIDTH_POS)
513#define RATE_MCS_CHAN_WIDTH_160 (3 << RATE_MCS_CHAN_WIDTH_POS)
514#define RATE_MCS_CHAN_WIDTH_320 (4 << RATE_MCS_CHAN_WIDTH_POS)
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524#define RATE_MCS_LDPC_POS 16
525#define RATE_MCS_LDPC_MSK (1 << RATE_MCS_LDPC_POS)
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557#define RATE_MCS_HE_GI_LTF_MSK (0x7 << RATE_MCS_HE_GI_LTF_POS)
558#define RATE_MCS_SGI_POS RATE_MCS_HE_GI_LTF_POS
559#define RATE_MCS_SGI_MSK (1 << RATE_MCS_SGI_POS)
560#define RATE_MCS_HE_SU_4_LTF 3
561#define RATE_MCS_HE_SU_4_LTF_08_GI 4
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564#define RATE_MCS_HE_TYPE_POS 23
565#define RATE_MCS_HE_TYPE_SU (0 << RATE_MCS_HE_TYPE_POS)
566#define RATE_MCS_HE_TYPE_EXT_SU (1 << RATE_MCS_HE_TYPE_POS)
567#define RATE_MCS_HE_TYPE_MU (2 << RATE_MCS_HE_TYPE_POS)
568#define RATE_MCS_HE_TYPE_TRIG (3 << RATE_MCS_HE_TYPE_POS)
569#define RATE_MCS_HE_TYPE_MSK (3 << RATE_MCS_HE_TYPE_POS)
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579#define RATE_MCS_DUP_POS 25
580#define RATE_MCS_DUP_MSK (1 << RATE_MCS_DUP_POS)
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583#define RATE_MCS_HE_106T_POS 26
584#define RATE_MCS_HE_106T_MSK (1 << RATE_MCS_HE_106T_POS)
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589#define RATE_MCS_EHT_EXTRA_LTF_POS 27
590#define RATE_MCS_EHT_EXTRA_LTF_MSK (1 << RATE_MCS_EHT_EXTRA_LTF_POS)
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597#define LQ_MAX_RETRY_NUM 16
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602#define LQ_FLAG_USE_RTS_POS 0
603#define LQ_FLAG_USE_RTS_MSK (1 << LQ_FLAG_USE_RTS_POS)
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606#define LQ_FLAG_COLOR_POS 1
607#define LQ_FLAG_COLOR_MSK (7 << LQ_FLAG_COLOR_POS)
608#define LQ_FLAG_COLOR_GET(_f) (((_f) & LQ_FLAG_COLOR_MSK) >>\
609 LQ_FLAG_COLOR_POS)
610#define LQ_FLAGS_COLOR_INC(_c) ((((_c) + 1) << LQ_FLAG_COLOR_POS) &\
611 LQ_FLAG_COLOR_MSK)
612#define LQ_FLAG_COLOR_SET(_f, _c) ((_c) | ((_f) & ~LQ_FLAG_COLOR_MSK))
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619#define LQ_FLAG_RTS_BW_SIG_POS 4
620#define LQ_FLAG_RTS_BW_SIG_NONE (0 << LQ_FLAG_RTS_BW_SIG_POS)
621#define LQ_FLAG_RTS_BW_SIG_STATIC (1 << LQ_FLAG_RTS_BW_SIG_POS)
622#define LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << LQ_FLAG_RTS_BW_SIG_POS)
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627#define LQ_FLAG_DYNAMIC_BW_POS 6
628#define LQ_FLAG_DYNAMIC_BW_MSK (1 << LQ_FLAG_DYNAMIC_BW_POS)
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642#define LQ_SS_STBC_ALLOWED_POS 0
643#define LQ_SS_STBC_ALLOWED_MSK (3 << LQ_SS_STBC_ALLOWED_MSK)
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646#define LQ_SS_STBC_1SS_ALLOWED (1 << LQ_SS_STBC_ALLOWED_POS)
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649#define LQ_SS_BFER_ALLOWED_POS 2
650#define LQ_SS_BFER_ALLOWED (1 << LQ_SS_BFER_ALLOWED_POS)
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657#define LQ_SS_FORCE_POS 3
658#define LQ_SS_FORCE (1 << LQ_SS_FORCE_POS)
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663#define LQ_SS_PARAMS_VALID_POS 31
664#define LQ_SS_PARAMS_VALID (1 << LQ_SS_PARAMS_VALID_POS)
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692struct iwl_lq_cmd {
693 u8 sta_id;
694 u8 reduced_tpc;
695 __le16 control;
696
697 u8 flags;
698 u8 mimo_delim;
699 u8 single_stream_ant_msk;
700 u8 dual_stream_ant_msk;
701 u8 initial_rate_index[AC_NUM];
702
703 __le16 agg_time_limit;
704 u8 agg_disable_start_th;
705 u8 agg_frame_cnt_limit;
706 __le32 reserved2;
707 __le32 rs_table[LQ_MAX_RETRY_NUM];
708 __le32 ss_params;
709};
710
711u8 iwl_fw_rate_idx_to_plcp(int idx);
712u32 iwl_new_rate_from_v1(u32 rate_v1);
713u32 iwl_legacy_rate_to_fw_idx(u32 rate_n_flags);
714const struct iwl_rate_mcs_info *iwl_rate_mcs(int idx);
715const char *iwl_rs_pretty_ant(u8 ant);
716const char *iwl_rs_pretty_bw(int bw);
717int rs_pretty_print_rate(char *buf, int bufsz, const u32 rate);
718bool iwl_he_is_sgi(u32 rate_n_flags);
719
720#endif
721