1
2
3
4#ifndef __MT76_CONNAC_MCU_H
5#define __MT76_CONNAC_MCU_H
6
7#include "mt76_connac.h"
8
9struct tlv {
10 __le16 tag;
11 __le16 len;
12} __packed;
13
14
15
16struct sta_ntlv_hdr {
17 u8 rsv[2];
18 __le16 tlv_num;
19} __packed;
20
21struct sta_req_hdr {
22 u8 bss_idx;
23 u8 wlan_idx_lo;
24 __le16 tlv_num;
25 u8 is_tlv_append;
26 u8 muar_idx;
27 u8 wlan_idx_hi;
28 u8 rsv;
29} __packed;
30
31struct sta_rec_basic {
32 __le16 tag;
33 __le16 len;
34 __le32 conn_type;
35 u8 conn_state;
36 u8 qos;
37 __le16 aid;
38 u8 peer_addr[ETH_ALEN];
39#define EXTRA_INFO_VER BIT(0)
40#define EXTRA_INFO_NEW BIT(1)
41 __le16 extra_info;
42} __packed;
43
44struct sta_rec_ht {
45 __le16 tag;
46 __le16 len;
47 __le16 ht_cap;
48 u16 rsv;
49} __packed;
50
51struct sta_rec_vht {
52 __le16 tag;
53 __le16 len;
54 __le32 vht_cap;
55 __le16 vht_rx_mcs_map;
56 __le16 vht_tx_mcs_map;
57
58 u8 rts_bw_sig;
59 u8 rsv[3];
60} __packed;
61
62struct sta_rec_uapsd {
63 __le16 tag;
64 __le16 len;
65 u8 dac_map;
66 u8 tac_map;
67 u8 max_sp;
68 u8 rsv0;
69 __le16 listen_interval;
70 u8 rsv1[2];
71} __packed;
72
73struct sta_rec_ba {
74 __le16 tag;
75 __le16 len;
76 u8 tid;
77 u8 ba_type;
78 u8 amsdu;
79 u8 ba_en;
80 __le16 ssn;
81 __le16 winsize;
82} __packed;
83
84struct sta_rec_he {
85 __le16 tag;
86 __le16 len;
87
88 __le32 he_cap;
89
90 u8 t_frame_dur;
91 u8 max_ampdu_exp;
92 u8 bw_set;
93 u8 device_class;
94 u8 dcm_tx_mode;
95 u8 dcm_tx_max_nss;
96 u8 dcm_rx_mode;
97 u8 dcm_rx_max_nss;
98 u8 dcm_max_ru;
99 u8 punc_pream_rx;
100 u8 pkt_ext;
101 u8 rsv1;
102
103 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
104
105 u8 rsv2[2];
106} __packed;
107
108struct sta_rec_amsdu {
109 __le16 tag;
110 __le16 len;
111 u8 max_amsdu_num;
112 u8 max_mpdu_size;
113 u8 amsdu_en;
114 u8 rsv;
115} __packed;
116
117struct sta_rec_state {
118 __le16 tag;
119 __le16 len;
120 __le32 flags;
121 u8 state;
122 u8 vht_opmode;
123 u8 action;
124 u8 rsv[1];
125} __packed;
126
127#define RA_LEGACY_OFDM GENMASK(13, 6)
128#define RA_LEGACY_CCK GENMASK(3, 0)
129#define HT_MCS_MASK_NUM 10
130struct sta_rec_ra_info {
131 __le16 tag;
132 __le16 len;
133 __le16 legacy;
134 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
135} __packed;
136
137struct sta_rec_phy {
138 __le16 tag;
139 __le16 len;
140 __le16 basic_rate;
141 u8 phy_type;
142 u8 ampdu;
143 u8 rts_policy;
144 u8 rcpi;
145 u8 rsv[2];
146} __packed;
147
148struct sta_rec_he_6g_capa {
149 __le16 tag;
150 __le16 len;
151 __le16 capa;
152 u8 rsv[2];
153} __packed;
154
155
156
157struct wtbl_req_hdr {
158 u8 wlan_idx_lo;
159 u8 operation;
160 __le16 tlv_num;
161 u8 wlan_idx_hi;
162 u8 rsv[3];
163} __packed;
164
165struct wtbl_generic {
166 __le16 tag;
167 __le16 len;
168 u8 peer_addr[ETH_ALEN];
169 u8 muar_idx;
170 u8 skip_tx;
171 u8 cf_ack;
172 u8 qos;
173 u8 mesh;
174 u8 adm;
175 __le16 partial_aid;
176 u8 baf_en;
177 u8 aad_om;
178} __packed;
179
180struct wtbl_rx {
181 __le16 tag;
182 __le16 len;
183 u8 rcid;
184 u8 rca1;
185 u8 rca2;
186 u8 rv;
187 u8 rsv[4];
188} __packed;
189
190struct wtbl_ht {
191 __le16 tag;
192 __le16 len;
193 u8 ht;
194 u8 ldpc;
195 u8 af;
196 u8 mm;
197 u8 rsv[4];
198} __packed;
199
200struct wtbl_vht {
201 __le16 tag;
202 __le16 len;
203 u8 ldpc;
204 u8 dyn_bw;
205 u8 vht;
206 u8 txop_ps;
207 u8 rsv[4];
208} __packed;
209
210struct wtbl_tx_ps {
211 __le16 tag;
212 __le16 len;
213 u8 txps;
214 u8 rsv[3];
215} __packed;
216
217struct wtbl_hdr_trans {
218 __le16 tag;
219 __le16 len;
220 u8 to_ds;
221 u8 from_ds;
222 u8 no_rx_trans;
223 u8 rsv;
224} __packed;
225
226struct wtbl_ba {
227 __le16 tag;
228 __le16 len;
229
230 u8 tid;
231 u8 ba_type;
232 u8 rsv0[2];
233
234 __le16 sn;
235 u8 ba_en;
236 u8 ba_winsize_idx;
237 __le16 ba_winsize;
238
239 u8 peer_addr[ETH_ALEN];
240 u8 rst_ba_tid;
241 u8 rst_ba_sel;
242 u8 rst_ba_sb;
243 u8 band_idx;
244 u8 rsv1[4];
245} __packed;
246
247struct wtbl_smps {
248 __le16 tag;
249 __le16 len;
250 u8 smps;
251 u8 rsv[3];
252} __packed;
253
254
255
256struct wtbl_bf {
257 __le16 tag;
258 __le16 len;
259 u8 ibf;
260 u8 ebf;
261 u8 ibf_vht;
262 u8 ebf_vht;
263 u8 gid;
264 u8 pfmu_idx;
265 u8 rsv[2];
266} __packed;
267
268struct wtbl_pn {
269 __le16 tag;
270 __le16 len;
271 u8 pn[6];
272 u8 rsv[2];
273} __packed;
274
275struct wtbl_spe {
276 __le16 tag;
277 __le16 len;
278 u8 spe_idx;
279 u8 rsv[3];
280} __packed;
281
282struct wtbl_raw {
283 __le16 tag;
284 __le16 len;
285 u8 wtbl_idx;
286 u8 dw;
287 u8 rsv[2];
288 __le32 msk;
289 __le32 val;
290} __packed;
291
292#define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
293 sizeof(struct wtbl_generic) + \
294 sizeof(struct wtbl_rx) + \
295 sizeof(struct wtbl_ht) + \
296 sizeof(struct wtbl_vht) + \
297 sizeof(struct wtbl_tx_ps) + \
298 sizeof(struct wtbl_hdr_trans) +\
299 sizeof(struct wtbl_ba) + \
300 sizeof(struct wtbl_bf) + \
301 sizeof(struct wtbl_smps) + \
302 sizeof(struct wtbl_pn) + \
303 sizeof(struct wtbl_spe))
304
305#define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
306 sizeof(struct sta_rec_basic) + \
307 sizeof(struct sta_rec_ht) + \
308 sizeof(struct sta_rec_he) + \
309 sizeof(struct sta_rec_ba) + \
310 sizeof(struct sta_rec_vht) + \
311 sizeof(struct sta_rec_uapsd) + \
312 sizeof(struct sta_rec_amsdu) + \
313 sizeof(struct sta_rec_he_6g_capa) + \
314 sizeof(struct tlv) + \
315 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
316
317enum {
318 STA_REC_BASIC,
319 STA_REC_RA,
320 STA_REC_RA_CMM_INFO,
321 STA_REC_RA_UPDATE,
322 STA_REC_BF,
323 STA_REC_AMSDU,
324 STA_REC_BA,
325 STA_REC_STATE,
326 STA_REC_TX_PROC,
327 STA_REC_HT,
328 STA_REC_VHT,
329 STA_REC_APPS,
330 STA_REC_KEY,
331 STA_REC_WTBL,
332 STA_REC_HE,
333 STA_REC_HW_AMSDU,
334 STA_REC_WTBL_AADOM,
335 STA_REC_KEY_V2,
336 STA_REC_MURU,
337 STA_REC_MUEDCA,
338 STA_REC_BFEE,
339 STA_REC_PHY = 0x15,
340 STA_REC_HE_6G = 0x17,
341 STA_REC_MAX_NUM
342};
343
344enum {
345 WTBL_GENERIC,
346 WTBL_RX,
347 WTBL_HT,
348 WTBL_VHT,
349 WTBL_PEER_PS,
350 WTBL_TX_PS,
351 WTBL_HDR_TRANS,
352 WTBL_SEC_KEY,
353 WTBL_BA,
354 WTBL_RDG,
355 WTBL_PROTECT,
356 WTBL_CLEAR,
357 WTBL_BF,
358 WTBL_SMPS,
359 WTBL_RAW_DATA,
360 WTBL_PN,
361 WTBL_SPE,
362 WTBL_MAX_NUM
363};
364
365#define STA_TYPE_STA BIT(0)
366#define STA_TYPE_AP BIT(1)
367#define STA_TYPE_ADHOC BIT(2)
368#define STA_TYPE_WDS BIT(4)
369#define STA_TYPE_BC BIT(5)
370
371#define NETWORK_INFRA BIT(16)
372#define NETWORK_P2P BIT(17)
373#define NETWORK_IBSS BIT(18)
374#define NETWORK_WDS BIT(21)
375
376#define SCAN_FUNC_RANDOM_MAC BIT(0)
377#define SCAN_FUNC_SPLIT_SCAN BIT(5)
378
379#define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
380#define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
381#define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
382#define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
383#define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
384#define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
385#define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
386
387#define CONN_STATE_DISCONNECT 0
388#define CONN_STATE_CONNECT 1
389#define CONN_STATE_PORT_SECURE 2
390
391
392#define STA_REC_HE_CAP_HTC BIT(0)
393#define STA_REC_HE_CAP_BQR BIT(1)
394#define STA_REC_HE_CAP_BSR BIT(2)
395#define STA_REC_HE_CAP_OM BIT(3)
396#define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
397
398#define STA_REC_HE_CAP_DUAL_BAND BIT(5)
399#define STA_REC_HE_CAP_LDPC BIT(6)
400#define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
401#define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
402
403#define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
404#define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
405#define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
406#define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
407
408#define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
409#define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
410#define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
411#define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
412#define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
413
414#define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
415#define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
416#define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
417
418#define PHY_MODE_A BIT(0)
419#define PHY_MODE_B BIT(1)
420#define PHY_MODE_G BIT(2)
421#define PHY_MODE_GN BIT(3)
422#define PHY_MODE_AN BIT(4)
423#define PHY_MODE_AC BIT(5)
424#define PHY_MODE_AX_24G BIT(6)
425#define PHY_MODE_AX_5G BIT(7)
426#define PHY_MODE_AX_6G BIT(8)
427
428#define MODE_CCK BIT(0)
429#define MODE_OFDM BIT(1)
430#define MODE_HT BIT(2)
431#define MODE_VHT BIT(3)
432#define MODE_HE BIT(4)
433
434enum {
435 PHY_TYPE_HR_DSSS_INDEX = 0,
436 PHY_TYPE_ERP_INDEX,
437 PHY_TYPE_ERP_P2P_INDEX,
438 PHY_TYPE_OFDM_INDEX,
439 PHY_TYPE_HT_INDEX,
440 PHY_TYPE_VHT_INDEX,
441 PHY_TYPE_HE_INDEX,
442 PHY_TYPE_INDEX_NUM
443};
444
445#define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX)
446#define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX)
447#define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX)
448#define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX)
449#define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX)
450#define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX)
451
452#define MT_WTBL_RATE_TX_MODE GENMASK(9, 6)
453#define MT_WTBL_RATE_MCS GENMASK(5, 0)
454#define MT_WTBL_RATE_NSS GENMASK(12, 10)
455#define MT_WTBL_RATE_HE_GI GENMASK(7, 4)
456#define MT_WTBL_RATE_GI GENMASK(3, 0)
457
458#define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
459#define MT_WTBL_W5_SHORT_GI_20 BIT(8)
460#define MT_WTBL_W5_SHORT_GI_40 BIT(9)
461#define MT_WTBL_W5_SHORT_GI_80 BIT(10)
462#define MT_WTBL_W5_SHORT_GI_160 BIT(11)
463#define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
464#define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
465#define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
466#define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
467
468enum {
469 WTBL_RESET_AND_SET = 1,
470 WTBL_SET,
471 WTBL_QUERY,
472 WTBL_RESET_ALL
473};
474
475enum {
476 MT_BA_TYPE_INVALID,
477 MT_BA_TYPE_ORIGINATOR,
478 MT_BA_TYPE_RECIPIENT
479};
480
481enum {
482 RST_BA_MAC_TID_MATCH,
483 RST_BA_MAC_MATCH,
484 RST_BA_NO_MATCH
485};
486
487enum {
488 DEV_INFO_ACTIVE,
489 DEV_INFO_MAX_NUM
490};
491
492#define MCU_CMD_ACK BIT(0)
493#define MCU_CMD_UNI BIT(1)
494#define MCU_CMD_QUERY BIT(2)
495
496#define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \
497 MCU_CMD_QUERY)
498
499#define MCU_FW_PREFIX BIT(31)
500#define MCU_UNI_PREFIX BIT(30)
501#define MCU_CE_PREFIX BIT(29)
502#define MCU_QUERY_PREFIX BIT(28)
503#define MCU_CMD_MASK ~(MCU_FW_PREFIX | MCU_UNI_PREFIX | \
504 MCU_CE_PREFIX | MCU_QUERY_PREFIX)
505
506#define MCU_QUERY_MASK BIT(16)
507
508enum {
509 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
510 MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
511 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
512 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
513 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
514 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
515 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
516 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
517 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
518 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
519 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
520 MCU_EXT_CMD_GET_TEMP = 0x2c,
521 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
522 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
523 MCU_EXT_CMD_ATE_CTRL = 0x3d,
524 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
525 MCU_EXT_CMD_DBDC_CTRL = 0x45,
526 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
527 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
528 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
529 MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
530 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
531 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
532 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
533 MCU_EXT_CMD_TXDPD_CAL = 0x60,
534 MCU_EXT_CMD_CAL_CACHE = 0x67,
535 MCU_EXT_CMD_SET_RDD_TH = 0x7c,
536 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
537};
538
539enum {
540 MCU_UNI_CMD_DEV_INFO_UPDATE = MCU_UNI_PREFIX | 0x01,
541 MCU_UNI_CMD_BSS_INFO_UPDATE = MCU_UNI_PREFIX | 0x02,
542 MCU_UNI_CMD_STA_REC_UPDATE = MCU_UNI_PREFIX | 0x03,
543 MCU_UNI_CMD_SUSPEND = MCU_UNI_PREFIX | 0x05,
544 MCU_UNI_CMD_OFFLOAD = MCU_UNI_PREFIX | 0x06,
545 MCU_UNI_CMD_HIF_CTRL = MCU_UNI_PREFIX | 0x07,
546};
547
548enum {
549 MCU_CMD_TARGET_ADDRESS_LEN_REQ = MCU_FW_PREFIX | 0x01,
550 MCU_CMD_FW_START_REQ = MCU_FW_PREFIX | 0x02,
551 MCU_CMD_INIT_ACCESS_REG = 0x3,
552 MCU_CMD_NIC_POWER_CTRL = MCU_FW_PREFIX | 0x4,
553 MCU_CMD_PATCH_START_REQ = MCU_FW_PREFIX | 0x05,
554 MCU_CMD_PATCH_FINISH_REQ = MCU_FW_PREFIX | 0x07,
555 MCU_CMD_PATCH_SEM_CONTROL = MCU_FW_PREFIX | 0x10,
556 MCU_CMD_EXT_CID = 0xed,
557 MCU_CMD_FW_SCATTER = MCU_FW_PREFIX | 0xee,
558 MCU_CMD_RESTART_DL_REQ = MCU_FW_PREFIX | 0xef,
559};
560
561
562enum {
563 MCU_CMD_TEST_CTRL = MCU_CE_PREFIX | 0x01,
564 MCU_CMD_START_HW_SCAN = MCU_CE_PREFIX | 0x03,
565 MCU_CMD_SET_PS_PROFILE = MCU_CE_PREFIX | 0x05,
566 MCU_CMD_SET_CHAN_DOMAIN = MCU_CE_PREFIX | 0x0f,
567 MCU_CMD_SET_BSS_CONNECTED = MCU_CE_PREFIX | 0x16,
568 MCU_CMD_SET_BSS_ABORT = MCU_CE_PREFIX | 0x17,
569 MCU_CMD_CANCEL_HW_SCAN = MCU_CE_PREFIX | 0x1b,
570 MCU_CMD_SET_ROC = MCU_CE_PREFIX | 0x1d,
571 MCU_CMD_SET_P2P_OPPPS = MCU_CE_PREFIX | 0x33,
572 MCU_CMD_SET_RATE_TX_POWER = MCU_CE_PREFIX | 0x5d,
573 MCU_CMD_SCHED_SCAN_ENABLE = MCU_CE_PREFIX | 0x61,
574 MCU_CMD_SCHED_SCAN_REQ = MCU_CE_PREFIX | 0x62,
575 MCU_CMD_GET_NIC_CAPAB = MCU_CE_PREFIX | 0x8a,
576 MCU_CMD_SET_MU_EDCA_PARMS = MCU_CE_PREFIX | 0xb0,
577 MCU_CMD_REG_WRITE = MCU_CE_PREFIX | 0xc0,
578 MCU_CMD_REG_READ = MCU_CE_PREFIX | MCU_QUERY_MASK | 0xc0,
579 MCU_CMD_CHIP_CONFIG = MCU_CE_PREFIX | 0xca,
580 MCU_CMD_FWLOG_2_HOST = MCU_CE_PREFIX | 0xc5,
581 MCU_CMD_GET_WTBL = MCU_CE_PREFIX | 0xcd,
582 MCU_CMD_GET_TXPWR = MCU_CE_PREFIX | 0xd0,
583};
584
585enum {
586 PATCH_SEM_RELEASE,
587 PATCH_SEM_GET
588};
589
590enum {
591 UNI_BSS_INFO_BASIC = 0,
592 UNI_BSS_INFO_RLM = 2,
593 UNI_BSS_INFO_BSS_COLOR = 4,
594 UNI_BSS_INFO_HE_BASIC = 5,
595 UNI_BSS_INFO_BCN_CONTENT = 7,
596 UNI_BSS_INFO_QBSS = 15,
597 UNI_BSS_INFO_UAPSD = 19,
598 UNI_BSS_INFO_PS = 21,
599 UNI_BSS_INFO_BCNFT = 22,
600};
601
602enum {
603 UNI_OFFLOAD_OFFLOAD_ARP,
604 UNI_OFFLOAD_OFFLOAD_ND,
605 UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
606 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
607};
608
609enum {
610 MT_NIC_CAP_TX_RESOURCE,
611 MT_NIC_CAP_TX_EFUSE_ADDR,
612 MT_NIC_CAP_COEX,
613 MT_NIC_CAP_SINGLE_SKU,
614 MT_NIC_CAP_CSUM_OFFLOAD,
615 MT_NIC_CAP_HW_VER,
616 MT_NIC_CAP_SW_VER,
617 MT_NIC_CAP_MAC_ADDR,
618 MT_NIC_CAP_PHY,
619 MT_NIC_CAP_MAC,
620 MT_NIC_CAP_FRAME_BUF,
621 MT_NIC_CAP_BEAM_FORM,
622 MT_NIC_CAP_LOCATION,
623 MT_NIC_CAP_MUMIMO,
624 MT_NIC_CAP_BUFFER_MODE_INFO,
625 MT_NIC_CAP_HW_ADIE_VERSION = 0x14,
626 MT_NIC_CAP_ANTSWP = 0x16,
627 MT_NIC_CAP_WFDMA_REALLOC,
628 MT_NIC_CAP_6G,
629};
630
631#define UNI_WOW_DETECT_TYPE_MAGIC BIT(0)
632#define UNI_WOW_DETECT_TYPE_ANY BIT(1)
633#define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2)
634#define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3)
635#define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4)
636#define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5)
637#define UNI_WOW_DETECT_TYPE_BITMAP BIT(6)
638
639enum {
640 UNI_SUSPEND_MODE_SETTING,
641 UNI_SUSPEND_WOW_CTRL,
642 UNI_SUSPEND_WOW_GPIO_PARAM,
643 UNI_SUSPEND_WOW_WAKEUP_PORT,
644 UNI_SUSPEND_WOW_PATTERN,
645};
646
647enum {
648 WOW_USB = 1,
649 WOW_PCIE = 2,
650 WOW_GPIO = 3,
651};
652
653struct mt76_connac_bss_basic_tlv {
654 __le16 tag;
655 __le16 len;
656 u8 active;
657 u8 omac_idx;
658 u8 hw_bss_idx;
659 u8 band_idx;
660 __le32 conn_type;
661 u8 conn_state;
662 u8 wmm_idx;
663 u8 bssid[ETH_ALEN];
664 __le16 bmc_tx_wlan_idx;
665 __le16 bcn_interval;
666 u8 dtim_period;
667 u8 phymode;
668
669
670
671
672
673
674
675
676
677 __le16 sta_idx;
678 __le16 nonht_basic_phy;
679 u8 phymode_ext;
680 u8 pad[1];
681} __packed;
682
683struct mt76_connac_bss_qos_tlv {
684 __le16 tag;
685 __le16 len;
686 u8 qos;
687 u8 pad[3];
688} __packed;
689
690struct mt76_connac_beacon_loss_event {
691 u8 bss_idx;
692 u8 reason;
693 u8 pad[2];
694} __packed;
695
696struct mt76_connac_mcu_bss_event {
697 u8 bss_idx;
698 u8 is_absent;
699 u8 free_quota;
700 u8 pad;
701} __packed;
702
703struct mt76_connac_mcu_scan_ssid {
704 __le32 ssid_len;
705 u8 ssid[IEEE80211_MAX_SSID_LEN];
706} __packed;
707
708struct mt76_connac_mcu_scan_channel {
709 u8 band;
710
711
712
713 u8 channel_num;
714} __packed;
715
716struct mt76_connac_mcu_scan_match {
717 __le32 rssi_th;
718 u8 ssid[IEEE80211_MAX_SSID_LEN];
719 u8 ssid_len;
720 u8 rsv[3];
721} __packed;
722
723struct mt76_connac_hw_scan_req {
724 u8 seq_num;
725 u8 bss_idx;
726 u8 scan_type;
727
728
729 u8 ssid_type;
730
731
732
733
734 u8 ssids_num;
735 u8 probe_req_num;
736 u8 scan_func;
737
738
739
740 u8 version;
741
742
743 struct mt76_connac_mcu_scan_ssid ssids[4];
744 __le16 probe_delay_time;
745 __le16 channel_dwell_time;
746 __le16 timeout_value;
747 u8 channel_type;
748
749
750
751
752
753
754 u8 channels_num;
755
756 struct mt76_connac_mcu_scan_channel channels[32];
757 __le16 ies_len;
758 u8 ies[MT76_CONNAC_SCAN_IE_LEN];
759
760 u8 ext_channels_num;
761 u8 ext_ssids_num;
762 __le16 channel_min_dwell_time;
763 struct mt76_connac_mcu_scan_channel ext_channels[32];
764 struct mt76_connac_mcu_scan_ssid ext_ssids[6];
765 u8 bssid[ETH_ALEN];
766 u8 random_mac[ETH_ALEN];
767 u8 pad[63];
768 u8 ssid_type_ext;
769} __packed;
770
771#define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64
772
773struct mt76_connac_hw_scan_done {
774 u8 seq_num;
775 u8 sparse_channel_num;
776 struct mt76_connac_mcu_scan_channel sparse_channel;
777 u8 complete_channel_num;
778 u8 current_state;
779 u8 version;
780 u8 pad;
781 __le32 beacon_scan_num;
782 u8 pno_enabled;
783 u8 pad2[3];
784 u8 sparse_channel_valid_num;
785 u8 pad3[3];
786 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
787
788
789
790
791
792 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
793
794 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
795 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
796 __le32 beacon_2g_num;
797 __le32 beacon_5g_num;
798} __packed;
799
800struct mt76_connac_sched_scan_req {
801 u8 version;
802 u8 seq_num;
803 u8 stop_on_match;
804 u8 ssids_num;
805 u8 match_num;
806 u8 pad;
807 __le16 ie_len;
808 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
809 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
810 u8 channel_type;
811 u8 channels_num;
812 u8 intervals_num;
813 u8 scan_func;
814 struct mt76_connac_mcu_scan_channel channels[64];
815 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL];
816 union {
817 struct {
818 u8 random_mac[ETH_ALEN];
819 u8 pad2[58];
820 } mt7663;
821 struct {
822 u8 bss_idx;
823 u8 pad1[3];
824 __le32 delay;
825 u8 pad2[12];
826 u8 random_mac[ETH_ALEN];
827 u8 pad3[38];
828 } mt7921;
829 };
830} __packed;
831
832struct mt76_connac_sched_scan_done {
833 u8 seq_num;
834 u8 status;
835 __le16 pad;
836} __packed;
837
838struct bss_info_uni_bss_color {
839 __le16 tag;
840 __le16 len;
841 u8 enable;
842 u8 bss_color;
843 u8 rsv[2];
844} __packed;
845
846struct bss_info_uni_he {
847 __le16 tag;
848 __le16 len;
849 __le16 he_rts_thres;
850 u8 he_pe_duration;
851 u8 su_disable;
852 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
853 u8 rsv[2];
854} __packed;
855
856struct mt76_connac_gtk_rekey_tlv {
857 __le16 tag;
858 __le16 len;
859 u8 kek[NL80211_KEK_LEN];
860 u8 kck[NL80211_KCK_LEN];
861 u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
862 u8 rekey_mode;
863
864
865
866 u8 keyid;
867 u8 option;
868 u8 pad[1];
869 __le32 proto;
870 __le32 pairwise_cipher;
871 __le32 group_cipher;
872 __le32 key_mgmt;
873 __le32 mgmt_group_cipher;
874 u8 reserverd[4];
875} __packed;
876
877#define MT76_CONNAC_WOW_MASK_MAX_LEN 16
878#define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128
879
880struct mt76_connac_wow_pattern_tlv {
881 __le16 tag;
882 __le16 len;
883 u8 index;
884 u8 enable;
885
886
887 u8 data_len;
888 u8 pad;
889 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
890 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
891 u8 rsv[4];
892} __packed;
893
894struct mt76_connac_wow_ctrl_tlv {
895 __le16 tag;
896 __le16 len;
897 u8 cmd;
898
899
900
901 u8 trigger;
902
903
904
905
906
907
908
909 u8 wakeup_hif;
910
911
912
913
914 u8 pad;
915 u8 rsv[4];
916} __packed;
917
918struct mt76_connac_wow_gpio_param_tlv {
919 __le16 tag;
920 __le16 len;
921 u8 gpio_pin;
922 u8 trigger_lvl;
923 u8 pad[2];
924 __le32 gpio_interval;
925 u8 rsv[4];
926} __packed;
927
928struct mt76_connac_arpns_tlv {
929 __le16 tag;
930 __le16 len;
931 u8 mode;
932 u8 ips_num;
933 u8 option;
934 u8 pad[1];
935} __packed;
936
937struct mt76_connac_suspend_tlv {
938 __le16 tag;
939 __le16 len;
940 u8 enable;
941
942
943 u8 mdtim;
944 u8 wow_suspend;
945
946
947 u8 pad[5];
948} __packed;
949
950enum mt76_sta_info_state {
951 MT76_STA_INFO_STATE_NONE,
952 MT76_STA_INFO_STATE_AUTH,
953 MT76_STA_INFO_STATE_ASSOC
954};
955
956struct mt76_sta_cmd_info {
957 struct ieee80211_sta *sta;
958 struct mt76_wcid *wcid;
959
960 struct ieee80211_vif *vif;
961
962 bool offload_fw;
963 bool enable;
964 bool newly;
965 int cmd;
966 u8 rcpi;
967 u8 state;
968};
969
970#define MT_SKU_POWER_LIMIT 161
971
972struct mt76_connac_sku_tlv {
973 u8 channel;
974 s8 pwr_limit[MT_SKU_POWER_LIMIT];
975} __packed;
976
977struct mt76_connac_tx_power_limit_tlv {
978
979 u8 ver;
980 u8 pad0;
981 __le16 len;
982
983 u8 n_chan;
984 u8 band;
985 u8 last_msg;
986 u8 pad1;
987
988 u8 alpha2[4];
989 u8 pad2[32];
990} __packed;
991
992struct mt76_connac_config {
993 __le16 id;
994 u8 type;
995 u8 resp_type;
996 __le16 data_size;
997 __le16 resv;
998 u8 data[320];
999} __packed;
1000
1001#define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1002#define to_wcid_hi(id) FIELD_GET(GENMASK(9, 8), (u16)id)
1003
1004static inline void
1005mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
1006 u8 *wlan_idx_lo, u8 *wlan_idx_hi)
1007{
1008 *wlan_idx_hi = 0;
1009
1010 if (is_mt7921(dev)) {
1011 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
1012 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
1013 } else {
1014 *wlan_idx_lo = wcid ? wcid->idx : 0;
1015 }
1016}
1017
1018struct sk_buff *
1019mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif *mvif,
1020 struct mt76_wcid *wcid);
1021struct wtbl_req_hdr *
1022mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
1023 int cmd, void *sta_wtbl, struct sk_buff **skb);
1024struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
1025 int len, void *sta_ntlv,
1026 void *sta_wtbl);
1027static inline struct tlv *
1028mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
1029{
1030 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
1031}
1032
1033int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
1034int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
1035void mt76_connac_mcu_sta_basic_tlv(struct sk_buff *skb,
1036 struct ieee80211_vif *vif,
1037 struct ieee80211_sta *sta, bool enable,
1038 bool newly);
1039void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1040 struct ieee80211_vif *vif,
1041 struct ieee80211_sta *sta, void *sta_wtbl,
1042 void *wtbl_tlv);
1043void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb,
1044 struct ieee80211_vif *vif,
1045 struct mt76_wcid *wcid,
1046 void *sta_wtbl, void *wtbl_tlv);
1047int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev,
1048 struct ieee80211_vif *vif,
1049 struct mt76_wcid *wcid, int cmd);
1050void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
1051 struct ieee80211_sta *sta,
1052 struct ieee80211_vif *vif,
1053 u8 rcpi, u8 state);
1054void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1055 struct ieee80211_sta *sta, void *sta_wtbl,
1056 void *wtbl_tlv);
1057void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
1058 struct ieee80211_ampdu_params *params,
1059 bool enable, bool tx, void *sta_wtbl,
1060 void *wtbl_tlv);
1061void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
1062 struct ieee80211_ampdu_params *params,
1063 bool enable, bool tx);
1064int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
1065 struct ieee80211_vif *vif,
1066 struct mt76_wcid *wcid,
1067 bool enable);
1068int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif,
1069 struct ieee80211_ampdu_params *params,
1070 bool enable, bool tx);
1071int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
1072 struct ieee80211_vif *vif,
1073 struct mt76_wcid *wcid,
1074 bool enable);
1075int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy,
1076 struct mt76_sta_cmd_info *info);
1077void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
1078 struct ieee80211_vif *vif);
1079int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
1080int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
1081 bool hdr_trans);
1082int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
1083 u32 mode);
1084int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
1085int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
1086int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
1087int mt76_connac_mcu_get_nic_capability(struct mt76_phy *phy);
1088
1089int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
1090 struct ieee80211_scan_request *scan_req);
1091int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
1092 struct ieee80211_vif *vif);
1093int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
1094 struct ieee80211_vif *vif,
1095 struct cfg80211_sched_scan_request *sreq);
1096int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
1097 struct ieee80211_vif *vif,
1098 bool enable);
1099int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev,
1100 struct mt76_vif *vif,
1101 struct ieee80211_bss_conf *info);
1102int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
1103 struct ieee80211_vif *vif,
1104 struct cfg80211_gtk_rekey_data *key);
1105int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend);
1106void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
1107 struct ieee80211_vif *vif);
1108int mt76_connac_sta_state_dp(struct mt76_dev *dev,
1109 enum ieee80211_sta_state old_state,
1110 enum ieee80211_sta_state new_state);
1111int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
1112int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable);
1113void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
1114 struct mt76_connac_coredump *coredump);
1115int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy);
1116int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw,
1117 struct ieee80211_vif *vif);
1118u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
1119void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
1120#endif
1121
