1
2
3
4#include "../wifi.h"
5#include "../base.h"
6#include "../core.h"
7#include "reg.h"
8#include "def.h"
9#include "phy.h"
10#include "dm.h"
11#include "fw.h"
12
13#define UNDEC_SM_PWDB entry_min_undec_sm_pwdb
14
15static const u32 ofdmswing_table[OFDM_TABLE_SIZE_92D] = {
16 0x7f8001fe,
17 0x788001e2,
18 0x71c001c7,
19 0x6b8001ae,
20 0x65400195,
21 0x5fc0017f,
22 0x5a400169,
23 0x55400155,
24 0x50800142,
25 0x4c000130,
26 0x47c0011f,
27 0x43c0010f,
28 0x40000100,
29 0x3c8000f2,
30 0x390000e4,
31 0x35c000d7,
32 0x32c000cb,
33 0x300000c0,
34 0x2d4000b5,
35 0x2ac000ab,
36 0x288000a2,
37 0x26000098,
38 0x24000090,
39 0x22000088,
40 0x20000080,
41 0x1e400079,
42 0x1c800072,
43 0x1b00006c,
44 0x19800066,
45 0x18000060,
46 0x16c0005b,
47 0x15800056,
48 0x14400051,
49 0x1300004c,
50 0x12000048,
51 0x11000044,
52 0x10000040,
53 0x0f00003c,
54 0x0e400039,
55 0x0d800036,
56 0x0cc00033,
57 0x0c000030,
58 0x0b40002d,
59};
60
61static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
62 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
63 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
64 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
65 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
66 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
67 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
68 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
69 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
70 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
71 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
72 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
73 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
74 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
75 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
76 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
77 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
78 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
79 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
80 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
81 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
82 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
83 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
84 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
85 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
86 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
87 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
88 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
89 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
90 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
91 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
92 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
93 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
94 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
95};
96
97static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
98 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
99 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
100 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
101 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
102 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
103 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
104 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
105 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
106 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
107 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
108 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
109 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
110 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
111 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
112 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
113 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
114 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
115 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
116 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
117 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
118 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
119 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
120 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
121 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
122 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
123 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
124 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
125 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
126 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
127 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
128 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
129 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
130 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
131};
132
133static void rtl92d_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
134{
135 u32 ret_value;
136 struct rtl_priv *rtlpriv = rtl_priv(hw);
137 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
138 unsigned long flag = 0;
139
140
141 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 1);
142 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 1);
143
144 ret_value = rtl_get_bbreg(hw, ROFDM0_FRAMESYNC, MASKDWORD);
145 falsealm_cnt->cnt_fast_fsync_fail = (ret_value & 0xffff);
146 falsealm_cnt->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
147 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
148 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
149 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
150 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
151 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
152 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
153 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
154 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
155 falsealm_cnt->cnt_rate_illegal +
156 falsealm_cnt->cnt_crc8_fail +
157 falsealm_cnt->cnt_mcs_fail +
158 falsealm_cnt->cnt_fast_fsync_fail +
159 falsealm_cnt->cnt_sb_search_fail;
160
161 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
162
163 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
164 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
165 falsealm_cnt->cnt_cck_fail = ret_value;
166 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
167 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
168 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
169 } else {
170 falsealm_cnt->cnt_cck_fail = 0;
171 }
172
173
174 falsealm_cnt->cnt_all = falsealm_cnt->cnt_fast_fsync_fail +
175 falsealm_cnt->cnt_sb_search_fail +
176 falsealm_cnt->cnt_parity_fail +
177 falsealm_cnt->cnt_rate_illegal +
178 falsealm_cnt->cnt_crc8_fail +
179 falsealm_cnt->cnt_mcs_fail +
180 falsealm_cnt->cnt_cck_fail;
181
182 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
183
184 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
185
186 rtl_set_bbreg(hw, ROFDM0_LSTF, BIT(31), 0);
187
188 rtl_set_bbreg(hw, ROFDM1_LSTF, BIT(31), 0);
189 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G) {
190
191 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
192 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
193
194 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
195 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
196 }
197 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
198 "Cnt_Fast_Fsync_fail = %x, Cnt_SB_Search_fail = %x\n",
199 falsealm_cnt->cnt_fast_fsync_fail,
200 falsealm_cnt->cnt_sb_search_fail);
201 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
202 "Cnt_Parity_Fail = %x, Cnt_Rate_Illegal = %x, Cnt_Crc8_fail = %x, Cnt_Mcs_fail = %x\n",
203 falsealm_cnt->cnt_parity_fail,
204 falsealm_cnt->cnt_rate_illegal,
205 falsealm_cnt->cnt_crc8_fail,
206 falsealm_cnt->cnt_mcs_fail);
207 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
208 "Cnt_Ofdm_fail = %x, Cnt_Cck_fail = %x, Cnt_all = %x\n",
209 falsealm_cnt->cnt_ofdm_fail,
210 falsealm_cnt->cnt_cck_fail,
211 falsealm_cnt->cnt_all);
212}
213
214static void rtl92d_dm_find_minimum_rssi(struct ieee80211_hw *hw)
215{
216 struct rtl_priv *rtlpriv = rtl_priv(hw);
217 struct dig_t *de_digtable = &rtlpriv->dm_digtable;
218 struct rtl_mac *mac = rtl_mac(rtlpriv);
219
220
221 if ((mac->link_state < MAC80211_LINKED) &&
222 (rtlpriv->dm.UNDEC_SM_PWDB == 0)) {
223 de_digtable->min_undec_pwdb_for_dm = 0;
224 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
225 "Not connected to any\n");
226 }
227 if (mac->link_state >= MAC80211_LINKED) {
228 if (mac->opmode == NL80211_IFTYPE_AP ||
229 mac->opmode == NL80211_IFTYPE_ADHOC) {
230 de_digtable->min_undec_pwdb_for_dm =
231 rtlpriv->dm.UNDEC_SM_PWDB;
232 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
233 "AP Client PWDB = 0x%lx\n",
234 rtlpriv->dm.UNDEC_SM_PWDB);
235 } else {
236 de_digtable->min_undec_pwdb_for_dm =
237 rtlpriv->dm.undec_sm_pwdb;
238 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
239 "STA Default Port PWDB = 0x%x\n",
240 de_digtable->min_undec_pwdb_for_dm);
241 }
242 } else {
243 de_digtable->min_undec_pwdb_for_dm = rtlpriv->dm.UNDEC_SM_PWDB;
244 rtl_dbg(rtlpriv, COMP_BB_POWERSAVING, DBG_LOUD,
245 "AP Ext Port or disconnect PWDB = 0x%x\n",
246 de_digtable->min_undec_pwdb_for_dm);
247 }
248
249 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "MinUndecoratedPWDBForDM =%d\n",
250 de_digtable->min_undec_pwdb_for_dm);
251}
252
253static void rtl92d_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
254{
255 struct rtl_priv *rtlpriv = rtl_priv(hw);
256 struct dig_t *de_digtable = &rtlpriv->dm_digtable;
257 unsigned long flag = 0;
258
259 if (de_digtable->cursta_cstate == DIG_STA_CONNECT) {
260 if (de_digtable->pre_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
261 if (de_digtable->min_undec_pwdb_for_dm <= 25)
262 de_digtable->cur_cck_pd_state =
263 CCK_PD_STAGE_LOWRSSI;
264 else
265 de_digtable->cur_cck_pd_state =
266 CCK_PD_STAGE_HIGHRSSI;
267 } else {
268 if (de_digtable->min_undec_pwdb_for_dm <= 20)
269 de_digtable->cur_cck_pd_state =
270 CCK_PD_STAGE_LOWRSSI;
271 else
272 de_digtable->cur_cck_pd_state =
273 CCK_PD_STAGE_HIGHRSSI;
274 }
275 } else {
276 de_digtable->cur_cck_pd_state = CCK_PD_STAGE_LOWRSSI;
277 }
278 if (de_digtable->pre_cck_pd_state != de_digtable->cur_cck_pd_state) {
279 if (de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI) {
280 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
281 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x83);
282 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
283 } else {
284 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
285 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
286 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
287 }
288 de_digtable->pre_cck_pd_state = de_digtable->cur_cck_pd_state;
289 }
290 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CurSTAConnectState=%s\n",
291 de_digtable->cursta_cstate == DIG_STA_CONNECT ?
292 "DIG_STA_CONNECT " : "DIG_STA_DISCONNECT");
293 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "CCKPDStage=%s\n",
294 de_digtable->cur_cck_pd_state == CCK_PD_STAGE_LOWRSSI ?
295 "Low RSSI " : "High RSSI ");
296 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "is92d single phy =%x\n",
297 IS_92D_SINGLEPHY(rtlpriv->rtlhal.version));
298
299}
300
301void rtl92d_dm_write_dig(struct ieee80211_hw *hw)
302{
303 struct rtl_priv *rtlpriv = rtl_priv(hw);
304 struct dig_t *de_digtable = &rtlpriv->dm_digtable;
305
306 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
307 "cur_igvalue = 0x%x, pre_igvalue = 0x%x, back_val = %d\n",
308 de_digtable->cur_igvalue, de_digtable->pre_igvalue,
309 de_digtable->back_val);
310 if (de_digtable->dig_enable_flag == false) {
311 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "DIG is disabled\n");
312 de_digtable->pre_igvalue = 0x17;
313 return;
314 }
315 if (de_digtable->pre_igvalue != de_digtable->cur_igvalue) {
316 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
317 de_digtable->cur_igvalue);
318 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
319 de_digtable->cur_igvalue);
320 de_digtable->pre_igvalue = de_digtable->cur_igvalue;
321 }
322}
323
324static void rtl92d_early_mode_enabled(struct rtl_priv *rtlpriv)
325{
326 struct dig_t *de_digtable = &rtlpriv->dm_digtable;
327
328 if ((rtlpriv->mac80211.link_state >= MAC80211_LINKED) &&
329 (rtlpriv->mac80211.vendor == PEER_CISCO)) {
330 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "IOT_PEER = CISCO\n");
331 if (de_digtable->last_min_undec_pwdb_for_dm >= 50
332 && de_digtable->min_undec_pwdb_for_dm < 50) {
333 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x00);
334 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
335 "Early Mode Off\n");
336 } else if (de_digtable->last_min_undec_pwdb_for_dm <= 55 &&
337 de_digtable->min_undec_pwdb_for_dm > 55) {
338 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f);
339 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
340 "Early Mode On\n");
341 }
342 } else if (!(rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL) & 0xf)) {
343 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, 0x0f);
344 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "Early Mode On\n");
345 }
346}
347
348static void rtl92d_dm_dig(struct ieee80211_hw *hw)
349{
350 struct rtl_priv *rtlpriv = rtl_priv(hw);
351 struct dig_t *de_digtable = &rtlpriv->dm_digtable;
352 u8 value_igi = de_digtable->cur_igvalue;
353 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
354
355 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "==>\n");
356 if (rtlpriv->rtlhal.earlymode_enable) {
357 rtl92d_early_mode_enabled(rtlpriv);
358 de_digtable->last_min_undec_pwdb_for_dm =
359 de_digtable->min_undec_pwdb_for_dm;
360 }
361 if (!rtlpriv->dm.dm_initialgain_enable)
362 return;
363
364
365
366
367
368
369
370
371
372 if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
373 return;
374 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "progress\n");
375
376 if (rtlpriv->mac80211.link_state >= MAC80211_LINKED)
377 de_digtable->cursta_cstate = DIG_STA_CONNECT;
378 else
379 de_digtable->cursta_cstate = DIG_STA_DISCONNECT;
380
381
382 if (falsealm_cnt->cnt_all < DM_DIG_FA_TH0)
383 value_igi--;
384 else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH1)
385 value_igi += 0;
386 else if (falsealm_cnt->cnt_all < DM_DIG_FA_TH2)
387 value_igi++;
388 else if (falsealm_cnt->cnt_all >= DM_DIG_FA_TH2)
389 value_igi += 2;
390 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
391 "dm_DIG() Before: large_fa_hit=%d, forbidden_igi=%x\n",
392 de_digtable->large_fa_hit, de_digtable->forbidden_igi);
393 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
394 "dm_DIG() Before: Recover_cnt=%d, rx_gain_min=%x\n",
395 de_digtable->recover_cnt, de_digtable->rx_gain_min);
396
397
398 if (falsealm_cnt->cnt_all > 10000) {
399 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
400 "dm_DIG(): Abnormally false alarm case\n");
401
402 de_digtable->large_fa_hit++;
403 if (de_digtable->forbidden_igi < de_digtable->cur_igvalue) {
404 de_digtable->forbidden_igi = de_digtable->cur_igvalue;
405 de_digtable->large_fa_hit = 1;
406 }
407 if (de_digtable->large_fa_hit >= 3) {
408 if ((de_digtable->forbidden_igi + 1) > DM_DIG_MAX)
409 de_digtable->rx_gain_min = DM_DIG_MAX;
410 else
411 de_digtable->rx_gain_min =
412 (de_digtable->forbidden_igi + 1);
413 de_digtable->recover_cnt = 3600;
414 }
415 } else {
416
417 if (de_digtable->recover_cnt != 0) {
418 de_digtable->recover_cnt--;
419 } else {
420 if (de_digtable->large_fa_hit == 0) {
421 if ((de_digtable->forbidden_igi - 1) <
422 DM_DIG_FA_LOWER) {
423 de_digtable->forbidden_igi =
424 DM_DIG_FA_LOWER;
425 de_digtable->rx_gain_min =
426 DM_DIG_FA_LOWER;
427
428 } else {
429 de_digtable->forbidden_igi--;
430 de_digtable->rx_gain_min =
431 (de_digtable->forbidden_igi + 1);
432 }
433 } else if (de_digtable->large_fa_hit == 3) {
434 de_digtable->large_fa_hit = 0;
435 }
436 }
437 }
438 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
439 "dm_DIG() After: large_fa_hit=%d, forbidden_igi=%x\n",
440 de_digtable->large_fa_hit, de_digtable->forbidden_igi);
441 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD,
442 "dm_DIG() After: recover_cnt=%d, rx_gain_min=%x\n",
443 de_digtable->recover_cnt, de_digtable->rx_gain_min);
444
445 if (value_igi > DM_DIG_MAX)
446 value_igi = DM_DIG_MAX;
447 else if (value_igi < de_digtable->rx_gain_min)
448 value_igi = de_digtable->rx_gain_min;
449 de_digtable->cur_igvalue = value_igi;
450 rtl92d_dm_write_dig(hw);
451 if (rtlpriv->rtlhal.current_bandtype != BAND_ON_5G)
452 rtl92d_dm_cck_packet_detection_thresh(hw);
453 rtl_dbg(rtlpriv, COMP_DIG, DBG_LOUD, "<<==\n");
454}
455
456static void rtl92d_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
457{
458 struct rtl_priv *rtlpriv = rtl_priv(hw);
459
460 rtlpriv->dm.dynamic_txpower_enable = true;
461 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
462 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
463}
464
465static void rtl92d_dm_dynamic_txpower(struct ieee80211_hw *hw)
466{
467 struct rtl_priv *rtlpriv = rtl_priv(hw);
468 struct rtl_phy *rtlphy = &(rtlpriv->phy);
469 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
470 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
471 long undec_sm_pwdb;
472
473 if ((!rtlpriv->dm.dynamic_txpower_enable)
474 || rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
475 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
476 return;
477 }
478 if ((mac->link_state < MAC80211_LINKED) &&
479 (rtlpriv->dm.UNDEC_SM_PWDB == 0)) {
480 rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE,
481 "Not connected to any\n");
482 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
483 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
484 return;
485 }
486 if (mac->link_state >= MAC80211_LINKED) {
487 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
488 undec_sm_pwdb =
489 rtlpriv->dm.UNDEC_SM_PWDB;
490 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
491 "IBSS Client PWDB = 0x%lx\n",
492 undec_sm_pwdb);
493 } else {
494 undec_sm_pwdb =
495 rtlpriv->dm.undec_sm_pwdb;
496 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
497 "STA Default Port PWDB = 0x%lx\n",
498 undec_sm_pwdb);
499 }
500 } else {
501 undec_sm_pwdb =
502 rtlpriv->dm.UNDEC_SM_PWDB;
503
504 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
505 "AP Ext Port PWDB = 0x%lx\n",
506 undec_sm_pwdb);
507 }
508 if (rtlhal->current_bandtype == BAND_ON_5G) {
509 if (undec_sm_pwdb >= 0x33) {
510 rtlpriv->dm.dynamic_txhighpower_lvl =
511 TXHIGHPWRLEVEL_LEVEL2;
512 rtl_dbg(rtlpriv, COMP_HIPWR, DBG_LOUD,
513 "5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n");
514 } else if ((undec_sm_pwdb < 0x33)
515 && (undec_sm_pwdb >= 0x2b)) {
516 rtlpriv->dm.dynamic_txhighpower_lvl =
517 TXHIGHPWRLEVEL_LEVEL1;
518 rtl_dbg(rtlpriv, COMP_HIPWR, DBG_LOUD,
519 "5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n");
520 } else if (undec_sm_pwdb < 0x2b) {
521 rtlpriv->dm.dynamic_txhighpower_lvl =
522 TXHIGHPWRLEVEL_NORMAL;
523 rtl_dbg(rtlpriv, COMP_HIPWR, DBG_LOUD,
524 "5G:TxHighPwrLevel_Normal\n");
525 }
526 } else {
527 if (undec_sm_pwdb >=
528 TX_POWER_NEAR_FIELD_THRESH_LVL2) {
529 rtlpriv->dm.dynamic_txhighpower_lvl =
530 TXHIGHPWRLEVEL_LEVEL2;
531 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
532 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
533 } else
534 if ((undec_sm_pwdb <
535 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3))
536 && (undec_sm_pwdb >=
537 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
538
539 rtlpriv->dm.dynamic_txhighpower_lvl =
540 TXHIGHPWRLEVEL_LEVEL1;
541 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
542 "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
543 } else if (undec_sm_pwdb <
544 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
545 rtlpriv->dm.dynamic_txhighpower_lvl =
546 TXHIGHPWRLEVEL_NORMAL;
547 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
548 "TXHIGHPWRLEVEL_NORMAL\n");
549 }
550 }
551 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
552 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
553 "PHY_SetTxPowerLevel8192S() Channel = %d\n",
554 rtlphy->current_channel);
555 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
556 }
557 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
558}
559
560static void rtl92d_dm_pwdb_monitor(struct ieee80211_hw *hw)
561{
562 struct rtl_priv *rtlpriv = rtl_priv(hw);
563
564
565 if (rtlpriv->mac80211.opmode != NL80211_IFTYPE_STATION)
566 return;
567
568 if (rtlpriv->dm.useramask) {
569 u32 temp = rtlpriv->dm.undec_sm_pwdb;
570
571 temp <<= 16;
572 temp |= 0x100;
573
574
575 rtl92d_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, (u8 *) (&temp));
576 } else {
577 rtl_write_byte(rtlpriv, 0x4fe,
578 (u8) rtlpriv->dm.undec_sm_pwdb);
579 }
580}
581
582void rtl92d_dm_init_edca_turbo(struct ieee80211_hw *hw)
583{
584 struct rtl_priv *rtlpriv = rtl_priv(hw);
585
586 rtlpriv->dm.current_turbo_edca = false;
587 rtlpriv->dm.is_any_nonbepkts = false;
588 rtlpriv->dm.is_cur_rdlstate = false;
589}
590
591static void rtl92d_dm_check_edca_turbo(struct ieee80211_hw *hw)
592{
593 struct rtl_priv *rtlpriv = rtl_priv(hw);
594 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
595 static u64 last_txok_cnt;
596 static u64 last_rxok_cnt;
597 u64 cur_txok_cnt;
598 u64 cur_rxok_cnt;
599 u32 edca_be_ul = 0x5ea42b;
600 u32 edca_be_dl = 0x5ea42b;
601
602 if (mac->link_state != MAC80211_LINKED) {
603 rtlpriv->dm.current_turbo_edca = false;
604 goto exit;
605 }
606
607
608
609 if ((!rtlpriv->dm.disable_framebursting) &&
610 (rtlpriv->sec.pairwise_enc_algorithm == WEP40_ENCRYPTION ||
611 rtlpriv->sec.pairwise_enc_algorithm == WEP104_ENCRYPTION ||
612 rtlpriv->sec.pairwise_enc_algorithm == TKIP_ENCRYPTION)) {
613
614 if (!(edca_be_ul & 0xffff0000))
615 edca_be_ul |= 0x005e0000;
616
617 if (!(edca_be_dl & 0xffff0000))
618 edca_be_dl |= 0x005e0000;
619 }
620
621 if ((!rtlpriv->dm.is_any_nonbepkts) &&
622 (!rtlpriv->dm.disable_framebursting)) {
623 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
624 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
625 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
626 if (!rtlpriv->dm.is_cur_rdlstate ||
627 !rtlpriv->dm.current_turbo_edca) {
628 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
629 edca_be_dl);
630 rtlpriv->dm.is_cur_rdlstate = true;
631 }
632 } else {
633 if (rtlpriv->dm.is_cur_rdlstate ||
634 !rtlpriv->dm.current_turbo_edca) {
635 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
636 edca_be_ul);
637 rtlpriv->dm.is_cur_rdlstate = false;
638 }
639 }
640 rtlpriv->dm.current_turbo_edca = true;
641 } else {
642 if (rtlpriv->dm.current_turbo_edca) {
643 u8 tmp = AC0_BE;
644 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
645 &tmp);
646 rtlpriv->dm.current_turbo_edca = false;
647 }
648 }
649
650exit:
651 rtlpriv->dm.is_any_nonbepkts = false;
652 last_txok_cnt = rtlpriv->stats.txbytesunicast;
653 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
654}
655
656static void rtl92d_dm_rxgain_tracking_thermalmeter(struct ieee80211_hw *hw)
657{
658 struct rtl_priv *rtlpriv = rtl_priv(hw);
659 u8 index_mapping[RX_INDEX_MAPPING_NUM] = {
660 0x0f, 0x0f, 0x0d, 0x0c, 0x0b,
661 0x0a, 0x09, 0x08, 0x07, 0x06,
662 0x05, 0x04, 0x04, 0x03, 0x02
663 };
664 int i;
665 u32 u4tmp;
666
667 u4tmp = (index_mapping[(rtlpriv->efuse.eeprom_thermalmeter -
668 rtlpriv->dm.thermalvalue_rxgain)]) << 12;
669 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
670 "===> Rx Gain %x\n", u4tmp);
671 for (i = RF90_PATH_A; i < rtlpriv->phy.num_total_rfpath; i++)
672 rtl_set_rfreg(hw, i, 0x3C, RFREG_OFFSET_MASK,
673 (rtlpriv->phy.reg_rf3c[i] & (~(0xF000))) | u4tmp);
674}
675
676static void rtl92d_bandtype_2_4G(struct ieee80211_hw *hw, long *temp_cckg,
677 u8 *cck_index_old)
678{
679 struct rtl_priv *rtlpriv = rtl_priv(hw);
680 int i;
681 unsigned long flag = 0;
682 long temp_cck;
683 const u8 *cckswing;
684
685
686 rtl92d_acquire_cckandrw_pagea_ctl(hw, &flag);
687 temp_cck = rtl_get_bbreg(hw, RCCK0_TXFILTER2,
688 MASKDWORD) & MASKCCK;
689 rtl92d_release_cckandrw_pagea_ctl(hw, &flag);
690 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
691 if (rtlpriv->dm.cck_inch14)
692 cckswing = &cckswing_table_ch14[i][2];
693 else
694 cckswing = &cckswing_table_ch1ch13[i][2];
695
696 if (temp_cck == le32_to_cpu(*((__le32 *)cckswing))) {
697 *cck_index_old = (u8)i;
698 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
699 "Initial reg0x%x = 0x%lx, cck_index = 0x%x, ch14 %d\n",
700 RCCK0_TXFILTER2, temp_cck,
701 *cck_index_old,
702 rtlpriv->dm.cck_inch14);
703 break;
704 }
705 }
706 *temp_cckg = temp_cck;
707}
708
709static void rtl92d_bandtype_5G(struct rtl_hal *rtlhal, u8 *ofdm_index,
710 bool *internal_pa, u8 thermalvalue, u8 delta,
711 u8 rf, struct rtl_efuse *rtlefuse,
712 struct rtl_priv *rtlpriv, struct rtl_phy *rtlphy,
713 const u8 index_mapping[5][INDEX_MAPPING_NUM],
714 const u8 index_mapping_pa[8][INDEX_MAPPING_NUM])
715{
716 int i;
717 u8 index;
718 u8 offset = 0;
719
720 for (i = 0; i < rf; i++) {
721 if (rtlhal->macphymode == DUALMAC_DUALPHY &&
722 rtlhal->interfaceindex == 1)
723 *internal_pa = rtlefuse->internal_pa_5g[1];
724 else
725 *internal_pa = rtlefuse->internal_pa_5g[i];
726 if (*internal_pa) {
727 if (rtlhal->interfaceindex == 1 || i == rf)
728 offset = 4;
729 else
730 offset = 0;
731 if (rtlphy->current_channel >= 100 &&
732 rtlphy->current_channel <= 165)
733 offset += 2;
734 } else {
735 if (rtlhal->interfaceindex == 1 || i == rf)
736 offset = 2;
737 else
738 offset = 0;
739 }
740 if (thermalvalue > rtlefuse->eeprom_thermalmeter)
741 offset++;
742 if (*internal_pa) {
743 if (delta > INDEX_MAPPING_NUM - 1)
744 index = index_mapping_pa[offset]
745 [INDEX_MAPPING_NUM - 1];
746 else
747 index =
748 index_mapping_pa[offset][delta];
749 } else {
750 if (delta > INDEX_MAPPING_NUM - 1)
751 index =
752 index_mapping[offset][INDEX_MAPPING_NUM - 1];
753 else
754 index = index_mapping[offset][delta];
755 }
756 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
757 if (*internal_pa && thermalvalue > 0x12) {
758 ofdm_index[i] = rtlpriv->dm.ofdm_index[i] -
759 ((delta / 2) * 3 + (delta % 2));
760 } else {
761 ofdm_index[i] -= index;
762 }
763 } else {
764 ofdm_index[i] += index;
765 }
766 }
767}
768
769static void rtl92d_dm_txpower_tracking_callback_thermalmeter(
770 struct ieee80211_hw *hw)
771{
772 struct rtl_priv *rtlpriv = rtl_priv(hw);
773 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
774 struct rtl_phy *rtlphy = &(rtlpriv->phy);
775 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
776 u8 thermalvalue, delta, delta_lck, delta_iqk, delta_rxgain;
777 u8 offset, thermalvalue_avg_count = 0;
778 u32 thermalvalue_avg = 0;
779 bool internal_pa = false;
780 long ele_a = 0, ele_d, temp_cck, val_x, value32;
781 long val_y, ele_c = 0;
782 u8 ofdm_index[2];
783 s8 cck_index = 0;
784 u8 ofdm_index_old[2] = {0, 0};
785 s8 cck_index_old = 0;
786 u8 index;
787 int i;
788 bool is2t = IS_92D_SINGLEPHY(rtlhal->version);
789 u8 ofdm_min_index = 6, ofdm_min_index_internal_pa = 3, rf;
790 u8 indexforchannel =
791 rtl92d_get_rightchnlplace_for_iqk(rtlphy->current_channel);
792 static const u8 index_mapping[5][INDEX_MAPPING_NUM] = {
793
794 {0, 1, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18},
795
796 {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
797
798 {0, 2, 3, 6, 8, 9, 11, 13, 14, 16, 17, 18, 18},
799
800 {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
801
802 {0, 1, 2, 3, 4, 5, 6, 7, 7, 8, 9, 10, 10},
803 };
804 static const u8 index_mapping_internal_pa[8][INDEX_MAPPING_NUM] = {
805
806 {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16},
807
808 {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
809
810 {0, 1, 2, 3, 5, 6, 8, 10, 11, 13, 14, 15, 15},
811
812 {0, 2, 4, 5, 7, 10, 12, 14, 16, 18, 18, 18, 18},
813
814 {0, 1, 2, 4, 6, 7, 9, 11, 12, 14, 15, 16, 16},
815
816 {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
817
818 {0, 1, 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 14},
819
820 {0, 2, 4, 5, 7, 10, 13, 16, 16, 18, 18, 18, 18},
821 };
822
823 rtlpriv->dm.txpower_trackinginit = true;
824 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "\n");
825 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0xf800);
826 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
827 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
828 thermalvalue,
829 rtlpriv->dm.thermalvalue, rtlefuse->eeprom_thermalmeter);
830 rtl92d_phy_ap_calibrate(hw, (thermalvalue -
831 rtlefuse->eeprom_thermalmeter));
832
833 if (!thermalvalue)
834 goto exit;
835
836 if (is2t)
837 rf = 2;
838 else
839 rf = 1;
840
841 if (rtlpriv->dm.thermalvalue && !rtlhal->reloadtxpowerindex)
842 goto old_index_done;
843
844 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD) & MASKOFDM_D;
845 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
846 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
847 ofdm_index_old[0] = (u8)i;
848
849 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
850 "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
851 ROFDM0_XATXIQIMBALANCE,
852 ele_d, ofdm_index_old[0]);
853 break;
854 }
855 }
856 if (is2t) {
857 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
858 MASKDWORD) & MASKOFDM_D;
859 for (i = 0; i < OFDM_TABLE_SIZE_92D; i++) {
860 if (ele_d ==
861 (ofdmswing_table[i] & MASKOFDM_D)) {
862 ofdm_index_old[1] = (u8)i;
863 rtl_dbg(rtlpriv, COMP_POWER_TRACKING,
864 DBG_LOUD,
865 "Initial pathB ele_d reg 0x%x = 0x%lx, ofdm_index = 0x%x\n",
866 ROFDM0_XBTXIQIMBALANCE, ele_d,
867 ofdm_index_old[1]);
868 break;
869 }
870 }
871 }
872 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
873 rtl92d_bandtype_2_4G(hw, &temp_cck, &cck_index_old);
874 } else {
875 temp_cck = 0x090e1317;
876 cck_index_old = 12;
877 }
878
879 if (!rtlpriv->dm.thermalvalue) {
880 rtlpriv->dm.thermalvalue = rtlefuse->eeprom_thermalmeter;
881 rtlpriv->dm.thermalvalue_lck = thermalvalue;
882 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
883 rtlpriv->dm.thermalvalue_rxgain = rtlefuse->eeprom_thermalmeter;
884 for (i = 0; i < rf; i++)
885 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
886 rtlpriv->dm.cck_index = cck_index_old;
887 }
888 if (rtlhal->reloadtxpowerindex) {
889 for (i = 0; i < rf; i++)
890 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
891 rtlpriv->dm.cck_index = cck_index_old;
892 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
893 "reload ofdm index for band switch\n");
894 }
895old_index_done:
896 for (i = 0; i < rf; i++)
897 ofdm_index[i] = rtlpriv->dm.ofdm_index[i];
898
899 rtlpriv->dm.thermalvalue_avg
900 [rtlpriv->dm.thermalvalue_avg_index] = thermalvalue;
901 rtlpriv->dm.thermalvalue_avg_index++;
902 if (rtlpriv->dm.thermalvalue_avg_index == AVG_THERMAL_NUM)
903 rtlpriv->dm.thermalvalue_avg_index = 0;
904 for (i = 0; i < AVG_THERMAL_NUM; i++) {
905 if (rtlpriv->dm.thermalvalue_avg[i]) {
906 thermalvalue_avg += rtlpriv->dm.thermalvalue_avg[i];
907 thermalvalue_avg_count++;
908 }
909 }
910 if (thermalvalue_avg_count)
911 thermalvalue = (u8)(thermalvalue_avg / thermalvalue_avg_count);
912 if (rtlhal->reloadtxpowerindex) {
913 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
914 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
915 (rtlefuse->eeprom_thermalmeter - thermalvalue);
916 rtlhal->reloadtxpowerindex = false;
917 rtlpriv->dm.done_txpower = false;
918 } else if (rtlpriv->dm.done_txpower) {
919 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
920 (thermalvalue - rtlpriv->dm.thermalvalue) :
921 (rtlpriv->dm.thermalvalue - thermalvalue);
922 } else {
923 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
924 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
925 (rtlefuse->eeprom_thermalmeter - thermalvalue);
926 }
927 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
928 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
929 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
930 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
931 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
932 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
933 delta_rxgain =
934 (thermalvalue > rtlpriv->dm.thermalvalue_rxgain) ?
935 (thermalvalue - rtlpriv->dm.thermalvalue_rxgain) :
936 (rtlpriv->dm.thermalvalue_rxgain - thermalvalue);
937 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
938 "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
939 thermalvalue, rtlpriv->dm.thermalvalue,
940 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
941 delta_iqk);
942 if (delta_lck > rtlefuse->delta_lck && rtlefuse->delta_lck != 0) {
943 rtlpriv->dm.thermalvalue_lck = thermalvalue;
944 rtl92d_phy_lc_calibrate(hw);
945 }
946
947 if (delta == 0 || !rtlpriv->dm.txpower_track_control)
948 goto check_delta;
949
950 rtlpriv->dm.done_txpower = true;
951 delta = (thermalvalue > rtlefuse->eeprom_thermalmeter) ?
952 (thermalvalue - rtlefuse->eeprom_thermalmeter) :
953 (rtlefuse->eeprom_thermalmeter - thermalvalue);
954 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
955 offset = 4;
956 if (delta > INDEX_MAPPING_NUM - 1)
957 index = index_mapping[offset][INDEX_MAPPING_NUM - 1];
958 else
959 index = index_mapping[offset][delta];
960 if (thermalvalue > rtlpriv->dm.thermalvalue) {
961 for (i = 0; i < rf; i++)
962 ofdm_index[i] -= delta;
963 cck_index -= delta;
964 } else {
965 for (i = 0; i < rf; i++)
966 ofdm_index[i] += index;
967 cck_index += index;
968 }
969 } else if (rtlhal->current_bandtype == BAND_ON_5G) {
970 rtl92d_bandtype_5G(rtlhal, ofdm_index,
971 &internal_pa, thermalvalue,
972 delta, rf, rtlefuse, rtlpriv,
973 rtlphy, index_mapping,
974 index_mapping_internal_pa);
975 }
976 if (is2t) {
977 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
978 "temp OFDM_A_index=0x%x, OFDM_B_index = 0x%x,cck_index=0x%x\n",
979 rtlpriv->dm.ofdm_index[0],
980 rtlpriv->dm.ofdm_index[1],
981 rtlpriv->dm.cck_index);
982 } else {
983 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
984 "temp OFDM_A_index=0x%x,cck_index = 0x%x\n",
985 rtlpriv->dm.ofdm_index[0],
986 rtlpriv->dm.cck_index);
987 }
988 for (i = 0; i < rf; i++) {
989 if (ofdm_index[i] > OFDM_TABLE_SIZE_92D - 1) {
990 ofdm_index[i] = OFDM_TABLE_SIZE_92D - 1;
991 } else if (internal_pa ||
992 rtlhal->current_bandtype == BAND_ON_2_4G) {
993 if (ofdm_index[i] < ofdm_min_index_internal_pa)
994 ofdm_index[i] = ofdm_min_index_internal_pa;
995 } else if (ofdm_index[i] < ofdm_min_index) {
996 ofdm_index[i] = ofdm_min_index;
997 }
998 }
999 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1000 if (cck_index > CCK_TABLE_SIZE - 1) {
1001 cck_index = CCK_TABLE_SIZE - 1;
1002 } else if (cck_index < 0) {
1003 cck_index = 0;
1004 }
1005 }
1006 if (is2t) {
1007 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1008 "new OFDM_A_index=0x%x, OFDM_B_index = 0x%x, cck_index=0x%x\n",
1009 ofdm_index[0], ofdm_index[1],
1010 cck_index);
1011 } else {
1012 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1013 "new OFDM_A_index=0x%x,cck_index = 0x%x\n",
1014 ofdm_index[0], cck_index);
1015 }
1016 ele_d = (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
1017 val_x = rtlphy->iqk_matrix[indexforchannel].value[0][0];
1018 val_y = rtlphy->iqk_matrix[indexforchannel].value[0][1];
1019 if (val_x != 0) {
1020 if ((val_x & 0x00000200) != 0)
1021 val_x = val_x | 0xFFFFFC00;
1022 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
1023
1024
1025 if ((val_y & 0x00000200) != 0)
1026 val_y = val_y | 0xFFFFFC00;
1027 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
1028
1029
1030
1031
1032 value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a;
1033 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1034 MASKDWORD, value32);
1035
1036 value32 = (ele_c & 0x000003C0) >> 6;
1037 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
1038 value32);
1039
1040 value32 = ((val_x * ele_d) >> 7) & 0x01;
1041 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
1042 value32);
1043
1044 } else {
1045 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1046 MASKDWORD,
1047 ofdmswing_table[(u8)ofdm_index[0]]);
1048 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
1049 0x00);
1050 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1051 BIT(24), 0x00);
1052 }
1053
1054 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1055 "TxPwrTracking for interface %d path A: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xe94 = 0x%lx 0xe9c = 0x%lx\n",
1056 rtlhal->interfaceindex,
1057 val_x, val_y, ele_a, ele_c, ele_d,
1058 val_x, val_y);
1059
1060 if (cck_index >= CCK_TABLE_SIZE)
1061 cck_index = CCK_TABLE_SIZE - 1;
1062 if (cck_index < 0)
1063 cck_index = 0;
1064 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
1065
1066 if (!rtlpriv->dm.cck_inch14) {
1067 rtl_write_byte(rtlpriv, 0xa22,
1068 cckswing_table_ch1ch13[cck_index][0]);
1069 rtl_write_byte(rtlpriv, 0xa23,
1070 cckswing_table_ch1ch13[cck_index][1]);
1071 rtl_write_byte(rtlpriv, 0xa24,
1072 cckswing_table_ch1ch13[cck_index][2]);
1073 rtl_write_byte(rtlpriv, 0xa25,
1074 cckswing_table_ch1ch13[cck_index][3]);
1075 rtl_write_byte(rtlpriv, 0xa26,
1076 cckswing_table_ch1ch13[cck_index][4]);
1077 rtl_write_byte(rtlpriv, 0xa27,
1078 cckswing_table_ch1ch13[cck_index][5]);
1079 rtl_write_byte(rtlpriv, 0xa28,
1080 cckswing_table_ch1ch13[cck_index][6]);
1081 rtl_write_byte(rtlpriv, 0xa29,
1082 cckswing_table_ch1ch13[cck_index][7]);
1083 } else {
1084 rtl_write_byte(rtlpriv, 0xa22,
1085 cckswing_table_ch14[cck_index][0]);
1086 rtl_write_byte(rtlpriv, 0xa23,
1087 cckswing_table_ch14[cck_index][1]);
1088 rtl_write_byte(rtlpriv, 0xa24,
1089 cckswing_table_ch14[cck_index][2]);
1090 rtl_write_byte(rtlpriv, 0xa25,
1091 cckswing_table_ch14[cck_index][3]);
1092 rtl_write_byte(rtlpriv, 0xa26,
1093 cckswing_table_ch14[cck_index][4]);
1094 rtl_write_byte(rtlpriv, 0xa27,
1095 cckswing_table_ch14[cck_index][5]);
1096 rtl_write_byte(rtlpriv, 0xa28,
1097 cckswing_table_ch14[cck_index][6]);
1098 rtl_write_byte(rtlpriv, 0xa29,
1099 cckswing_table_ch14[cck_index][7]);
1100 }
1101 }
1102 if (is2t) {
1103 ele_d = (ofdmswing_table[ofdm_index[1]] & 0xFFC00000) >> 22;
1104 val_x = rtlphy->iqk_matrix[indexforchannel].value[0][4];
1105 val_y = rtlphy->iqk_matrix[indexforchannel].value[0][5];
1106 if (val_x != 0) {
1107 if ((val_x & 0x00000200) != 0)
1108
1109 val_x = val_x | 0xFFFFFC00;
1110 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
1111
1112 if ((val_y & 0x00000200) != 0)
1113 val_y = val_y | 0xFFFFFC00;
1114 ele_c = ((val_y * ele_d) >> 8) & 0x00003FF;
1115
1116
1117
1118 value32 = (ele_d << 22) | ((ele_c & 0x3F) << 16) | ele_a;
1119 rtl_set_bbreg(hw,
1120 ROFDM0_XBTXIQIMBALANCE,
1121 MASKDWORD, value32);
1122 value32 = (ele_c & 0x000003C0) >> 6;
1123 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1124 MASKH4BITS, value32);
1125 value32 = ((val_x * ele_d) >> 7) & 0x01;
1126 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1127 BIT(28), value32);
1128 } else {
1129 rtl_set_bbreg(hw,
1130 ROFDM0_XBTXIQIMBALANCE,
1131 MASKDWORD,
1132 ofdmswing_table[ofdm_index[1]]);
1133 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1134 MASKH4BITS, 0x00);
1135 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1136 BIT(28), 0x00);
1137 }
1138 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1139 "TxPwrTracking path B: X = 0x%lx, Y = 0x%lx ele_A = 0x%lx ele_C = 0x%lx ele_D = 0x%lx 0xeb4 = 0x%lx 0xebc = 0x%lx\n",
1140 val_x, val_y, ele_a, ele_c,
1141 ele_d, val_x, val_y);
1142 }
1143 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1144 "TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n",
1145 rtl_get_bbreg(hw, 0xc80, MASKDWORD),
1146 rtl_get_bbreg(hw, 0xc94, MASKDWORD),
1147 rtl_get_rfreg(hw, RF90_PATH_A, 0x24,
1148 RFREG_OFFSET_MASK));
1149
1150check_delta:
1151 if (delta_iqk > rtlefuse->delta_iqk && rtlefuse->delta_iqk != 0) {
1152 rtl92d_phy_reset_iqk_result(hw);
1153 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1154 rtl92d_phy_iq_calibrate(hw);
1155 }
1156 if (delta_rxgain > 0 && rtlhal->current_bandtype == BAND_ON_5G &&
1157 thermalvalue <= rtlefuse->eeprom_thermalmeter) {
1158 rtlpriv->dm.thermalvalue_rxgain = thermalvalue;
1159 rtl92d_dm_rxgain_tracking_thermalmeter(hw);
1160 }
1161 if (rtlpriv->dm.txpower_track_control)
1162 rtlpriv->dm.thermalvalue = thermalvalue;
1163
1164exit:
1165 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
1166}
1167
1168static void rtl92d_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1169{
1170 struct rtl_priv *rtlpriv = rtl_priv(hw);
1171
1172 rtlpriv->dm.txpower_tracking = true;
1173 rtlpriv->dm.txpower_trackinginit = false;
1174 rtlpriv->dm.txpower_track_control = true;
1175 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1176 "pMgntInfo->txpower_tracking = %d\n",
1177 rtlpriv->dm.txpower_tracking);
1178}
1179
1180void rtl92d_dm_check_txpower_tracking_thermal_meter(struct ieee80211_hw *hw)
1181{
1182 struct rtl_priv *rtlpriv = rtl_priv(hw);
1183
1184 if (!rtlpriv->dm.txpower_tracking)
1185 return;
1186
1187 if (!rtlpriv->dm.tm_trigger) {
1188 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, BIT(17) |
1189 BIT(16), 0x03);
1190 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1191 "Trigger 92S Thermal Meter!!\n");
1192 rtlpriv->dm.tm_trigger = 1;
1193 return;
1194 } else {
1195 rtl_dbg(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1196 "Schedule TxPowerTracking direct call!!\n");
1197 rtl92d_dm_txpower_tracking_callback_thermalmeter(hw);
1198 rtlpriv->dm.tm_trigger = 0;
1199 }
1200}
1201
1202void rtl92d_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1203{
1204 struct rtl_priv *rtlpriv = rtl_priv(hw);
1205 struct rate_adaptive *ra = &(rtlpriv->ra);
1206
1207 ra->ratr_state = DM_RATR_STA_INIT;
1208 ra->pre_ratr_state = DM_RATR_STA_INIT;
1209 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1210 rtlpriv->dm.useramask = true;
1211 else
1212 rtlpriv->dm.useramask = false;
1213}
1214
1215void rtl92d_dm_init(struct ieee80211_hw *hw)
1216{
1217 struct rtl_priv *rtlpriv = rtl_priv(hw);
1218
1219 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1220 rtl_dm_diginit(hw, 0x20);
1221 rtlpriv->dm_digtable.rx_gain_max = DM_DIG_FA_UPPER;
1222 rtlpriv->dm_digtable.rx_gain_min = DM_DIG_FA_LOWER;
1223 rtl92d_dm_init_dynamic_txpower(hw);
1224 rtl92d_dm_init_edca_turbo(hw);
1225 rtl92d_dm_init_rate_adaptive_mask(hw);
1226 rtl92d_dm_initialize_txpower_tracking(hw);
1227}
1228
1229void rtl92d_dm_watchdog(struct ieee80211_hw *hw)
1230{
1231 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1232 bool fw_current_inpsmode = false;
1233 bool fwps_awake = true;
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243 if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
1244 fwps_awake) && (!ppsc->rfchange_inprogress)) {
1245 rtl92d_dm_pwdb_monitor(hw);
1246 rtl92d_dm_false_alarm_counter_statistics(hw);
1247 rtl92d_dm_find_minimum_rssi(hw);
1248 rtl92d_dm_dig(hw);
1249
1250 rtl92d_dm_dynamic_txpower(hw);
1251
1252
1253
1254 rtl92d_dm_check_edca_turbo(hw);
1255 }
1256}
1257
