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5
6#include <linux/delay.h>
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/phy/phy.h>
11#include <linux/regulator/consumer.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/slab.h>
15
16#include <soc/tegra/fuse.h>
17
18#include "xusb.h"
19
20
21#define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
22#define HS_CURR_LEVEL_PAD_MASK 0x3f
23#define HS_TERM_RANGE_ADJ_SHIFT 7
24#define HS_TERM_RANGE_ADJ_MASK 0xf
25#define HS_SQUELCH_SHIFT 29
26#define HS_SQUELCH_MASK 0x7
27
28#define RPD_CTRL_SHIFT 0
29#define RPD_CTRL_MASK 0x1f
30
31
32#define XUSB_PADCTL_USB2_PAD_MUX 0x4
33#define USB2_PORT_SHIFT(x) ((x) * 2)
34#define USB2_PORT_MASK 0x3
35#define PORT_XUSB 1
36#define HSIC_PORT_SHIFT(x) ((x) + 20)
37#define HSIC_PORT_MASK 0x1
38#define PORT_HSIC 0
39
40#define XUSB_PADCTL_USB2_PORT_CAP 0x8
41#define XUSB_PADCTL_SS_PORT_CAP 0xc
42#define PORTX_CAP_SHIFT(x) ((x) * 4)
43#define PORT_CAP_MASK 0x3
44#define PORT_CAP_DISABLED 0x0
45#define PORT_CAP_HOST 0x1
46#define PORT_CAP_DEVICE 0x2
47#define PORT_CAP_OTG 0x3
48
49#define XUSB_PADCTL_ELPG_PROGRAM 0x20
50#define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x)
51#define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
52#define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
53#define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
54#define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
55#define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
56#define ALL_WAKE_EVENTS \
57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
60 USB2_HSIC_PORT_WAKEUP_EVENT(0))
61
62#define XUSB_PADCTL_ELPG_PROGRAM_1 0x24
63#define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
64#define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
65#define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
66#define XUSB_PADCTL_SS_PORT_CFG 0x2c
67#define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
68#define PORTX_SPEED_SUPPORT_MASK (0x3)
69#define PORT_SPEED_SUPPORT_GEN1 (0x0)
70
71#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
72#define HS_CURR_LEVEL(x) ((x) & 0x3f)
73#define TERM_SEL BIT(25)
74#define USB2_OTG_PD BIT(26)
75#define USB2_OTG_PD2 BIT(27)
76#define USB2_OTG_PD2_OVRD_EN BIT(28)
77#define USB2_OTG_PD_ZI BIT(29)
78
79#define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40)
80#define USB2_OTG_PD_DR BIT(2)
81#define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3)
82#define RPD_CTRL(x) (((x) & 0x1f) << 26)
83
84#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
85#define BIAS_PAD_PD BIT(11)
86#define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0)
87
88#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
89#define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12)
90#define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19)
91#define USB2_PD_TRK BIT(26)
92
93#define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
94#define HSIC_PD_TX_DATA0 BIT(1)
95#define HSIC_PD_TX_STROBE BIT(3)
96#define HSIC_PD_RX_DATA0 BIT(4)
97#define HSIC_PD_RX_STROBE BIT(6)
98#define HSIC_PD_ZI_DATA0 BIT(7)
99#define HSIC_PD_ZI_STROBE BIT(9)
100#define HSIC_RPD_DATA0 BIT(13)
101#define HSIC_RPD_STROBE BIT(15)
102#define HSIC_RPU_DATA0 BIT(16)
103#define HSIC_RPU_STROBE BIT(18)
104
105#define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 0x340
106#define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5)
107#define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12)
108#define HSIC_PD_TRK BIT(19)
109
110#define USB2_VBUS_ID 0x360
111#define VBUS_OVERRIDE BIT(14)
112#define ID_OVERRIDE(x) (((x) & 0xf) << 18)
113#define ID_OVERRIDE_FLOATING ID_OVERRIDE(8)
114#define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0)
115
116
117#define XUSB_AO_USB_DEBOUNCE_DEL (0x4)
118#define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 4)
119#define UTMIP_LINE_DEB_CNT(x) ((x) & 0xf)
120
121#define XUSB_AO_UTMIP_TRIGGERS(x) (0x40 + (x) * 4)
122#define CLR_WALK_PTR BIT(0)
123#define CAP_CFG BIT(1)
124#define CLR_WAKE_ALARM BIT(3)
125
126#define XUSB_AO_UHSIC_TRIGGERS(x) (0x60 + (x) * 4)
127#define HSIC_CLR_WALK_PTR BIT(0)
128#define HSIC_CLR_WAKE_ALARM BIT(3)
129#define HSIC_CAP_CFG BIT(4)
130
131#define XUSB_AO_UTMIP_SAVED_STATE(x) (0x70 + (x) * 4)
132#define SPEED(x) ((x) & 0x3)
133#define UTMI_HS SPEED(0)
134#define UTMI_FS SPEED(1)
135#define UTMI_LS SPEED(2)
136#define UTMI_RST SPEED(3)
137
138#define XUSB_AO_UHSIC_SAVED_STATE(x) (0x90 + (x) * 4)
139#define MODE(x) ((x) & 0x1)
140#define MODE_HS MODE(0)
141#define MODE_RST MODE(1)
142
143#define XUSB_AO_UTMIP_SLEEPWALK_CFG(x) (0xd0 + (x) * 4)
144#define XUSB_AO_UHSIC_SLEEPWALK_CFG(x) (0xf0 + (x) * 4)
145#define FAKE_USBOP_VAL BIT(0)
146#define FAKE_USBON_VAL BIT(1)
147#define FAKE_USBOP_EN BIT(2)
148#define FAKE_USBON_EN BIT(3)
149#define FAKE_STROBE_VAL BIT(0)
150#define FAKE_DATA_VAL BIT(1)
151#define FAKE_STROBE_EN BIT(2)
152#define FAKE_DATA_EN BIT(3)
153#define WAKE_WALK_EN BIT(14)
154#define MASTER_ENABLE BIT(15)
155#define LINEVAL_WALK_EN BIT(16)
156#define WAKE_VAL(x) (((x) & 0xf) << 17)
157#define WAKE_VAL_NONE WAKE_VAL(12)
158#define WAKE_VAL_ANY WAKE_VAL(15)
159#define WAKE_VAL_DS10 WAKE_VAL(2)
160#define LINE_WAKEUP_EN BIT(21)
161#define MASTER_CFG_SEL BIT(22)
162
163#define XUSB_AO_UTMIP_SLEEPWALK(x) (0x100 + (x) * 4)
164
165#define USBOP_RPD_A BIT(0)
166#define USBON_RPD_A BIT(1)
167#define AP_A BIT(4)
168#define AN_A BIT(5)
169#define HIGHZ_A BIT(6)
170
171#define USBOP_RPD_B BIT(8)
172#define USBON_RPD_B BIT(9)
173#define AP_B BIT(12)
174#define AN_B BIT(13)
175#define HIGHZ_B BIT(14)
176
177#define USBOP_RPD_C BIT(16)
178#define USBON_RPD_C BIT(17)
179#define AP_C BIT(20)
180#define AN_C BIT(21)
181#define HIGHZ_C BIT(22)
182
183#define USBOP_RPD_D BIT(24)
184#define USBON_RPD_D BIT(25)
185#define AP_D BIT(28)
186#define AN_D BIT(29)
187#define HIGHZ_D BIT(30)
188
189#define XUSB_AO_UHSIC_SLEEPWALK(x) (0x120 + (x) * 4)
190
191#define RPD_STROBE_A BIT(0)
192#define RPD_DATA0_A BIT(1)
193#define RPU_STROBE_A BIT(2)
194#define RPU_DATA0_A BIT(3)
195
196#define RPD_STROBE_B BIT(8)
197#define RPD_DATA0_B BIT(9)
198#define RPU_STROBE_B BIT(10)
199#define RPU_DATA0_B BIT(11)
200
201#define RPD_STROBE_C BIT(16)
202#define RPD_DATA0_C BIT(17)
203#define RPU_STROBE_C BIT(18)
204#define RPU_DATA0_C BIT(19)
205
206#define RPD_STROBE_D BIT(24)
207#define RPD_DATA0_D BIT(25)
208#define RPU_STROBE_D BIT(26)
209#define RPU_DATA0_D BIT(27)
210
211#define XUSB_AO_UTMIP_PAD_CFG(x) (0x130 + (x) * 4)
212#define FSLS_USE_XUSB_AO BIT(3)
213#define TRK_CTRL_USE_XUSB_AO BIT(4)
214#define RPD_CTRL_USE_XUSB_AO BIT(5)
215#define RPU_USE_XUSB_AO BIT(6)
216#define VREG_USE_XUSB_AO BIT(7)
217#define USBOP_VAL_PD BIT(8)
218#define USBON_VAL_PD BIT(9)
219#define E_DPD_OVRD_EN BIT(10)
220#define E_DPD_OVRD_VAL BIT(11)
221
222#define XUSB_AO_UHSIC_PAD_CFG(x) (0x150 + (x) * 4)
223#define STROBE_VAL_PD BIT(0)
224#define DATA0_VAL_PD BIT(1)
225#define USE_XUSB_AO BIT(4)
226
227#define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \
228 { \
229 .name = _name, \
230 .offset = _offset, \
231 .shift = _shift, \
232 .mask = _mask, \
233 .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \
234 .funcs = tegra186_##_type##_functions, \
235 }
236
237struct tegra_xusb_fuse_calibration {
238 u32 *hs_curr_level;
239 u32 hs_squelch;
240 u32 hs_term_range_adj;
241 u32 rpd_ctrl;
242};
243
244struct tegra186_xusb_padctl_context {
245 u32 vbus_id;
246 u32 usb2_pad_mux;
247 u32 usb2_port_cap;
248 u32 ss_port_cap;
249};
250
251struct tegra186_xusb_padctl {
252 struct tegra_xusb_padctl base;
253 void __iomem *ao_regs;
254
255 struct tegra_xusb_fuse_calibration calib;
256
257
258 struct clk *usb2_trk_clk;
259 unsigned int bias_pad_enable;
260
261
262 struct tegra186_xusb_padctl_context context;
263};
264
265static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset)
266{
267 writel(value, priv->ao_regs + offset);
268}
269
270static inline u32 ao_readl(struct tegra186_xusb_padctl *priv, unsigned int offset)
271{
272 return readl(priv->ao_regs + offset);
273}
274
275static inline struct tegra186_xusb_padctl *
276to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
277{
278 return container_of(padctl, struct tegra186_xusb_padctl, base);
279}
280
281
282static struct tegra_xusb_lane *
283tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
284 unsigned int index)
285{
286 struct tegra_xusb_usb2_lane *usb2;
287 int err;
288
289 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
290 if (!usb2)
291 return ERR_PTR(-ENOMEM);
292
293 INIT_LIST_HEAD(&usb2->base.list);
294 usb2->base.soc = &pad->soc->lanes[index];
295 usb2->base.index = index;
296 usb2->base.pad = pad;
297 usb2->base.np = np;
298
299 err = tegra_xusb_lane_parse_dt(&usb2->base, np);
300 if (err < 0) {
301 kfree(usb2);
302 return ERR_PTR(err);
303 }
304
305 return &usb2->base;
306}
307
308static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane)
309{
310 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
311
312 kfree(usb2);
313}
314
315static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
316 enum usb_device_speed speed)
317{
318 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
319 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
320 unsigned int index = lane->index;
321 u32 value;
322
323 mutex_lock(&padctl->lock);
324
325
326 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
327 value &= ~MASTER_ENABLE;
328 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
329
330
331 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
332 value |= MASTER_CFG_SEL;
333 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
334
335
336 value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL);
337 value &= ~UTMIP_LINE_DEB_CNT(~0);
338 value |= UTMIP_LINE_DEB_CNT(1);
339 ao_writel(priv, value, XUSB_AO_USB_DEBOUNCE_DEL);
340
341
342 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
343 value &= ~(FAKE_USBOP_VAL | FAKE_USBON_VAL |
344 FAKE_USBOP_EN | FAKE_USBON_EN);
345 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
346
347
348 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
349 value &= ~LINE_WAKEUP_EN;
350 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
351
352
353 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
354 value &= ~WAKE_VAL(~0);
355 value |= WAKE_VAL_NONE;
356 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
357
358
359 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
360 value |= (USBOP_VAL_PD | USBON_VAL_PD);
361 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
362
363
364 value = ao_readl(priv, XUSB_AO_UTMIP_SAVED_STATE(index));
365 value &= ~SPEED(~0);
366
367 switch (speed) {
368 case USB_SPEED_HIGH:
369 value |= UTMI_HS;
370 break;
371
372 case USB_SPEED_FULL:
373 value |= UTMI_FS;
374 break;
375
376 case USB_SPEED_LOW:
377 value |= UTMI_LS;
378 break;
379
380 default:
381 value |= UTMI_RST;
382 break;
383 }
384
385 ao_writel(priv, value, XUSB_AO_UTMIP_SAVED_STATE(index));
386
387
388 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
389 value |= LINEVAL_WALK_EN;
390 value &= ~WAKE_WALK_EN;
391 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
392
393
394
395
396 value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
397 value |= (CLR_WALK_PTR | CLR_WAKE_ALARM | CAP_CFG);
398 ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
399
400
401
402
403
404
405 value = USBOP_RPD_A | USBOP_RPD_B | USBOP_RPD_C | USBOP_RPD_D;
406 value |= USBON_RPD_A | USBON_RPD_B | USBON_RPD_C | USBON_RPD_D;
407
408 switch (speed) {
409 case USB_SPEED_HIGH:
410 case USB_SPEED_FULL:
411
412 value |= HIGHZ_A;
413 value |= AP_A;
414 value |= AN_B | AN_C | AN_D;
415 break;
416
417 case USB_SPEED_LOW:
418
419 value |= HIGHZ_A;
420 value |= AN_A;
421 value |= AP_B | AP_C | AP_D;
422 break;
423
424 default:
425 value |= HIGHZ_A | HIGHZ_B | HIGHZ_C | HIGHZ_D;
426 break;
427 }
428
429 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
430
431
432 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
433 value &= ~(USBOP_VAL_PD | USBON_VAL_PD);
434 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
435
436 usleep_range(150, 200);
437
438
439 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
440 value |= FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
441 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO;
442 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
443
444
445 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
446 value &= ~WAKE_VAL(~0);
447 value |= WAKE_VAL_ANY;
448 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
449
450
451 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
452 value |= MASTER_ENABLE | LINE_WAKEUP_EN;
453 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
454
455 mutex_unlock(&padctl->lock);
456
457 return 0;
458}
459
460static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
461{
462 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
463 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
464 unsigned int index = lane->index;
465 u32 value;
466
467 mutex_lock(&padctl->lock);
468
469
470 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
471 value &= ~(MASTER_ENABLE | LINE_WAKEUP_EN);
472 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
473
474
475 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
476 value &= ~(FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
477 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO);
478 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
479
480
481 value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
482 value &= ~WAKE_VAL(~0);
483 value |= WAKE_VAL_NONE;
484 ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
485
486
487 value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
488 value |= USBOP_VAL_PD | USBON_VAL_PD;
489 ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
490
491
492 value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
493 value |= CLR_WAKE_ALARM;
494 ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
495
496 mutex_unlock(&padctl->lock);
497
498 return 0;
499}
500
501static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane)
502{
503 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
504 unsigned int index = lane->index;
505 u32 value;
506
507 mutex_lock(&padctl->lock);
508
509 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
510 value &= ~ALL_WAKE_EVENTS;
511 value |= USB2_PORT_WAKEUP_EVENT(index);
512 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
513
514 usleep_range(10, 20);
515
516 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
517 value &= ~ALL_WAKE_EVENTS;
518 value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
519 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
520
521 mutex_unlock(&padctl->lock);
522
523 return 0;
524}
525
526static int tegra186_utmi_disable_phy_wake(struct tegra_xusb_lane *lane)
527{
528 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
529 unsigned int index = lane->index;
530 u32 value;
531
532 mutex_lock(&padctl->lock);
533
534 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
535 value &= ~ALL_WAKE_EVENTS;
536 value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
537 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
538
539 usleep_range(10, 20);
540
541 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
542 value &= ~ALL_WAKE_EVENTS;
543 value |= USB2_PORT_WAKEUP_EVENT(index);
544 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
545
546 mutex_unlock(&padctl->lock);
547
548 return 0;
549}
550
551static bool tegra186_utmi_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
552{
553 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
554 unsigned int index = lane->index;
555 u32 value;
556
557 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
558 if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) &&
559 (value & USB2_PORT_WAKEUP_EVENT(index)))
560 return true;
561
562 return false;
563}
564
565static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = {
566 .probe = tegra186_usb2_lane_probe,
567 .remove = tegra186_usb2_lane_remove,
568 .enable_phy_sleepwalk = tegra186_utmi_enable_phy_sleepwalk,
569 .disable_phy_sleepwalk = tegra186_utmi_disable_phy_sleepwalk,
570 .enable_phy_wake = tegra186_utmi_enable_phy_wake,
571 .disable_phy_wake = tegra186_utmi_disable_phy_wake,
572 .remote_wake_detected = tegra186_utmi_phy_remote_wake_detected,
573};
574
575static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
576{
577 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
578 struct device *dev = padctl->dev;
579 u32 value;
580 int err;
581
582 mutex_lock(&padctl->lock);
583
584 if (priv->bias_pad_enable++ > 0) {
585 mutex_unlock(&padctl->lock);
586 return;
587 }
588
589 err = clk_prepare_enable(priv->usb2_trk_clk);
590 if (err < 0)
591 dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);
592
593 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
594 value &= ~USB2_TRK_START_TIMER(~0);
595 value |= USB2_TRK_START_TIMER(0x1e);
596 value &= ~USB2_TRK_DONE_RESET_TIMER(~0);
597 value |= USB2_TRK_DONE_RESET_TIMER(0xa);
598 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
599
600 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
601 value &= ~BIAS_PAD_PD;
602 value &= ~HS_SQUELCH_LEVEL(~0);
603 value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);
604 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
605
606 udelay(1);
607
608 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
609 value &= ~USB2_PD_TRK;
610 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
611
612 mutex_unlock(&padctl->lock);
613}
614
615static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
616{
617 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
618 u32 value;
619
620 mutex_lock(&padctl->lock);
621
622 if (WARN_ON(priv->bias_pad_enable == 0)) {
623 mutex_unlock(&padctl->lock);
624 return;
625 }
626
627 if (--priv->bias_pad_enable > 0) {
628 mutex_unlock(&padctl->lock);
629 return;
630 }
631
632 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
633 value |= USB2_PD_TRK;
634 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
635
636 clk_disable_unprepare(priv->usb2_trk_clk);
637
638 mutex_unlock(&padctl->lock);
639}
640
641static void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy)
642{
643 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
644 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
645 struct tegra_xusb_usb2_port *port;
646 struct device *dev = padctl->dev;
647 unsigned int index = lane->index;
648 u32 value;
649
650 if (!phy)
651 return;
652
653 port = tegra_xusb_find_usb2_port(padctl, index);
654 if (!port) {
655 dev_err(dev, "no port found for USB2 lane %u\n", index);
656 return;
657 }
658
659 tegra186_utmi_bias_pad_power_on(padctl);
660
661 udelay(2);
662
663 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
664 value &= ~USB2_OTG_PD;
665 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
666
667 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
668 value &= ~USB2_OTG_PD_DR;
669 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
670}
671
672static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy)
673{
674 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
675 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
676 unsigned int index = lane->index;
677 u32 value;
678
679 if (!phy)
680 return;
681
682 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
683 value |= USB2_OTG_PD;
684 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
685
686 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
687 value |= USB2_OTG_PD_DR;
688 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
689
690 udelay(2);
691
692 tegra186_utmi_bias_pad_power_off(padctl);
693}
694
695static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
696 bool status)
697{
698 u32 value;
699
700 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
701
702 value = padctl_readl(padctl, USB2_VBUS_ID);
703
704 if (status) {
705 value |= VBUS_OVERRIDE;
706 value &= ~ID_OVERRIDE(~0);
707 value |= ID_OVERRIDE_FLOATING;
708 } else {
709 value &= ~VBUS_OVERRIDE;
710 }
711
712 padctl_writel(padctl, value, USB2_VBUS_ID);
713
714 return 0;
715}
716
717static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
718 bool status)
719{
720 u32 value;
721
722 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
723
724 value = padctl_readl(padctl, USB2_VBUS_ID);
725
726 if (status) {
727 if (value & VBUS_OVERRIDE) {
728 value &= ~VBUS_OVERRIDE;
729 padctl_writel(padctl, value, USB2_VBUS_ID);
730 usleep_range(1000, 2000);
731
732 value = padctl_readl(padctl, USB2_VBUS_ID);
733 }
734
735 value &= ~ID_OVERRIDE(~0);
736 value |= ID_OVERRIDE_GROUNDED;
737 } else {
738 value &= ~ID_OVERRIDE(~0);
739 value |= ID_OVERRIDE_FLOATING;
740 }
741
742 padctl_writel(padctl, value, USB2_VBUS_ID);
743
744 return 0;
745}
746
747static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode,
748 int submode)
749{
750 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
751 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
752 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
753 lane->index);
754 int err = 0;
755
756 mutex_lock(&padctl->lock);
757
758 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
759
760 if (mode == PHY_MODE_USB_OTG) {
761 if (submode == USB_ROLE_HOST) {
762 tegra186_xusb_padctl_id_override(padctl, true);
763
764 err = regulator_enable(port->supply);
765 } else if (submode == USB_ROLE_DEVICE) {
766 tegra186_xusb_padctl_vbus_override(padctl, true);
767 } else if (submode == USB_ROLE_NONE) {
768
769
770
771
772
773 if (regulator_is_enabled(port->supply))
774 regulator_disable(port->supply);
775
776 tegra186_xusb_padctl_id_override(padctl, false);
777 tegra186_xusb_padctl_vbus_override(padctl, false);
778 }
779 }
780
781 mutex_unlock(&padctl->lock);
782
783 return err;
784}
785
786static int tegra186_utmi_phy_power_on(struct phy *phy)
787{
788 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
789 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
790 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
791 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
792 struct tegra_xusb_usb2_port *port;
793 unsigned int index = lane->index;
794 struct device *dev = padctl->dev;
795 u32 value;
796
797 port = tegra_xusb_find_usb2_port(padctl, index);
798 if (!port) {
799 dev_err(dev, "no port found for USB2 lane %u\n", index);
800 return -ENODEV;
801 }
802
803 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
804 value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
805 value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
806 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
807
808 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
809 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
810
811 if (port->mode == USB_DR_MODE_UNKNOWN)
812 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
813 else if (port->mode == USB_DR_MODE_PERIPHERAL)
814 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
815 else if (port->mode == USB_DR_MODE_HOST)
816 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
817 else if (port->mode == USB_DR_MODE_OTG)
818 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
819
820 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
821
822 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
823 value &= ~USB2_OTG_PD_ZI;
824 value |= TERM_SEL;
825 value &= ~HS_CURR_LEVEL(~0);
826
827 if (usb2->hs_curr_level_offset) {
828 int hs_current_level;
829
830 hs_current_level = (int)priv->calib.hs_curr_level[index] +
831 usb2->hs_curr_level_offset;
832
833 if (hs_current_level < 0)
834 hs_current_level = 0;
835 if (hs_current_level > 0x3f)
836 hs_current_level = 0x3f;
837
838 value |= HS_CURR_LEVEL(hs_current_level);
839 } else {
840 value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);
841 }
842
843 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
844
845 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
846 value &= ~TERM_RANGE_ADJ(~0);
847 value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
848 value &= ~RPD_CTRL(~0);
849 value |= RPD_CTRL(priv->calib.rpd_ctrl);
850 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
851
852
853 tegra_phy_xusb_utmi_pad_power_on(phy);
854 return 0;
855}
856
857static int tegra186_utmi_phy_power_off(struct phy *phy)
858{
859
860 tegra_phy_xusb_utmi_pad_power_down(phy);
861
862 return 0;
863}
864
865static int tegra186_utmi_phy_init(struct phy *phy)
866{
867 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
868 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
869 struct tegra_xusb_usb2_port *port;
870 unsigned int index = lane->index;
871 struct device *dev = padctl->dev;
872 int err;
873
874 port = tegra_xusb_find_usb2_port(padctl, index);
875 if (!port) {
876 dev_err(dev, "no port found for USB2 lane %u\n", index);
877 return -ENODEV;
878 }
879
880 if (port->supply && port->mode == USB_DR_MODE_HOST) {
881 err = regulator_enable(port->supply);
882 if (err) {
883 dev_err(dev, "failed to enable port %u VBUS: %d\n",
884 index, err);
885 return err;
886 }
887 }
888
889 return 0;
890}
891
892static int tegra186_utmi_phy_exit(struct phy *phy)
893{
894 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
895 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
896 struct tegra_xusb_usb2_port *port;
897 unsigned int index = lane->index;
898 struct device *dev = padctl->dev;
899 int err;
900
901 port = tegra_xusb_find_usb2_port(padctl, index);
902 if (!port) {
903 dev_err(dev, "no port found for USB2 lane %u\n", index);
904 return -ENODEV;
905 }
906
907 if (port->supply && port->mode == USB_DR_MODE_HOST) {
908 err = regulator_disable(port->supply);
909 if (err) {
910 dev_err(dev, "failed to disable port %u VBUS: %d\n",
911 index, err);
912 return err;
913 }
914 }
915
916 return 0;
917}
918
919static const struct phy_ops utmi_phy_ops = {
920 .init = tegra186_utmi_phy_init,
921 .exit = tegra186_utmi_phy_exit,
922 .power_on = tegra186_utmi_phy_power_on,
923 .power_off = tegra186_utmi_phy_power_off,
924 .set_mode = tegra186_utmi_phy_set_mode,
925 .owner = THIS_MODULE,
926};
927
928static struct tegra_xusb_pad *
929tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
930 const struct tegra_xusb_pad_soc *soc,
931 struct device_node *np)
932{
933 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
934 struct tegra_xusb_usb2_pad *usb2;
935 struct tegra_xusb_pad *pad;
936 int err;
937
938 usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
939 if (!usb2)
940 return ERR_PTR(-ENOMEM);
941
942 pad = &usb2->base;
943 pad->ops = &tegra186_usb2_lane_ops;
944 pad->soc = soc;
945
946 err = tegra_xusb_pad_init(pad, padctl, np);
947 if (err < 0) {
948 kfree(usb2);
949 goto out;
950 }
951
952 priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
953 if (IS_ERR(priv->usb2_trk_clk)) {
954 err = PTR_ERR(priv->usb2_trk_clk);
955 dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
956 goto unregister;
957 }
958
959 err = tegra_xusb_pad_register(pad, &utmi_phy_ops);
960 if (err < 0)
961 goto unregister;
962
963 dev_set_drvdata(&pad->dev, pad);
964
965 return pad;
966
967unregister:
968 device_unregister(&pad->dev);
969out:
970 return ERR_PTR(err);
971}
972
973static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad)
974{
975 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
976
977 kfree(usb2);
978}
979
980static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = {
981 .probe = tegra186_usb2_pad_probe,
982 .remove = tegra186_usb2_pad_remove,
983};
984
985static const char * const tegra186_usb2_functions[] = {
986 "xusb",
987};
988
989static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
990{
991 return 0;
992}
993
994static void tegra186_usb2_port_disable(struct tegra_xusb_port *port)
995{
996}
997
998static struct tegra_xusb_lane *
999tegra186_usb2_port_map(struct tegra_xusb_port *port)
1000{
1001 return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1002}
1003
1004static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = {
1005 .release = tegra_xusb_usb2_port_release,
1006 .remove = tegra_xusb_usb2_port_remove,
1007 .enable = tegra186_usb2_port_enable,
1008 .disable = tegra186_usb2_port_disable,
1009 .map = tegra186_usb2_port_map,
1010};
1011
1012
1013static struct tegra_xusb_lane *
1014tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1015 unsigned int index)
1016{
1017 struct tegra_xusb_usb3_lane *usb3;
1018 int err;
1019
1020 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
1021 if (!usb3)
1022 return ERR_PTR(-ENOMEM);
1023
1024 INIT_LIST_HEAD(&usb3->base.list);
1025 usb3->base.soc = &pad->soc->lanes[index];
1026 usb3->base.index = index;
1027 usb3->base.pad = pad;
1028 usb3->base.np = np;
1029
1030 err = tegra_xusb_lane_parse_dt(&usb3->base, np);
1031 if (err < 0) {
1032 kfree(usb3);
1033 return ERR_PTR(err);
1034 }
1035
1036 return &usb3->base;
1037}
1038
1039static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane)
1040{
1041 struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);
1042
1043 kfree(usb3);
1044}
1045
1046static int tegra186_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
1047 enum usb_device_speed speed)
1048{
1049 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1050 unsigned int index = lane->index;
1051 u32 value;
1052
1053 mutex_lock(&padctl->lock);
1054
1055 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1056 value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1057 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1058
1059 usleep_range(100, 200);
1060
1061 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1062 value |= SSPX_ELPG_CLAMP_EN(index);
1063 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1064
1065 usleep_range(250, 350);
1066
1067 mutex_unlock(&padctl->lock);
1068
1069 return 0;
1070}
1071
1072static int tegra186_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
1073{
1074 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1075 unsigned int index = lane->index;
1076 u32 value;
1077
1078 mutex_lock(&padctl->lock);
1079
1080 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1081 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1082 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1083
1084 usleep_range(100, 200);
1085
1086 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1087 value &= ~SSPX_ELPG_CLAMP_EN(index);
1088 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1089
1090 mutex_unlock(&padctl->lock);
1091
1092 return 0;
1093}
1094
1095static int tegra186_usb3_enable_phy_wake(struct tegra_xusb_lane *lane)
1096{
1097 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1098 unsigned int index = lane->index;
1099 u32 value;
1100
1101 mutex_lock(&padctl->lock);
1102
1103 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1104 value &= ~ALL_WAKE_EVENTS;
1105 value |= SS_PORT_WAKEUP_EVENT(index);
1106 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1107
1108 usleep_range(10, 20);
1109
1110 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1111 value &= ~ALL_WAKE_EVENTS;
1112 value |= SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1113 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1114
1115 mutex_unlock(&padctl->lock);
1116
1117 return 0;
1118}
1119
1120static int tegra186_usb3_disable_phy_wake(struct tegra_xusb_lane *lane)
1121{
1122 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1123 unsigned int index = lane->index;
1124 u32 value;
1125
1126 mutex_lock(&padctl->lock);
1127
1128 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1129 value &= ~ALL_WAKE_EVENTS;
1130 value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1131 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1132
1133 usleep_range(10, 20);
1134
1135 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1136 value &= ~ALL_WAKE_EVENTS;
1137 value |= SS_PORT_WAKEUP_EVENT(index);
1138 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1139
1140 mutex_unlock(&padctl->lock);
1141
1142 return 0;
1143}
1144
1145static bool tegra186_usb3_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
1146{
1147 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1148 unsigned int index = lane->index;
1149 u32 value;
1150
1151 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1152 if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index)))
1153 return true;
1154
1155 return false;
1156}
1157
1158static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = {
1159 .probe = tegra186_usb3_lane_probe,
1160 .remove = tegra186_usb3_lane_remove,
1161 .enable_phy_sleepwalk = tegra186_usb3_enable_phy_sleepwalk,
1162 .disable_phy_sleepwalk = tegra186_usb3_disable_phy_sleepwalk,
1163 .enable_phy_wake = tegra186_usb3_enable_phy_wake,
1164 .disable_phy_wake = tegra186_usb3_disable_phy_wake,
1165 .remote_wake_detected = tegra186_usb3_phy_remote_wake_detected,
1166};
1167
1168static int tegra186_usb3_port_enable(struct tegra_xusb_port *port)
1169{
1170 return 0;
1171}
1172
1173static void tegra186_usb3_port_disable(struct tegra_xusb_port *port)
1174{
1175}
1176
1177static struct tegra_xusb_lane *
1178tegra186_usb3_port_map(struct tegra_xusb_port *port)
1179{
1180 return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
1181}
1182
1183static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = {
1184 .release = tegra_xusb_usb3_port_release,
1185 .remove = tegra_xusb_usb3_port_remove,
1186 .enable = tegra186_usb3_port_enable,
1187 .disable = tegra186_usb3_port_disable,
1188 .map = tegra186_usb3_port_map,
1189};
1190
1191static int tegra186_usb3_phy_power_on(struct phy *phy)
1192{
1193 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1194 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1195 struct tegra_xusb_usb3_port *port;
1196 struct tegra_xusb_usb2_port *usb2;
1197 unsigned int index = lane->index;
1198 struct device *dev = padctl->dev;
1199 u32 value;
1200
1201 port = tegra_xusb_find_usb3_port(padctl, index);
1202 if (!port) {
1203 dev_err(dev, "no port found for USB3 lane %u\n", index);
1204 return -ENODEV;
1205 }
1206
1207 usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
1208 if (!usb2) {
1209 dev_err(dev, "no companion port found for USB3 lane %u\n",
1210 index);
1211 return -ENODEV;
1212 }
1213
1214 mutex_lock(&padctl->lock);
1215
1216 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1217 value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
1218
1219 if (usb2->mode == USB_DR_MODE_UNKNOWN)
1220 value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
1221 else if (usb2->mode == USB_DR_MODE_PERIPHERAL)
1222 value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
1223 else if (usb2->mode == USB_DR_MODE_HOST)
1224 value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
1225 else if (usb2->mode == USB_DR_MODE_OTG)
1226 value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
1227
1228 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
1229
1230 if (padctl->soc->supports_gen2 && port->disable_gen2) {
1231 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
1232 value &= ~(PORTX_SPEED_SUPPORT_MASK <<
1233 PORTX_SPEED_SUPPORT_SHIFT(index));
1234 value |= (PORT_SPEED_SUPPORT_GEN1 <<
1235 PORTX_SPEED_SUPPORT_SHIFT(index));
1236 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
1237 }
1238
1239 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1240 value &= ~SSPX_ELPG_VCORE_DOWN(index);
1241 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1242
1243 usleep_range(100, 200);
1244
1245 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1246 value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1247 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1248
1249 usleep_range(100, 200);
1250
1251 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1252 value &= ~SSPX_ELPG_CLAMP_EN(index);
1253 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1254
1255 mutex_unlock(&padctl->lock);
1256
1257 return 0;
1258}
1259
1260static int tegra186_usb3_phy_power_off(struct phy *phy)
1261{
1262 struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1263 struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1264 struct tegra_xusb_usb3_port *port;
1265 unsigned int index = lane->index;
1266 struct device *dev = padctl->dev;
1267 u32 value;
1268
1269 port = tegra_xusb_find_usb3_port(padctl, index);
1270 if (!port) {
1271 dev_err(dev, "no port found for USB3 lane %u\n", index);
1272 return -ENODEV;
1273 }
1274
1275 mutex_lock(&padctl->lock);
1276
1277 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1278 value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1279 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1280
1281 usleep_range(100, 200);
1282
1283 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1284 value |= SSPX_ELPG_CLAMP_EN(index);
1285 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1286
1287 usleep_range(250, 350);
1288
1289 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1290 value |= SSPX_ELPG_VCORE_DOWN(index);
1291 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1292
1293 mutex_unlock(&padctl->lock);
1294
1295 return 0;
1296}
1297
1298static int tegra186_usb3_phy_init(struct phy *phy)
1299{
1300 return 0;
1301}
1302
1303static int tegra186_usb3_phy_exit(struct phy *phy)
1304{
1305 return 0;
1306}
1307
1308static const struct phy_ops usb3_phy_ops = {
1309 .init = tegra186_usb3_phy_init,
1310 .exit = tegra186_usb3_phy_exit,
1311 .power_on = tegra186_usb3_phy_power_on,
1312 .power_off = tegra186_usb3_phy_power_off,
1313 .owner = THIS_MODULE,
1314};
1315
1316static struct tegra_xusb_pad *
1317tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
1318 const struct tegra_xusb_pad_soc *soc,
1319 struct device_node *np)
1320{
1321 struct tegra_xusb_usb3_pad *usb3;
1322 struct tegra_xusb_pad *pad;
1323 int err;
1324
1325 usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
1326 if (!usb3)
1327 return ERR_PTR(-ENOMEM);
1328
1329 pad = &usb3->base;
1330 pad->ops = &tegra186_usb3_lane_ops;
1331 pad->soc = soc;
1332
1333 err = tegra_xusb_pad_init(pad, padctl, np);
1334 if (err < 0) {
1335 kfree(usb3);
1336 goto out;
1337 }
1338
1339 err = tegra_xusb_pad_register(pad, &usb3_phy_ops);
1340 if (err < 0)
1341 goto unregister;
1342
1343 dev_set_drvdata(&pad->dev, pad);
1344
1345 return pad;
1346
1347unregister:
1348 device_unregister(&pad->dev);
1349out:
1350 return ERR_PTR(err);
1351}
1352
1353static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad)
1354{
1355 struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1356
1357 kfree(usb2);
1358}
1359
1360static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = {
1361 .probe = tegra186_usb3_pad_probe,
1362 .remove = tegra186_usb3_pad_remove,
1363};
1364
1365static const char * const tegra186_usb3_functions[] = {
1366 "xusb",
1367};
1368
1369static int
1370tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
1371{
1372 struct device *dev = padctl->base.dev;
1373 unsigned int i, count;
1374 u32 value, *level;
1375 int err;
1376
1377 count = padctl->base.soc->ports.usb2.count;
1378
1379 level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
1380 if (!level)
1381 return -ENOMEM;
1382
1383 err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
1384 if (err) {
1385 if (err != -EPROBE_DEFER)
1386 dev_err(dev, "failed to read calibration fuse: %d\n",
1387 err);
1388 return err;
1389 }
1390
1391 dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value);
1392
1393 for (i = 0; i < count; i++)
1394 level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) &
1395 HS_CURR_LEVEL_PAD_MASK;
1396
1397 padctl->calib.hs_curr_level = level;
1398
1399 padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
1400 HS_SQUELCH_MASK;
1401 padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
1402 HS_TERM_RANGE_ADJ_MASK;
1403
1404 err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
1405 if (err) {
1406 dev_err(dev, "failed to read calibration fuse: %d\n", err);
1407 return err;
1408 }
1409
1410 dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value);
1411
1412 padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
1413
1414 return 0;
1415}
1416
1417static struct tegra_xusb_padctl *
1418tegra186_xusb_padctl_probe(struct device *dev,
1419 const struct tegra_xusb_padctl_soc *soc)
1420{
1421 struct platform_device *pdev = to_platform_device(dev);
1422 struct tegra186_xusb_padctl *priv;
1423 struct resource *res;
1424 int err;
1425
1426 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1427 if (!priv)
1428 return ERR_PTR(-ENOMEM);
1429
1430 priv->base.dev = dev;
1431 priv->base.soc = soc;
1432
1433 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao");
1434 priv->ao_regs = devm_ioremap_resource(dev, res);
1435 if (IS_ERR(priv->ao_regs))
1436 return ERR_CAST(priv->ao_regs);
1437
1438 err = tegra186_xusb_read_fuse_calibration(priv);
1439 if (err < 0)
1440 return ERR_PTR(err);
1441
1442 return &priv->base;
1443}
1444
1445static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
1446{
1447 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1448
1449 priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);
1450 priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1451 priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
1452 priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1453}
1454
1455static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
1456{
1457 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1458
1459 padctl_writel(padctl, priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX);
1460 padctl_writel(padctl, priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP);
1461 padctl_writel(padctl, priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP);
1462 padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID);
1463}
1464
1465static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
1466{
1467 tegra186_xusb_padctl_save(padctl);
1468
1469 return 0;
1470}
1471
1472static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
1473{
1474 tegra186_xusb_padctl_restore(padctl);
1475
1476 return 0;
1477}
1478
1479static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
1480{
1481}
1482
1483static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
1484 .probe = tegra186_xusb_padctl_probe,
1485 .remove = tegra186_xusb_padctl_remove,
1486 .suspend_noirq = tegra186_xusb_padctl_suspend_noirq,
1487 .resume_noirq = tegra186_xusb_padctl_resume_noirq,
1488 .vbus_override = tegra186_xusb_padctl_vbus_override,
1489};
1490
1491#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
1492static const char * const tegra186_xusb_padctl_supply_names[] = {
1493 "avdd-pll-erefeut",
1494 "avdd-usb",
1495 "vclamp-usb",
1496 "vddio-hsic",
1497};
1498
1499static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
1500 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1501 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1502 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1503};
1504
1505static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
1506 .name = "usb2",
1507 .num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
1508 .lanes = tegra186_usb2_lanes,
1509 .ops = &tegra186_usb2_pad_ops,
1510};
1511
1512static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
1513 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
1514 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
1515 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1516};
1517
1518static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
1519 .name = "usb3",
1520 .num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
1521 .lanes = tegra186_usb3_lanes,
1522 .ops = &tegra186_usb3_pad_ops,
1523};
1524
1525static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
1526 &tegra186_usb2_pad,
1527 &tegra186_usb3_pad,
1528#if 0
1529 &tegra186_hsic_pad,
1530#endif
1531};
1532
1533const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
1534 .num_pads = ARRAY_SIZE(tegra186_pads),
1535 .pads = tegra186_pads,
1536 .ports = {
1537 .usb2 = {
1538 .ops = &tegra186_usb2_port_ops,
1539 .count = 3,
1540 },
1541#if 0
1542 .hsic = {
1543 .ops = &tegra186_hsic_port_ops,
1544 .count = 1,
1545 },
1546#endif
1547 .usb3 = {
1548 .ops = &tegra186_usb3_port_ops,
1549 .count = 3,
1550 },
1551 },
1552 .ops = &tegra186_xusb_padctl_ops,
1553 .supply_names = tegra186_xusb_padctl_supply_names,
1554 .num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
1555};
1556EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
1557#endif
1558
1559#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
1560static const char * const tegra194_xusb_padctl_supply_names[] = {
1561 "avdd-usb",
1562 "vclamp-usb",
1563};
1564
1565static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
1566 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1567 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1568 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1569 TEGRA186_LANE("usb2-3", 0, 0, 0, usb2),
1570};
1571
1572static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
1573 .name = "usb2",
1574 .num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
1575 .lanes = tegra194_usb2_lanes,
1576 .ops = &tegra186_usb2_pad_ops,
1577};
1578
1579static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
1580 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
1581 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
1582 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1583 TEGRA186_LANE("usb3-3", 0, 0, 0, usb3),
1584};
1585
1586static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
1587 .name = "usb3",
1588 .num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
1589 .lanes = tegra194_usb3_lanes,
1590 .ops = &tegra186_usb3_pad_ops,
1591};
1592
1593static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
1594 &tegra194_usb2_pad,
1595 &tegra194_usb3_pad,
1596};
1597
1598const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
1599 .num_pads = ARRAY_SIZE(tegra194_pads),
1600 .pads = tegra194_pads,
1601 .ports = {
1602 .usb2 = {
1603 .ops = &tegra186_usb2_port_ops,
1604 .count = 4,
1605 },
1606 .usb3 = {
1607 .ops = &tegra186_usb3_port_ops,
1608 .count = 4,
1609 },
1610 },
1611 .ops = &tegra186_xusb_padctl_ops,
1612 .supply_names = tegra194_xusb_padctl_supply_names,
1613 .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1614 .supports_gen2 = true,
1615};
1616EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
1617#endif
1618
1619MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
1620MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
1621MODULE_LICENSE("GPL v2");
1622
