1
2
3
4
5
6
7
8
9
10
11
12
13
14#include <linux/errno.h>
15#include <linux/kernel.h>
16
17#include "core.h"
18#include "sh_pfc.h"
19
20#define CPU_ALL_GP(fn, sfx) \
21 PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
22 PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
23 PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
24 PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
25 PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
26 PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
27 PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
28
29#define CPU_ALL_NOGP(fn) \
30 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
31 PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
32 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
33 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
34 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
35 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
36 PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
37 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
38
39
40
41
42
43
44
45#define GPSR0_8 F_(MLB_SIG, IP0_27_24)
46#define GPSR0_7 F_(MLB_DAT, IP0_23_20)
47#define GPSR0_6 F_(MLB_CLK, IP0_19_16)
48#define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12)
49#define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8)
50#define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4)
51#define GPSR0_2 F_(IRQ0_A, IP0_3_0)
52#define GPSR0_1 FM(USB0_OVC)
53#define GPSR0_0 FM(USB0_PWEN)
54
55
56#define GPSR1_31 F_(QPOLB, IP4_27_24)
57#define GPSR1_30 F_(QPOLA, IP4_23_20)
58#define GPSR1_29 F_(DU_CDE, IP4_19_16)
59#define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12)
60#define GPSR1_27 F_(DU_DISP, IP4_11_8)
61#define GPSR1_26 F_(DU_VSYNC, IP4_7_4)
62#define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
63#define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28)
64#define GPSR1_23 F_(DU_DR7, IP3_27_24)
65#define GPSR1_22 F_(DU_DR6, IP3_23_20)
66#define GPSR1_21 F_(DU_DR5, IP3_19_16)
67#define GPSR1_20 F_(DU_DR4, IP3_15_12)
68#define GPSR1_19 F_(DU_DR3, IP3_11_8)
69#define GPSR1_18 F_(DU_DR2, IP3_7_4)
70#define GPSR1_17 F_(DU_DR1, IP3_3_0)
71#define GPSR1_16 F_(DU_DR0, IP2_31_28)
72#define GPSR1_15 F_(DU_DG7, IP2_27_24)
73#define GPSR1_14 F_(DU_DG6, IP2_23_20)
74#define GPSR1_13 F_(DU_DG5, IP2_19_16)
75#define GPSR1_12 F_(DU_DG4, IP2_15_12)
76#define GPSR1_11 F_(DU_DG3, IP2_11_8)
77#define GPSR1_10 F_(DU_DG2, IP2_7_4)
78#define GPSR1_9 F_(DU_DG1, IP2_3_0)
79#define GPSR1_8 F_(DU_DG0, IP1_31_28)
80#define GPSR1_7 F_(DU_DB7, IP1_27_24)
81#define GPSR1_6 F_(DU_DB6, IP1_23_20)
82#define GPSR1_5 F_(DU_DB5, IP1_19_16)
83#define GPSR1_4 F_(DU_DB4, IP1_15_12)
84#define GPSR1_3 F_(DU_DB3, IP1_11_8)
85#define GPSR1_2 F_(DU_DB2, IP1_7_4)
86#define GPSR1_1 F_(DU_DB1, IP1_3_0)
87#define GPSR1_0 F_(DU_DB0, IP0_31_28)
88
89
90#define GPSR2_31 F_(NFCE_N, IP8_19_16)
91#define GPSR2_30 F_(NFCLE, IP8_15_12)
92#define GPSR2_29 F_(NFALE, IP8_11_8)
93#define GPSR2_28 F_(VI4_CLKENB, IP8_7_4)
94#define GPSR2_27 F_(VI4_FIELD, IP8_3_0)
95#define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28)
96#define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24)
97#define GPSR2_24 F_(VI4_DATA23, IP7_23_20)
98#define GPSR2_23 F_(VI4_DATA22, IP7_19_16)
99#define GPSR2_22 F_(VI4_DATA21, IP7_15_12)
100#define GPSR2_21 F_(VI4_DATA20, IP7_11_8)
101#define GPSR2_20 F_(VI4_DATA19, IP7_7_4)
102#define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
103#define GPSR2_18 F_(VI4_DATA17, IP6_31_28)
104#define GPSR2_17 F_(VI4_DATA16, IP6_27_24)
105#define GPSR2_16 F_(VI4_DATA15, IP6_23_20)
106#define GPSR2_15 F_(VI4_DATA14, IP6_19_16)
107#define GPSR2_14 F_(VI4_DATA13, IP6_15_12)
108#define GPSR2_13 F_(VI4_DATA12, IP6_11_8)
109#define GPSR2_12 F_(VI4_DATA11, IP6_7_4)
110#define GPSR2_11 F_(VI4_DATA10, IP6_3_0)
111#define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
112#define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
113#define GPSR2_8 F_(VI4_DATA7, IP5_23_20)
114#define GPSR2_7 F_(VI4_DATA6, IP5_19_16)
115#define GPSR2_6 F_(VI4_DATA5, IP5_15_12)
116#define GPSR2_5 FM(VI4_DATA4)
117#define GPSR2_4 F_(VI4_DATA3, IP5_11_8)
118#define GPSR2_3 F_(VI4_DATA2, IP5_7_4)
119#define GPSR2_2 F_(VI4_DATA1, IP5_3_0)
120#define GPSR2_1 F_(VI4_DATA0, IP4_31_28)
121#define GPSR2_0 FM(VI4_CLK)
122
123
124#define GPSR3_9 F_(NFDATA7, IP9_31_28)
125#define GPSR3_8 F_(NFDATA6, IP9_27_24)
126#define GPSR3_7 F_(NFDATA5, IP9_23_20)
127#define GPSR3_6 F_(NFDATA4, IP9_19_16)
128#define GPSR3_5 F_(NFDATA3, IP9_15_12)
129#define GPSR3_4 F_(NFDATA2, IP9_11_8)
130#define GPSR3_3 F_(NFDATA1, IP9_7_4)
131#define GPSR3_2 F_(NFDATA0, IP9_3_0)
132#define GPSR3_1 F_(NFWE_N, IP8_31_28)
133#define GPSR3_0 F_(NFRE_N, IP8_27_24)
134
135
136#define GPSR4_31 F_(CAN0_RX_A, IP12_27_24)
137#define GPSR4_30 F_(CAN1_TX_A, IP13_7_4)
138#define GPSR4_29 F_(CAN1_RX_A, IP13_3_0)
139#define GPSR4_28 F_(CAN0_TX_A, IP12_31_28)
140#define GPSR4_27 FM(TX2)
141#define GPSR4_26 FM(RX2)
142#define GPSR4_25 F_(SCK2, IP12_11_8)
143#define GPSR4_24 F_(TX1_A, IP12_7_4)
144#define GPSR4_23 F_(RX1_A, IP12_3_0)
145#define GPSR4_22 F_(SCK1_A, IP11_31_28)
146#define GPSR4_21 F_(TX0_A, IP11_27_24)
147#define GPSR4_20 F_(RX0_A, IP11_23_20)
148#define GPSR4_19 F_(SCK0_A, IP11_19_16)
149#define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12)
150#define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8)
151#define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4)
152#define GPSR4_15 FM(MSIOF0_RXD)
153#define GPSR4_14 FM(MSIOF0_TXD)
154#define GPSR4_13 FM(MSIOF0_SYNC)
155#define GPSR4_12 FM(MSIOF0_SCK)
156#define GPSR4_11 F_(SDA1, IP11_3_0)
157#define GPSR4_10 F_(SCL1, IP10_31_28)
158#define GPSR4_9 FM(SDA0)
159#define GPSR4_8 FM(SCL0)
160#define GPSR4_7 F_(SSI_WS4_A, IP10_27_24)
161#define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20)
162#define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16)
163#define GPSR4_4 F_(SSI_WS34, IP10_15_12)
164#define GPSR4_3 F_(SSI_SDATA3, IP10_11_8)
165#define GPSR4_2 F_(SSI_SCK34, IP10_7_4)
166#define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0)
167#define GPSR4_0 F_(NFRB_N, IP8_23_20)
168
169
170#define GPSR5_20 FM(AVB0_LINK)
171#define GPSR5_19 FM(AVB0_PHY_INT)
172#define GPSR5_18 FM(AVB0_MAGIC)
173#define GPSR5_17 FM(AVB0_MDC)
174#define GPSR5_16 FM(AVB0_MDIO)
175#define GPSR5_15 FM(AVB0_TXCREFCLK)
176#define GPSR5_14 FM(AVB0_TD3)
177#define GPSR5_13 FM(AVB0_TD2)
178#define GPSR5_12 FM(AVB0_TD1)
179#define GPSR5_11 FM(AVB0_TD0)
180#define GPSR5_10 FM(AVB0_TXC)
181#define GPSR5_9 FM(AVB0_TX_CTL)
182#define GPSR5_8 FM(AVB0_RD3)
183#define GPSR5_7 FM(AVB0_RD2)
184#define GPSR5_6 FM(AVB0_RD1)
185#define GPSR5_5 FM(AVB0_RD0)
186#define GPSR5_4 FM(AVB0_RXC)
187#define GPSR5_3 FM(AVB0_RX_CTL)
188#define GPSR5_2 F_(CAN_CLK, IP12_23_20)
189#define GPSR5_1 F_(TPU0TO1_A, IP12_19_16)
190#define GPSR5_0 F_(TPU0TO0_A, IP12_15_12)
191
192
193#define GPSR6_13 FM(RPC_INT_N)
194#define GPSR6_12 FM(RPC_RESET_N)
195#define GPSR6_11 FM(QSPI1_SSL)
196#define GPSR6_10 FM(QSPI1_IO3)
197#define GPSR6_9 FM(QSPI1_IO2)
198#define GPSR6_8 FM(QSPI1_MISO_IO1)
199#define GPSR6_7 FM(QSPI1_MOSI_IO0)
200#define GPSR6_6 FM(QSPI1_SPCLK)
201#define GPSR6_5 FM(QSPI0_SSL)
202#define GPSR6_4 FM(QSPI0_IO3)
203#define GPSR6_3 FM(QSPI0_IO2)
204#define GPSR6_2 FM(QSPI0_MISO_IO1)
205#define GPSR6_1 FM(QSPI0_MOSI_IO0)
206#define GPSR6_0 FM(QSPI0_SPCLK)
207
208
209#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241
242
243#define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275
276
277#define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309
310
311#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321
322#define PINMUX_GPSR \
323\
324 GPSR1_31 GPSR2_31 GPSR4_31 \
325 GPSR1_30 GPSR2_30 GPSR4_30 \
326 GPSR1_29 GPSR2_29 GPSR4_29 \
327 GPSR1_28 GPSR2_28 GPSR4_28 \
328 GPSR1_27 GPSR2_27 GPSR4_27 \
329 GPSR1_26 GPSR2_26 GPSR4_26 \
330 GPSR1_25 GPSR2_25 GPSR4_25 \
331 GPSR1_24 GPSR2_24 GPSR4_24 \
332 GPSR1_23 GPSR2_23 GPSR4_23 \
333 GPSR1_22 GPSR2_22 GPSR4_22 \
334 GPSR1_21 GPSR2_21 GPSR4_21 \
335 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \
336 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \
337 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \
338 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \
339 GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \
340 GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \
341 GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \
342 GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \
343 GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \
344 GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \
345 GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \
346 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
347GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
348GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
349GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
350GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
351GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
352GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
353GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
354GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
355GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
356
357#define PINMUX_IPSR \
358\
359FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
360FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
361FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
362FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
363FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
364FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
365FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
366FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
367\
368FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
369FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
370FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
371FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
372FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
373FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
374FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
375FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
376\
377FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
378FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
379FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
380FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
381FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
382FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
383FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
384FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
385\
386FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \
387FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \
388FM(IP12_11_8) IP12_11_8 \
389FM(IP12_15_12) IP12_15_12 \
390FM(IP12_19_16) IP12_19_16 \
391FM(IP12_23_20) IP12_23_20 \
392FM(IP12_27_24) IP12_27_24 \
393FM(IP12_31_28) IP12_31_28 \
394
395
396#define REV4(f0, f1, f2, f3) f0 f2 f1 f3
397
398
399#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
400#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
401#define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
402#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
403#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
404#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
405#define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0))
406#define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0))
407#define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
408#define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
409#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
410#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
411#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
412#define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1)
413#define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1)
414#define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1)
415#define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1)
416#define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1)
417#define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
418#define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
419#define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1)
420#define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
421
422#define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1)
423#define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1)
424#define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
425#define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
426#define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
427#define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
428
429
430#define PINMUX_MOD_SELS \
431\
432 MOD_SEL1_31 \
433MOD_SEL0_30 MOD_SEL1_30 \
434MOD_SEL0_29 MOD_SEL1_29 \
435MOD_SEL0_28 MOD_SEL1_28 \
436MOD_SEL0_27 MOD_SEL1_27 \
437MOD_SEL0_26 MOD_SEL1_26 \
438MOD_SEL0_25 \
439MOD_SEL0_24_23 \
440MOD_SEL0_22_21 \
441MOD_SEL0_20_19 \
442MOD_SEL0_18_17 \
443MOD_SEL0_15 \
444MOD_SEL0_14 \
445MOD_SEL0_13 \
446MOD_SEL0_12 \
447MOD_SEL0_11 \
448MOD_SEL0_10 \
449MOD_SEL0_5 \
450MOD_SEL0_4 \
451MOD_SEL0_3 \
452MOD_SEL0_2 \
453MOD_SEL0_1 \
454MOD_SEL0_0
455
456enum {
457 PINMUX_RESERVED = 0,
458
459 PINMUX_DATA_BEGIN,
460 GP_ALL(DATA),
461 PINMUX_DATA_END,
462
463#define F_(x, y)
464#define FM(x) FN_##x,
465 PINMUX_FUNCTION_BEGIN,
466 GP_ALL(FN),
467 PINMUX_GPSR
468 PINMUX_IPSR
469 PINMUX_MOD_SELS
470 PINMUX_FUNCTION_END,
471#undef F_
472#undef FM
473
474#define F_(x, y)
475#define FM(x) x##_MARK,
476 PINMUX_MARK_BEGIN,
477 PINMUX_GPSR
478 PINMUX_IPSR
479 PINMUX_MOD_SELS
480 PINMUX_MARK_END,
481#undef F_
482#undef FM
483};
484
485static const u16 pinmux_data[] = {
486 PINMUX_DATA_GP_ALL(),
487
488 PINMUX_SINGLE(USB0_OVC),
489 PINMUX_SINGLE(USB0_PWEN),
490 PINMUX_SINGLE(VI4_DATA4),
491 PINMUX_SINGLE(VI4_CLK),
492 PINMUX_SINGLE(TX2),
493 PINMUX_SINGLE(RX2),
494 PINMUX_SINGLE(AVB0_LINK),
495 PINMUX_SINGLE(AVB0_PHY_INT),
496 PINMUX_SINGLE(AVB0_MAGIC),
497 PINMUX_SINGLE(AVB0_MDC),
498 PINMUX_SINGLE(AVB0_MDIO),
499 PINMUX_SINGLE(AVB0_TXCREFCLK),
500 PINMUX_SINGLE(AVB0_TD3),
501 PINMUX_SINGLE(AVB0_TD2),
502 PINMUX_SINGLE(AVB0_TD1),
503 PINMUX_SINGLE(AVB0_TD0),
504 PINMUX_SINGLE(AVB0_TXC),
505 PINMUX_SINGLE(AVB0_TX_CTL),
506 PINMUX_SINGLE(AVB0_RD3),
507 PINMUX_SINGLE(AVB0_RD2),
508 PINMUX_SINGLE(AVB0_RD1),
509 PINMUX_SINGLE(AVB0_RD0),
510 PINMUX_SINGLE(AVB0_RXC),
511 PINMUX_SINGLE(AVB0_RX_CTL),
512 PINMUX_SINGLE(RPC_INT_N),
513 PINMUX_SINGLE(RPC_RESET_N),
514 PINMUX_SINGLE(QSPI1_SSL),
515 PINMUX_SINGLE(QSPI1_IO3),
516 PINMUX_SINGLE(QSPI1_IO2),
517 PINMUX_SINGLE(QSPI1_MISO_IO1),
518 PINMUX_SINGLE(QSPI1_MOSI_IO0),
519 PINMUX_SINGLE(QSPI1_SPCLK),
520 PINMUX_SINGLE(QSPI0_SSL),
521 PINMUX_SINGLE(QSPI0_IO3),
522 PINMUX_SINGLE(QSPI0_IO2),
523 PINMUX_SINGLE(QSPI0_MISO_IO1),
524 PINMUX_SINGLE(QSPI0_MOSI_IO0),
525 PINMUX_SINGLE(QSPI0_SPCLK),
526 PINMUX_SINGLE(SCL0),
527 PINMUX_SINGLE(SDA0),
528 PINMUX_SINGLE(MSIOF0_RXD),
529 PINMUX_SINGLE(MSIOF0_TXD),
530 PINMUX_SINGLE(MSIOF0_SYNC),
531 PINMUX_SINGLE(MSIOF0_SCK),
532
533
534 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
535 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
536
537 PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
538
539 PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
540 PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
541
542 PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD),
543 PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
544
545 PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK),
546 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
547 PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
548
549 PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT),
550 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1),
551 PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
552 PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
553
554 PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
555 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
556 PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
557 PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
558
559 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
560 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
561 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
562
563
564 PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
565 PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
566 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
567
568 PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2),
569 PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2),
570 PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1),
571
572 PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3),
573 PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3),
574 PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1),
575
576 PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
577 PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
578 PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
579
580 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5),
581 PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5),
582 PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1),
583
584 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6),
585 PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6),
586 PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1),
587
588 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7),
589 PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7),
590 PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1),
591
592 PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0),
593 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8),
594 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1),
595
596
597 PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1),
598 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9),
599 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1),
600
601 PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2),
602 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10),
603
604 PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3),
605 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11),
606 PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0),
607
608 PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
609 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
610 PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
611
612 PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5),
613 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13),
614 PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1),
615
616 PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6),
617 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14),
618 PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1),
619
620 PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7),
621 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15),
622 PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1),
623
624 PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0),
625 PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16),
626 PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1),
627
628
629 PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
630 PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
631 PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
632
633 PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
634 PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
635 PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
636
637 PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3),
638 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19),
639 PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2),
640
641 PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4),
642 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20),
643 PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1),
644
645 PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5),
646 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21),
647 PINMUX_IPSR_GPSR(IP3_19_16, NMI),
648
649 PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6),
650 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22),
651 PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2),
652
653 PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
654 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
655 PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
656
657 PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0),
658 PINMUX_IPSR_GPSR(IP3_31_28, QCLK),
659
660
661 PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
662 PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
663 PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
664
665 PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC),
666 PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS),
667 PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0),
668
669 PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP),
670 PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE),
671 PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2),
672
673 PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE),
674 PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE),
675 PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1),
676 PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1),
677
678 PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE),
679 PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE),
680 PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1),
681
682 PINMUX_IPSR_GPSR(IP4_23_20, QPOLA),
683 PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1),
684
685 PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
686 PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
687
688 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0),
689 PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0),
690
691
692 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1),
693 PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0),
694
695 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2),
696 PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0),
697
698 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3),
699 PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0),
700
701 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5),
702 PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0),
703
704 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6),
705 PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0),
706
707 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7),
708 PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0),
709
710 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
711
712 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
713 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
714 PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
715
716
717 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10),
718 PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0),
719
720 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11),
721 PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0),
722
723 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12),
724 PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0),
725
726 PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13),
727 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0),
728 PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N),
729
730 PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14),
731 PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1),
732 PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N),
733
734 PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15),
735 PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1),
736
737 PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16),
738 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0),
739
740 PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17),
741 PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0),
742
743
744 PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18),
745 PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0),
746
747 PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19),
748 PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1),
749 PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15),
750
751 PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20),
752 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0),
753 PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14),
754
755 PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21),
756 PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0),
757
758 PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13),
759 PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22),
760 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0),
761
762 PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12),
763 PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23),
764 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
765
766 PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11),
767
768 PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N),
769 PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1),
770 PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10),
771
772 PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N),
773 PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1),
774 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9),
775
776
777 PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD),
778 PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB),
779 PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0),
780 PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK),
781 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8),
782
783 PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB),
784 PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1),
785 PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N),
786 PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0),
787
788 PINMUX_IPSR_GPSR(IP8_11_8, NFALE),
789 PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1),
790 PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1),
791 PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1),
792
793 PINMUX_IPSR_GPSR(IP8_15_12, NFCLE),
794 PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1),
795 PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0),
796 PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1),
797
798 PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N),
799 PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0),
800 PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1),
801
802 PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N),
803 PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0),
804 PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1),
805
806 PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N),
807 PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD),
808
809 PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N),
810 PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK),
811
812
813 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0),
814 PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0),
815
816 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1),
817 PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1),
818
819 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2),
820 PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2),
821
822 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3),
823 PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3),
824
825 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4),
826 PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4),
827
828 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5),
829 PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5),
830
831 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6),
832 PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6),
833
834 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7),
835 PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7),
836
837
838 PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA),
839 PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1),
840
841 PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34),
842 PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0),
843
844 PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3),
845 PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0),
846
847 PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34),
848 PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0),
849
850 PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0),
851 PINMUX_IPSR_GPSR(IP10_19_16, HSCK0),
852 PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT),
853 PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1),
854 PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1),
855
856 PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0),
857 PINMUX_IPSR_GPSR(IP10_23_20, HTX0),
858 PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0),
859 PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1),
860
861 PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0),
862 PINMUX_IPSR_GPSR(IP10_27_24, HRX0),
863 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
864 PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1),
865
866 PINMUX_IPSR_GPSR(IP10_31_28, SCL1),
867 PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N),
868
869
870 PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
871 PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N),
872
873 PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
874 PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
875
876 PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD),
877 PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
878
879 PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD),
880 PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
881
882 PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0),
883 PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC),
884 PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
885
886 PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0),
887 PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1),
888 PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
889
890 PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
891 PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2),
892 PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1),
893
894 PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0),
895 PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2),
896 PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B),
897 PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1),
898 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1),
899
900
901 PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0),
902 PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N),
903 PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
904
905 PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
906 PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N),
907 PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
908
909 PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
910 PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1),
911 PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B),
912
913 PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A),
914 PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
915 PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N),
916
917 PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A),
918 PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
919 PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N),
920
921 PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK),
922 PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
923 PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1),
924 PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1),
925
926 PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0),
927 PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX),
928 PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1),
929
930 PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0),
931 PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX),
932 PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1),
933
934
935 PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0),
936 PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX),
937 PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A),
938
939 PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0),
940 PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX),
941 PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
942};
943
944
945
946
947enum {
948 GP_ASSIGN_LAST(),
949 NOGP_ALL(),
950};
951
952static const struct sh_pfc_pin pinmux_pins[] = {
953 PINMUX_GPIO_GP_ALL(),
954 PINMUX_NOGP_ALL(),
955};
956
957
958static const unsigned int audio_clk_a_pins[] = {
959
960 RCAR_GP_PIN(4, 1),
961};
962static const unsigned int audio_clk_a_mux[] = {
963 AUDIO_CLKA_MARK,
964};
965static const unsigned int audio_clk_b_pins[] = {
966
967 RCAR_GP_PIN(2, 27),
968};
969static const unsigned int audio_clk_b_mux[] = {
970 AUDIO_CLKB_MARK,
971};
972static const unsigned int audio_clkout_pins[] = {
973
974 RCAR_GP_PIN(4, 5),
975};
976static const unsigned int audio_clkout_mux[] = {
977 AUDIO_CLKOUT_MARK,
978};
979static const unsigned int audio_clkout1_pins[] = {
980
981 RCAR_GP_PIN(4, 22),
982};
983static const unsigned int audio_clkout1_mux[] = {
984 AUDIO_CLKOUT1_MARK,
985};
986
987
988static const unsigned int avb0_link_pins[] = {
989
990 RCAR_GP_PIN(5, 20),
991};
992static const unsigned int avb0_link_mux[] = {
993 AVB0_LINK_MARK,
994};
995static const unsigned int avb0_magic_pins[] = {
996
997 RCAR_GP_PIN(5, 18),
998};
999static const unsigned int avb0_magic_mux[] = {
1000 AVB0_MAGIC_MARK,
1001};
1002static const unsigned int avb0_phy_int_pins[] = {
1003
1004 RCAR_GP_PIN(5, 19),
1005};
1006static const unsigned int avb0_phy_int_mux[] = {
1007 AVB0_PHY_INT_MARK,
1008};
1009static const unsigned int avb0_mdio_pins[] = {
1010
1011 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
1012};
1013static const unsigned int avb0_mdio_mux[] = {
1014 AVB0_MDC_MARK, AVB0_MDIO_MARK,
1015};
1016static const unsigned int avb0_mii_pins[] = {
1017
1018
1019
1020
1021
1022
1023
1024 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1025 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1026 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1027 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1028 RCAR_GP_PIN(5, 15),
1029};
1030static const unsigned int avb0_mii_mux[] = {
1031 AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK,
1032 AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
1033 AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK,
1034 AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
1035 AVB0_TXCREFCLK_MARK,
1036};
1037static const unsigned int avb0_avtp_pps_a_pins[] = {
1038
1039 RCAR_GP_PIN(5, 2),
1040};
1041static const unsigned int avb0_avtp_pps_a_mux[] = {
1042 AVB0_AVTP_PPS_A_MARK,
1043};
1044static const unsigned int avb0_avtp_match_a_pins[] = {
1045
1046 RCAR_GP_PIN(5, 1),
1047};
1048static const unsigned int avb0_avtp_match_a_mux[] = {
1049 AVB0_AVTP_MATCH_A_MARK,
1050};
1051static const unsigned int avb0_avtp_capture_a_pins[] = {
1052
1053 RCAR_GP_PIN(5, 0),
1054};
1055static const unsigned int avb0_avtp_capture_a_mux[] = {
1056 AVB0_AVTP_CAPTURE_A_MARK,
1057};
1058static const unsigned int avb0_avtp_pps_b_pins[] = {
1059
1060 RCAR_GP_PIN(4, 16),
1061};
1062static const unsigned int avb0_avtp_pps_b_mux[] = {
1063 AVB0_AVTP_PPS_B_MARK,
1064};
1065static const unsigned int avb0_avtp_match_b_pins[] = {
1066
1067 RCAR_GP_PIN(4, 18),
1068};
1069static const unsigned int avb0_avtp_match_b_mux[] = {
1070 AVB0_AVTP_MATCH_B_MARK,
1071};
1072static const unsigned int avb0_avtp_capture_b_pins[] = {
1073
1074 RCAR_GP_PIN(4, 17),
1075};
1076static const unsigned int avb0_avtp_capture_b_mux[] = {
1077 AVB0_AVTP_CAPTURE_B_MARK,
1078};
1079
1080
1081static const unsigned int can0_data_a_pins[] = {
1082
1083 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1084};
1085static const unsigned int can0_data_a_mux[] = {
1086 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1087};
1088static const unsigned int can0_data_b_pins[] = {
1089
1090 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
1091};
1092static const unsigned int can0_data_b_mux[] = {
1093 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1094};
1095static const unsigned int can1_data_a_pins[] = {
1096
1097 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1098};
1099static const unsigned int can1_data_a_mux[] = {
1100 CAN1_TX_A_MARK, CAN1_RX_A_MARK,
1101};
1102static const unsigned int can1_data_b_pins[] = {
1103
1104 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
1105};
1106static const unsigned int can1_data_b_mux[] = {
1107 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1108};
1109
1110
1111static const unsigned int can_clk_pins[] = {
1112
1113 RCAR_GP_PIN(5, 2),
1114};
1115static const unsigned int can_clk_mux[] = {
1116 CAN_CLK_MARK,
1117};
1118
1119
1120static const unsigned int canfd0_data_pins[] = {
1121
1122 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1123};
1124static const unsigned int canfd0_data_mux[] = {
1125 CANFD0_TX_MARK, CANFD0_RX_MARK,
1126};
1127static const unsigned int canfd1_data_pins[] = {
1128
1129 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1130};
1131static const unsigned int canfd1_data_mux[] = {
1132 CANFD1_TX_MARK, CANFD1_RX_MARK,
1133};
1134
1135
1136static const unsigned int du_rgb666_pins[] = {
1137
1138 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1139 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1140 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1141 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1142 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1143 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1144};
1145static const unsigned int du_rgb666_mux[] = {
1146 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1147 DU_DR3_MARK, DU_DR2_MARK,
1148 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1149 DU_DG3_MARK, DU_DG2_MARK,
1150 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1151 DU_DB3_MARK, DU_DB2_MARK,
1152};
1153static const unsigned int du_rgb888_pins[] = {
1154
1155 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1156 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1157 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1158 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1159 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1160 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1161 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1162 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1163 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1164};
1165static const unsigned int du_rgb888_mux[] = {
1166 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1167 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1168 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1169 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1170 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1171 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1172};
1173static const unsigned int du_clk_in_1_pins[] = {
1174
1175 RCAR_GP_PIN(1, 28),
1176};
1177static const unsigned int du_clk_in_1_mux[] = {
1178 DU_DOTCLKIN1_MARK
1179};
1180static const unsigned int du_clk_out_0_pins[] = {
1181
1182 RCAR_GP_PIN(1, 24),
1183};
1184static const unsigned int du_clk_out_0_mux[] = {
1185 DU_DOTCLKOUT0_MARK
1186};
1187static const unsigned int du_sync_pins[] = {
1188
1189 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1190};
1191static const unsigned int du_sync_mux[] = {
1192 DU_VSYNC_MARK, DU_HSYNC_MARK
1193};
1194static const unsigned int du_disp_cde_pins[] = {
1195
1196 RCAR_GP_PIN(1, 28),
1197};
1198static const unsigned int du_disp_cde_mux[] = {
1199 DU_DISP_CDE_MARK,
1200};
1201static const unsigned int du_cde_pins[] = {
1202
1203 RCAR_GP_PIN(1, 29),
1204};
1205static const unsigned int du_cde_mux[] = {
1206 DU_CDE_MARK,
1207};
1208static const unsigned int du_disp_pins[] = {
1209
1210 RCAR_GP_PIN(1, 27),
1211};
1212static const unsigned int du_disp_mux[] = {
1213 DU_DISP_MARK,
1214};
1215
1216
1217static const unsigned int i2c0_pins[] = {
1218
1219 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1220};
1221static const unsigned int i2c0_mux[] = {
1222 SCL0_MARK, SDA0_MARK,
1223};
1224static const unsigned int i2c1_pins[] = {
1225
1226 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1227};
1228static const unsigned int i2c1_mux[] = {
1229 SCL1_MARK, SDA1_MARK,
1230};
1231static const unsigned int i2c2_a_pins[] = {
1232
1233 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1234};
1235static const unsigned int i2c2_a_mux[] = {
1236 SCL2_A_MARK, SDA2_A_MARK,
1237};
1238static const unsigned int i2c2_b_pins[] = {
1239
1240 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30),
1241};
1242static const unsigned int i2c2_b_mux[] = {
1243 SCL2_B_MARK, SDA2_B_MARK,
1244};
1245static const unsigned int i2c3_a_pins[] = {
1246
1247 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1248};
1249static const unsigned int i2c3_a_mux[] = {
1250 SCL3_A_MARK, SDA3_A_MARK,
1251};
1252static const unsigned int i2c3_b_pins[] = {
1253
1254 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1255};
1256static const unsigned int i2c3_b_mux[] = {
1257 SCL3_B_MARK, SDA3_B_MARK,
1258};
1259
1260
1261static const unsigned int mmc_data1_pins[] = {
1262
1263 RCAR_GP_PIN(3, 2),
1264};
1265static const unsigned int mmc_data1_mux[] = {
1266 MMC_D0_MARK,
1267};
1268static const unsigned int mmc_data4_pins[] = {
1269
1270 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1271 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1272};
1273static const unsigned int mmc_data4_mux[] = {
1274 MMC_D0_MARK, MMC_D1_MARK,
1275 MMC_D2_MARK, MMC_D3_MARK,
1276};
1277static const unsigned int mmc_data8_pins[] = {
1278
1279 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1280 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1281 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1282 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1283};
1284static const unsigned int mmc_data8_mux[] = {
1285 MMC_D0_MARK, MMC_D1_MARK,
1286 MMC_D2_MARK, MMC_D3_MARK,
1287 MMC_D4_MARK, MMC_D5_MARK,
1288 MMC_D6_MARK, MMC_D7_MARK,
1289};
1290static const unsigned int mmc_ctrl_pins[] = {
1291
1292 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1293};
1294static const unsigned int mmc_ctrl_mux[] = {
1295 MMC_CLK_MARK, MMC_CMD_MARK,
1296};
1297
1298
1299static const unsigned int msiof0_clk_pins[] = {
1300
1301 RCAR_GP_PIN(4, 12),
1302};
1303
1304static const unsigned int msiof0_clk_mux[] = {
1305 MSIOF0_SCK_MARK,
1306};
1307
1308static const unsigned int msiof0_sync_pins[] = {
1309
1310 RCAR_GP_PIN(4, 13),
1311};
1312
1313static const unsigned int msiof0_sync_mux[] = {
1314 MSIOF0_SYNC_MARK,
1315};
1316
1317static const unsigned int msiof0_ss1_pins[] = {
1318
1319 RCAR_GP_PIN(4, 20),
1320};
1321
1322static const unsigned int msiof0_ss1_mux[] = {
1323 MSIOF0_SS1_MARK,
1324};
1325
1326static const unsigned int msiof0_ss2_pins[] = {
1327
1328 RCAR_GP_PIN(4, 21),
1329};
1330
1331static const unsigned int msiof0_ss2_mux[] = {
1332 MSIOF0_SS2_MARK,
1333};
1334
1335static const unsigned int msiof0_txd_pins[] = {
1336
1337 RCAR_GP_PIN(4, 14),
1338};
1339
1340static const unsigned int msiof0_txd_mux[] = {
1341 MSIOF0_TXD_MARK,
1342};
1343
1344static const unsigned int msiof0_rxd_pins[] = {
1345
1346 RCAR_GP_PIN(4, 15),
1347};
1348
1349static const unsigned int msiof0_rxd_mux[] = {
1350 MSIOF0_RXD_MARK,
1351};
1352
1353
1354static const unsigned int msiof1_clk_pins[] = {
1355
1356 RCAR_GP_PIN(4, 16),
1357};
1358
1359static const unsigned int msiof1_clk_mux[] = {
1360 MSIOF1_SCK_MARK,
1361};
1362
1363static const unsigned int msiof1_sync_pins[] = {
1364
1365 RCAR_GP_PIN(4, 19),
1366};
1367
1368static const unsigned int msiof1_sync_mux[] = {
1369 MSIOF1_SYNC_MARK,
1370};
1371
1372static const unsigned int msiof1_ss1_pins[] = {
1373
1374 RCAR_GP_PIN(4, 25),
1375};
1376
1377static const unsigned int msiof1_ss1_mux[] = {
1378 MSIOF1_SS1_MARK,
1379};
1380
1381static const unsigned int msiof1_ss2_pins[] = {
1382
1383 RCAR_GP_PIN(4, 22),
1384};
1385
1386static const unsigned int msiof1_ss2_mux[] = {
1387 MSIOF1_SS2_MARK,
1388};
1389
1390static const unsigned int msiof1_txd_pins[] = {
1391
1392 RCAR_GP_PIN(4, 17),
1393};
1394
1395static const unsigned int msiof1_txd_mux[] = {
1396 MSIOF1_TXD_MARK,
1397};
1398
1399static const unsigned int msiof1_rxd_pins[] = {
1400
1401 RCAR_GP_PIN(4, 18),
1402};
1403
1404static const unsigned int msiof1_rxd_mux[] = {
1405 MSIOF1_RXD_MARK,
1406};
1407
1408
1409static const unsigned int msiof2_clk_pins[] = {
1410
1411 RCAR_GP_PIN(0, 3),
1412};
1413
1414static const unsigned int msiof2_clk_mux[] = {
1415 MSIOF2_SCK_MARK,
1416};
1417
1418static const unsigned int msiof2_sync_a_pins[] = {
1419
1420 RCAR_GP_PIN(0, 6),
1421};
1422
1423static const unsigned int msiof2_sync_a_mux[] = {
1424 MSIOF2_SYNC_A_MARK,
1425};
1426
1427static const unsigned int msiof2_sync_b_pins[] = {
1428
1429 RCAR_GP_PIN(0, 2),
1430};
1431
1432static const unsigned int msiof2_sync_b_mux[] = {
1433 MSIOF2_SYNC_B_MARK,
1434};
1435
1436static const unsigned int msiof2_ss1_pins[] = {
1437
1438 RCAR_GP_PIN(0, 7),
1439};
1440
1441static const unsigned int msiof2_ss1_mux[] = {
1442 MSIOF2_SS1_MARK,
1443};
1444
1445static const unsigned int msiof2_ss2_pins[] = {
1446
1447 RCAR_GP_PIN(0, 8),
1448};
1449
1450static const unsigned int msiof2_ss2_mux[] = {
1451 MSIOF2_SS2_MARK,
1452};
1453
1454static const unsigned int msiof2_txd_pins[] = {
1455
1456 RCAR_GP_PIN(0, 4),
1457};
1458
1459static const unsigned int msiof2_txd_mux[] = {
1460 MSIOF2_TXD_MARK,
1461};
1462
1463static const unsigned int msiof2_rxd_pins[] = {
1464
1465 RCAR_GP_PIN(0, 5),
1466};
1467
1468static const unsigned int msiof2_rxd_mux[] = {
1469 MSIOF2_RXD_MARK,
1470};
1471
1472
1473static const unsigned int msiof3_clk_a_pins[] = {
1474
1475 RCAR_GP_PIN(2, 24),
1476};
1477
1478static const unsigned int msiof3_clk_a_mux[] = {
1479 MSIOF3_SCK_A_MARK,
1480};
1481
1482static const unsigned int msiof3_sync_a_pins[] = {
1483
1484 RCAR_GP_PIN(2, 21),
1485};
1486
1487static const unsigned int msiof3_sync_a_mux[] = {
1488 MSIOF3_SYNC_A_MARK,
1489};
1490
1491static const unsigned int msiof3_ss1_a_pins[] = {
1492
1493 RCAR_GP_PIN(2, 14),
1494};
1495
1496static const unsigned int msiof3_ss1_a_mux[] = {
1497 MSIOF3_SS1_A_MARK,
1498};
1499
1500static const unsigned int msiof3_ss2_a_pins[] = {
1501
1502 RCAR_GP_PIN(2, 10),
1503};
1504
1505static const unsigned int msiof3_ss2_a_mux[] = {
1506 MSIOF3_SS2_A_MARK,
1507};
1508
1509static const unsigned int msiof3_txd_a_pins[] = {
1510
1511 RCAR_GP_PIN(2, 22),
1512};
1513
1514static const unsigned int msiof3_txd_a_mux[] = {
1515 MSIOF3_TXD_A_MARK,
1516};
1517
1518static const unsigned int msiof3_rxd_a_pins[] = {
1519
1520 RCAR_GP_PIN(2, 23),
1521};
1522
1523static const unsigned int msiof3_rxd_a_mux[] = {
1524 MSIOF3_RXD_A_MARK,
1525};
1526
1527static const unsigned int msiof3_clk_b_pins[] = {
1528
1529 RCAR_GP_PIN(1, 8),
1530};
1531
1532static const unsigned int msiof3_clk_b_mux[] = {
1533 MSIOF3_SCK_B_MARK,
1534};
1535
1536static const unsigned int msiof3_sync_b_pins[] = {
1537
1538 RCAR_GP_PIN(1, 9),
1539};
1540
1541static const unsigned int msiof3_sync_b_mux[] = {
1542 MSIOF3_SYNC_B_MARK,
1543};
1544
1545static const unsigned int msiof3_ss1_b_pins[] = {
1546
1547 RCAR_GP_PIN(1, 6),
1548};
1549
1550static const unsigned int msiof3_ss1_b_mux[] = {
1551 MSIOF3_SS1_B_MARK,
1552};
1553
1554static const unsigned int msiof3_ss2_b_pins[] = {
1555
1556 RCAR_GP_PIN(1, 7),
1557};
1558
1559static const unsigned int msiof3_ss2_b_mux[] = {
1560 MSIOF3_SS2_B_MARK,
1561};
1562
1563static const unsigned int msiof3_txd_b_pins[] = {
1564
1565 RCAR_GP_PIN(1, 0),
1566};
1567
1568static const unsigned int msiof3_txd_b_mux[] = {
1569 MSIOF3_TXD_B_MARK,
1570};
1571
1572static const unsigned int msiof3_rxd_b_pins[] = {
1573
1574 RCAR_GP_PIN(1, 1),
1575};
1576
1577static const unsigned int msiof3_rxd_b_mux[] = {
1578 MSIOF3_RXD_B_MARK,
1579};
1580
1581
1582static const unsigned int pwm0_a_pins[] = {
1583
1584 RCAR_GP_PIN(2, 1),
1585};
1586
1587static const unsigned int pwm0_a_mux[] = {
1588 PWM0_A_MARK,
1589};
1590
1591static const unsigned int pwm0_b_pins[] = {
1592
1593 RCAR_GP_PIN(1, 18),
1594};
1595
1596static const unsigned int pwm0_b_mux[] = {
1597 PWM0_B_MARK,
1598};
1599
1600static const unsigned int pwm0_c_pins[] = {
1601
1602 RCAR_GP_PIN(2, 29),
1603};
1604
1605static const unsigned int pwm0_c_mux[] = {
1606 PWM0_C_MARK,
1607};
1608
1609
1610static const unsigned int pwm1_a_pins[] = {
1611
1612 RCAR_GP_PIN(2, 2),
1613};
1614
1615static const unsigned int pwm1_a_mux[] = {
1616 PWM1_A_MARK,
1617};
1618
1619static const unsigned int pwm1_b_pins[] = {
1620
1621 RCAR_GP_PIN(1, 19),
1622};
1623
1624static const unsigned int pwm1_b_mux[] = {
1625 PWM1_B_MARK,
1626};
1627
1628static const unsigned int pwm1_c_pins[] = {
1629
1630 RCAR_GP_PIN(2, 30),
1631};
1632
1633static const unsigned int pwm1_c_mux[] = {
1634 PWM1_C_MARK,
1635};
1636
1637
1638static const unsigned int pwm2_a_pins[] = {
1639
1640 RCAR_GP_PIN(2, 3),
1641};
1642
1643static const unsigned int pwm2_a_mux[] = {
1644 PWM2_A_MARK,
1645};
1646
1647static const unsigned int pwm2_b_pins[] = {
1648
1649 RCAR_GP_PIN(1, 22),
1650};
1651
1652static const unsigned int pwm2_b_mux[] = {
1653 PWM2_B_MARK,
1654};
1655
1656static const unsigned int pwm2_c_pins[] = {
1657
1658 RCAR_GP_PIN(2, 31),
1659};
1660
1661static const unsigned int pwm2_c_mux[] = {
1662 PWM2_C_MARK,
1663};
1664
1665
1666static const unsigned int pwm3_a_pins[] = {
1667
1668 RCAR_GP_PIN(2, 4),
1669};
1670
1671static const unsigned int pwm3_a_mux[] = {
1672 PWM3_A_MARK,
1673};
1674
1675static const unsigned int pwm3_b_pins[] = {
1676
1677 RCAR_GP_PIN(1, 27),
1678};
1679
1680static const unsigned int pwm3_b_mux[] = {
1681 PWM3_B_MARK,
1682};
1683
1684static const unsigned int pwm3_c_pins[] = {
1685
1686 RCAR_GP_PIN(4, 0),
1687};
1688
1689static const unsigned int pwm3_c_mux[] = {
1690 PWM3_C_MARK,
1691};
1692
1693
1694static const unsigned int scif0_data_a_pins[] = {
1695
1696 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
1697};
1698static const unsigned int scif0_data_a_mux[] = {
1699 RX0_A_MARK, TX0_A_MARK,
1700};
1701static const unsigned int scif0_clk_a_pins[] = {
1702
1703 RCAR_GP_PIN(4, 19),
1704};
1705static const unsigned int scif0_clk_a_mux[] = {
1706 SCK0_A_MARK,
1707};
1708static const unsigned int scif0_data_b_pins[] = {
1709
1710 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28),
1711};
1712static const unsigned int scif0_data_b_mux[] = {
1713 RX0_B_MARK, TX0_B_MARK,
1714};
1715static const unsigned int scif0_clk_b_pins[] = {
1716
1717 RCAR_GP_PIN(5, 2),
1718};
1719static const unsigned int scif0_clk_b_mux[] = {
1720 SCK0_B_MARK,
1721};
1722static const unsigned int scif0_ctrl_pins[] = {
1723
1724 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1725};
1726static const unsigned int scif0_ctrl_mux[] = {
1727 RTS0_N_MARK, CTS0_N_MARK,
1728};
1729
1730static const unsigned int scif1_data_a_pins[] = {
1731
1732 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
1733};
1734static const unsigned int scif1_data_a_mux[] = {
1735 RX1_A_MARK, TX1_A_MARK,
1736};
1737static const unsigned int scif1_clk_a_pins[] = {
1738
1739 RCAR_GP_PIN(4, 22),
1740};
1741static const unsigned int scif1_clk_a_mux[] = {
1742 SCK1_A_MARK,
1743};
1744static const unsigned int scif1_data_b_pins[] = {
1745
1746 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28),
1747};
1748static const unsigned int scif1_data_b_mux[] = {
1749 RX1_B_MARK, TX1_B_MARK,
1750};
1751static const unsigned int scif1_clk_b_pins[] = {
1752
1753 RCAR_GP_PIN(2, 25),
1754};
1755static const unsigned int scif1_clk_b_mux[] = {
1756 SCK1_B_MARK,
1757};
1758static const unsigned int scif1_ctrl_pins[] = {
1759
1760 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1761};
1762static const unsigned int scif1_ctrl_mux[] = {
1763 RTS1_N_MARK, CTS1_N_MARK,
1764};
1765
1766
1767static const unsigned int scif2_data_pins[] = {
1768
1769 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
1770};
1771static const unsigned int scif2_data_mux[] = {
1772 RX2_MARK, TX2_MARK,
1773};
1774static const unsigned int scif2_clk_pins[] = {
1775
1776 RCAR_GP_PIN(4, 25),
1777};
1778static const unsigned int scif2_clk_mux[] = {
1779 SCK2_MARK,
1780};
1781
1782static const unsigned int scif3_data_a_pins[] = {
1783
1784 RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00),
1785};
1786static const unsigned int scif3_data_a_mux[] = {
1787 RX3_A_MARK, TX3_A_MARK,
1788};
1789static const unsigned int scif3_clk_a_pins[] = {
1790
1791 RCAR_GP_PIN(2, 30),
1792};
1793static const unsigned int scif3_clk_a_mux[] = {
1794 SCK3_A_MARK,
1795};
1796static const unsigned int scif3_data_b_pins[] = {
1797
1798 RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31),
1799};
1800static const unsigned int scif3_data_b_mux[] = {
1801 RX3_B_MARK, TX3_B_MARK,
1802};
1803static const unsigned int scif3_clk_b_pins[] = {
1804
1805 RCAR_GP_PIN(1, 29),
1806};
1807static const unsigned int scif3_clk_b_mux[] = {
1808 SCK3_B_MARK,
1809};
1810
1811static const unsigned int scif4_data_a_pins[] = {
1812
1813 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1814};
1815static const unsigned int scif4_data_a_mux[] = {
1816 RX4_A_MARK, TX4_A_MARK,
1817};
1818static const unsigned int scif4_clk_a_pins[] = {
1819
1820 RCAR_GP_PIN(2, 6),
1821};
1822static const unsigned int scif4_clk_a_mux[] = {
1823 SCK4_A_MARK,
1824};
1825static const unsigned int scif4_data_b_pins[] = {
1826
1827 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
1828};
1829static const unsigned int scif4_data_b_mux[] = {
1830 RX4_B_MARK, TX4_B_MARK,
1831};
1832static const unsigned int scif4_clk_b_pins[] = {
1833
1834 RCAR_GP_PIN(1, 15),
1835};
1836static const unsigned int scif4_clk_b_mux[] = {
1837 SCK4_B_MARK,
1838};
1839
1840static const unsigned int scif5_data_a_pins[] = {
1841
1842 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1843};
1844static const unsigned int scif5_data_a_mux[] = {
1845 RX5_A_MARK, TX5_A_MARK,
1846};
1847static const unsigned int scif5_clk_a_pins[] = {
1848
1849 RCAR_GP_PIN(0, 6),
1850};
1851static const unsigned int scif5_clk_a_mux[] = {
1852 SCK5_A_MARK,
1853};
1854static const unsigned int scif5_data_b_pins[] = {
1855
1856 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1857};
1858static const unsigned int scif5_data_b_mux[] = {
1859 RX5_B_MARK, TX5_B_MARK,
1860};
1861static const unsigned int scif5_clk_b_pins[] = {
1862
1863 RCAR_GP_PIN(1, 3),
1864};
1865static const unsigned int scif5_clk_b_mux[] = {
1866 SCK5_B_MARK,
1867};
1868
1869static const unsigned int scif_clk_pins[] = {
1870
1871 RCAR_GP_PIN(2, 27),
1872};
1873static const unsigned int scif_clk_mux[] = {
1874 SCIF_CLK_MARK,
1875};
1876
1877
1878static const unsigned int ssi3_data_pins[] = {
1879
1880 RCAR_GP_PIN(4, 3),
1881};
1882static const unsigned int ssi3_data_mux[] = {
1883 SSI_SDATA3_MARK,
1884};
1885static const unsigned int ssi34_ctrl_pins[] = {
1886
1887 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
1888};
1889static const unsigned int ssi34_ctrl_mux[] = {
1890 SSI_SCK34_MARK, SSI_WS34_MARK,
1891};
1892static const unsigned int ssi4_ctrl_a_pins[] = {
1893
1894 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1895};
1896static const unsigned int ssi4_ctrl_a_mux[] = {
1897 SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
1898};
1899static const unsigned int ssi4_data_a_pins[] = {
1900
1901 RCAR_GP_PIN(4, 6),
1902};
1903static const unsigned int ssi4_data_a_mux[] = {
1904 SSI_SDATA4_A_MARK,
1905};
1906static const unsigned int ssi4_ctrl_b_pins[] = {
1907
1908 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
1909};
1910static const unsigned int ssi4_ctrl_b_mux[] = {
1911 SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
1912};
1913static const unsigned int ssi4_data_b_pins[] = {
1914
1915 RCAR_GP_PIN(2, 16),
1916};
1917static const unsigned int ssi4_data_b_mux[] = {
1918 SSI_SDATA4_B_MARK,
1919};
1920
1921
1922static const unsigned int usb0_pins[] = {
1923
1924 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1925};
1926static const unsigned int usb0_mux[] = {
1927 USB0_PWEN_MARK, USB0_OVC_MARK,
1928};
1929
1930
1931static const unsigned int vin4_data18_pins[] = {
1932 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1933 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1934 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1935 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1936 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
1937 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1938 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1939 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1940 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1941};
1942static const unsigned int vin4_data18_mux[] = {
1943 VI4_DATA2_MARK, VI4_DATA3_MARK,
1944 VI4_DATA4_MARK, VI4_DATA5_MARK,
1945 VI4_DATA6_MARK, VI4_DATA7_MARK,
1946 VI4_DATA10_MARK, VI4_DATA11_MARK,
1947 VI4_DATA12_MARK, VI4_DATA13_MARK,
1948 VI4_DATA14_MARK, VI4_DATA15_MARK,
1949 VI4_DATA18_MARK, VI4_DATA19_MARK,
1950 VI4_DATA20_MARK, VI4_DATA21_MARK,
1951 VI4_DATA22_MARK, VI4_DATA23_MARK,
1952};
1953static const union vin_data vin4_data_pins = {
1954 .data24 = {
1955 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1956 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1957 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1958 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1959 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
1960 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1961 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
1962 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1963 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1964 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1965 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1966 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1967 },
1968};
1969static const union vin_data vin4_data_mux = {
1970 .data24 = {
1971 VI4_DATA0_MARK, VI4_DATA1_MARK,
1972 VI4_DATA2_MARK, VI4_DATA3_MARK,
1973 VI4_DATA4_MARK, VI4_DATA5_MARK,
1974 VI4_DATA6_MARK, VI4_DATA7_MARK,
1975 VI4_DATA8_MARK, VI4_DATA9_MARK,
1976 VI4_DATA10_MARK, VI4_DATA11_MARK,
1977 VI4_DATA12_MARK, VI4_DATA13_MARK,
1978 VI4_DATA14_MARK, VI4_DATA15_MARK,
1979 VI4_DATA16_MARK, VI4_DATA17_MARK,
1980 VI4_DATA18_MARK, VI4_DATA19_MARK,
1981 VI4_DATA20_MARK, VI4_DATA21_MARK,
1982 VI4_DATA22_MARK, VI4_DATA23_MARK,
1983 },
1984};
1985static const unsigned int vin4_sync_pins[] = {
1986
1987 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1988};
1989static const unsigned int vin4_sync_mux[] = {
1990 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1991};
1992static const unsigned int vin4_field_pins[] = {
1993
1994 RCAR_GP_PIN(2, 27),
1995};
1996static const unsigned int vin4_field_mux[] = {
1997 VI4_FIELD_MARK,
1998};
1999static const unsigned int vin4_clkenb_pins[] = {
2000
2001 RCAR_GP_PIN(2, 28),
2002};
2003static const unsigned int vin4_clkenb_mux[] = {
2004 VI4_CLKENB_MARK,
2005};
2006static const unsigned int vin4_clk_pins[] = {
2007
2008 RCAR_GP_PIN(2, 0),
2009};
2010static const unsigned int vin4_clk_mux[] = {
2011 VI4_CLK_MARK,
2012};
2013
2014static const struct sh_pfc_pin_group pinmux_groups[] = {
2015 SH_PFC_PIN_GROUP(audio_clk_a),
2016 SH_PFC_PIN_GROUP(audio_clk_b),
2017 SH_PFC_PIN_GROUP(audio_clkout),
2018 SH_PFC_PIN_GROUP(audio_clkout1),
2019 SH_PFC_PIN_GROUP(avb0_link),
2020 SH_PFC_PIN_GROUP(avb0_magic),
2021 SH_PFC_PIN_GROUP(avb0_phy_int),
2022 SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio),
2023 SH_PFC_PIN_GROUP(avb0_mdio),
2024 SH_PFC_PIN_GROUP(avb0_mii),
2025 SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
2026 SH_PFC_PIN_GROUP(avb0_avtp_match_a),
2027 SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
2028 SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
2029 SH_PFC_PIN_GROUP(avb0_avtp_match_b),
2030 SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
2031 SH_PFC_PIN_GROUP(can0_data_a),
2032 SH_PFC_PIN_GROUP(can0_data_b),
2033 SH_PFC_PIN_GROUP(can1_data_a),
2034 SH_PFC_PIN_GROUP(can1_data_b),
2035 SH_PFC_PIN_GROUP(can_clk),
2036 SH_PFC_PIN_GROUP(canfd0_data),
2037 SH_PFC_PIN_GROUP(canfd1_data),
2038 SH_PFC_PIN_GROUP(du_rgb666),
2039 SH_PFC_PIN_GROUP(du_rgb888),
2040 SH_PFC_PIN_GROUP(du_clk_in_1),
2041 SH_PFC_PIN_GROUP(du_clk_out_0),
2042 SH_PFC_PIN_GROUP(du_sync),
2043 SH_PFC_PIN_GROUP(du_disp_cde),
2044 SH_PFC_PIN_GROUP(du_cde),
2045 SH_PFC_PIN_GROUP(du_disp),
2046 SH_PFC_PIN_GROUP(i2c0),
2047 SH_PFC_PIN_GROUP(i2c1),
2048 SH_PFC_PIN_GROUP(i2c2_a),
2049 SH_PFC_PIN_GROUP(i2c2_b),
2050 SH_PFC_PIN_GROUP(i2c3_a),
2051 SH_PFC_PIN_GROUP(i2c3_b),
2052 SH_PFC_PIN_GROUP(mmc_data1),
2053 SH_PFC_PIN_GROUP(mmc_data4),
2054 SH_PFC_PIN_GROUP(mmc_data8),
2055 SH_PFC_PIN_GROUP(mmc_ctrl),
2056 SH_PFC_PIN_GROUP(msiof0_clk),
2057 SH_PFC_PIN_GROUP(msiof0_sync),
2058 SH_PFC_PIN_GROUP(msiof0_ss1),
2059 SH_PFC_PIN_GROUP(msiof0_ss2),
2060 SH_PFC_PIN_GROUP(msiof0_txd),
2061 SH_PFC_PIN_GROUP(msiof0_rxd),
2062 SH_PFC_PIN_GROUP(msiof1_clk),
2063 SH_PFC_PIN_GROUP(msiof1_sync),
2064 SH_PFC_PIN_GROUP(msiof1_ss1),
2065 SH_PFC_PIN_GROUP(msiof1_ss2),
2066 SH_PFC_PIN_GROUP(msiof1_txd),
2067 SH_PFC_PIN_GROUP(msiof1_rxd),
2068 SH_PFC_PIN_GROUP(msiof2_clk),
2069 SH_PFC_PIN_GROUP(msiof2_sync_a),
2070 SH_PFC_PIN_GROUP(msiof2_sync_b),
2071 SH_PFC_PIN_GROUP(msiof2_ss1),
2072 SH_PFC_PIN_GROUP(msiof2_ss2),
2073 SH_PFC_PIN_GROUP(msiof2_txd),
2074 SH_PFC_PIN_GROUP(msiof2_rxd),
2075 SH_PFC_PIN_GROUP(msiof3_clk_a),
2076 SH_PFC_PIN_GROUP(msiof3_sync_a),
2077 SH_PFC_PIN_GROUP(msiof3_ss1_a),
2078 SH_PFC_PIN_GROUP(msiof3_ss2_a),
2079 SH_PFC_PIN_GROUP(msiof3_txd_a),
2080 SH_PFC_PIN_GROUP(msiof3_rxd_a),
2081 SH_PFC_PIN_GROUP(msiof3_clk_b),
2082 SH_PFC_PIN_GROUP(msiof3_sync_b),
2083 SH_PFC_PIN_GROUP(msiof3_ss1_b),
2084 SH_PFC_PIN_GROUP(msiof3_ss2_b),
2085 SH_PFC_PIN_GROUP(msiof3_txd_b),
2086 SH_PFC_PIN_GROUP(msiof3_rxd_b),
2087 SH_PFC_PIN_GROUP(pwm0_a),
2088 SH_PFC_PIN_GROUP(pwm0_b),
2089 SH_PFC_PIN_GROUP(pwm0_c),
2090 SH_PFC_PIN_GROUP(pwm1_a),
2091 SH_PFC_PIN_GROUP(pwm1_b),
2092 SH_PFC_PIN_GROUP(pwm1_c),
2093 SH_PFC_PIN_GROUP(pwm2_a),
2094 SH_PFC_PIN_GROUP(pwm2_b),
2095 SH_PFC_PIN_GROUP(pwm2_c),
2096 SH_PFC_PIN_GROUP(pwm3_a),
2097 SH_PFC_PIN_GROUP(pwm3_b),
2098 SH_PFC_PIN_GROUP(pwm3_c),
2099 SH_PFC_PIN_GROUP(scif0_data_a),
2100 SH_PFC_PIN_GROUP(scif0_clk_a),
2101 SH_PFC_PIN_GROUP(scif0_data_b),
2102 SH_PFC_PIN_GROUP(scif0_clk_b),
2103 SH_PFC_PIN_GROUP(scif0_ctrl),
2104 SH_PFC_PIN_GROUP(scif1_data_a),
2105 SH_PFC_PIN_GROUP(scif1_clk_a),
2106 SH_PFC_PIN_GROUP(scif1_data_b),
2107 SH_PFC_PIN_GROUP(scif1_clk_b),
2108 SH_PFC_PIN_GROUP(scif1_ctrl),
2109 SH_PFC_PIN_GROUP(scif2_data),
2110 SH_PFC_PIN_GROUP(scif2_clk),
2111 SH_PFC_PIN_GROUP(scif3_data_a),
2112 SH_PFC_PIN_GROUP(scif3_clk_a),
2113 SH_PFC_PIN_GROUP(scif3_data_b),
2114 SH_PFC_PIN_GROUP(scif3_clk_b),
2115 SH_PFC_PIN_GROUP(scif4_data_a),
2116 SH_PFC_PIN_GROUP(scif4_clk_a),
2117 SH_PFC_PIN_GROUP(scif4_data_b),
2118 SH_PFC_PIN_GROUP(scif4_clk_b),
2119 SH_PFC_PIN_GROUP(scif5_data_a),
2120 SH_PFC_PIN_GROUP(scif5_clk_a),
2121 SH_PFC_PIN_GROUP(scif5_data_b),
2122 SH_PFC_PIN_GROUP(scif5_clk_b),
2123 SH_PFC_PIN_GROUP(scif_clk),
2124 SH_PFC_PIN_GROUP(ssi3_data),
2125 SH_PFC_PIN_GROUP(ssi34_ctrl),
2126 SH_PFC_PIN_GROUP(ssi4_ctrl_a),
2127 SH_PFC_PIN_GROUP(ssi4_data_a),
2128 SH_PFC_PIN_GROUP(ssi4_ctrl_b),
2129 SH_PFC_PIN_GROUP(ssi4_data_b),
2130 SH_PFC_PIN_GROUP(usb0),
2131 VIN_DATA_PIN_GROUP(vin4_data, 8),
2132 VIN_DATA_PIN_GROUP(vin4_data, 10),
2133 VIN_DATA_PIN_GROUP(vin4_data, 12),
2134 VIN_DATA_PIN_GROUP(vin4_data, 16),
2135 SH_PFC_PIN_GROUP(vin4_data18),
2136 VIN_DATA_PIN_GROUP(vin4_data, 20),
2137 VIN_DATA_PIN_GROUP(vin4_data, 24),
2138 SH_PFC_PIN_GROUP(vin4_sync),
2139 SH_PFC_PIN_GROUP(vin4_field),
2140 SH_PFC_PIN_GROUP(vin4_clkenb),
2141 SH_PFC_PIN_GROUP(vin4_clk),
2142};
2143
2144static const char * const audio_clk_groups[] = {
2145 "audio_clk_a",
2146 "audio_clk_b",
2147 "audio_clkout",
2148 "audio_clkout1",
2149};
2150
2151static const char * const avb0_groups[] = {
2152 "avb0_link",
2153 "avb0_magic",
2154 "avb0_phy_int",
2155 "avb0_mdc",
2156 "avb0_mdio",
2157 "avb0_mii",
2158 "avb0_avtp_pps_a",
2159 "avb0_avtp_match_a",
2160 "avb0_avtp_capture_a",
2161 "avb0_avtp_pps_b",
2162 "avb0_avtp_match_b",
2163 "avb0_avtp_capture_b",
2164};
2165
2166static const char * const can0_groups[] = {
2167 "can0_data_a",
2168 "can0_data_b",
2169};
2170static const char * const can1_groups[] = {
2171 "can1_data_a",
2172 "can1_data_b",
2173};
2174static const char * const can_clk_groups[] = {
2175 "can_clk",
2176};
2177
2178static const char * const canfd0_groups[] = {
2179 "canfd0_data",
2180};
2181static const char * const canfd1_groups[] = {
2182 "canfd1_data",
2183};
2184
2185static const char * const du_groups[] = {
2186 "du_rgb666",
2187 "du_rgb888",
2188 "du_clk_in_1",
2189 "du_clk_out_0",
2190 "du_sync",
2191 "du_disp_cde",
2192 "du_cde",
2193 "du_disp",
2194};
2195
2196static const char * const i2c0_groups[] = {
2197 "i2c0",
2198};
2199static const char * const i2c1_groups[] = {
2200 "i2c1",
2201};
2202
2203static const char * const i2c2_groups[] = {
2204 "i2c2_a",
2205 "i2c2_b",
2206};
2207
2208static const char * const i2c3_groups[] = {
2209 "i2c3_a",
2210 "i2c3_b",
2211};
2212
2213static const char * const mmc_groups[] = {
2214 "mmc_data1",
2215 "mmc_data4",
2216 "mmc_data8",
2217 "mmc_ctrl",
2218};
2219
2220static const char * const pwm0_groups[] = {
2221 "pwm0_a",
2222 "pwm0_b",
2223 "pwm0_c",
2224};
2225
2226static const char * const pwm1_groups[] = {
2227 "pwm1_a",
2228 "pwm1_b",
2229 "pwm1_c",
2230};
2231
2232static const char * const pwm2_groups[] = {
2233 "pwm2_a",
2234 "pwm2_b",
2235 "pwm2_c",
2236};
2237
2238static const char * const pwm3_groups[] = {
2239 "pwm3_a",
2240 "pwm3_b",
2241 "pwm3_c",
2242};
2243
2244static const char * const scif0_groups[] = {
2245 "scif0_data_a",
2246 "scif0_clk_a",
2247 "scif0_data_b",
2248 "scif0_clk_b",
2249 "scif0_ctrl",
2250};
2251
2252static const char * const scif1_groups[] = {
2253 "scif1_data_a",
2254 "scif1_clk_a",
2255 "scif1_data_b",
2256 "scif1_clk_b",
2257 "scif1_ctrl",
2258};
2259
2260static const char * const scif2_groups[] = {
2261 "scif2_data",
2262 "scif2_clk",
2263};
2264
2265static const char * const scif3_groups[] = {
2266 "scif3_data_a",
2267 "scif3_clk_a",
2268 "scif3_data_b",
2269 "scif3_clk_b",
2270};
2271
2272static const char * const scif4_groups[] = {
2273 "scif4_data_a",
2274 "scif4_clk_a",
2275 "scif4_data_b",
2276 "scif4_clk_b",
2277};
2278
2279static const char * const scif5_groups[] = {
2280 "scif5_data_a",
2281 "scif5_clk_a",
2282 "scif5_data_b",
2283 "scif5_clk_b",
2284};
2285
2286static const char * const scif_clk_groups[] = {
2287 "scif_clk",
2288};
2289
2290static const char * const ssi_groups[] = {
2291 "ssi3_data",
2292 "ssi34_ctrl",
2293 "ssi4_ctrl_a",
2294 "ssi4_data_a",
2295 "ssi4_ctrl_b",
2296 "ssi4_data_b",
2297};
2298
2299static const char * const usb0_groups[] = {
2300 "usb0",
2301};
2302
2303static const char * const vin4_groups[] = {
2304 "vin4_data8",
2305 "vin4_data10",
2306 "vin4_data12",
2307 "vin4_data16",
2308 "vin4_data18",
2309 "vin4_data20",
2310 "vin4_data24",
2311 "vin4_sync",
2312 "vin4_field",
2313 "vin4_clkenb",
2314 "vin4_clk",
2315};
2316
2317static const char * const msiof0_groups[] = {
2318 "msiof0_clk",
2319 "msiof0_sync",
2320 "msiof0_ss1",
2321 "msiof0_ss2",
2322 "msiof0_txd",
2323 "msiof0_rxd",
2324};
2325
2326static const char * const msiof1_groups[] = {
2327 "msiof1_clk",
2328 "msiof1_sync",
2329 "msiof1_ss1",
2330 "msiof1_ss2",
2331 "msiof1_txd",
2332 "msiof1_rxd",
2333};
2334
2335static const char * const msiof2_groups[] = {
2336 "msiof2_clk",
2337 "msiof2_sync_a",
2338 "msiof2_sync_b",
2339 "msiof2_ss1",
2340 "msiof2_ss2",
2341 "msiof2_txd",
2342 "msiof2_rxd",
2343};
2344
2345static const char * const msiof3_groups[] = {
2346 "msiof3_clk_a",
2347 "msiof3_sync_a",
2348 "msiof3_ss1_a",
2349 "msiof3_ss2_a",
2350 "msiof3_txd_a",
2351 "msiof3_rxd_a",
2352 "msiof3_clk_b",
2353 "msiof3_sync_b",
2354 "msiof3_ss1_b",
2355 "msiof3_ss2_b",
2356 "msiof3_txd_b",
2357 "msiof3_rxd_b",
2358};
2359
2360static const struct sh_pfc_function pinmux_functions[] = {
2361 SH_PFC_FUNCTION(audio_clk),
2362 SH_PFC_FUNCTION(avb0),
2363 SH_PFC_FUNCTION(can0),
2364 SH_PFC_FUNCTION(can1),
2365 SH_PFC_FUNCTION(can_clk),
2366 SH_PFC_FUNCTION(canfd0),
2367 SH_PFC_FUNCTION(canfd1),
2368 SH_PFC_FUNCTION(du),
2369 SH_PFC_FUNCTION(i2c0),
2370 SH_PFC_FUNCTION(i2c1),
2371 SH_PFC_FUNCTION(i2c2),
2372 SH_PFC_FUNCTION(i2c3),
2373 SH_PFC_FUNCTION(mmc),
2374 SH_PFC_FUNCTION(msiof0),
2375 SH_PFC_FUNCTION(msiof1),
2376 SH_PFC_FUNCTION(msiof2),
2377 SH_PFC_FUNCTION(msiof3),
2378 SH_PFC_FUNCTION(pwm0),
2379 SH_PFC_FUNCTION(pwm1),
2380 SH_PFC_FUNCTION(pwm2),
2381 SH_PFC_FUNCTION(pwm3),
2382 SH_PFC_FUNCTION(scif0),
2383 SH_PFC_FUNCTION(scif1),
2384 SH_PFC_FUNCTION(scif2),
2385 SH_PFC_FUNCTION(scif3),
2386 SH_PFC_FUNCTION(scif4),
2387 SH_PFC_FUNCTION(scif5),
2388 SH_PFC_FUNCTION(scif_clk),
2389 SH_PFC_FUNCTION(ssi),
2390 SH_PFC_FUNCTION(usb0),
2391 SH_PFC_FUNCTION(vin4),
2392};
2393
2394static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2395#define F_(x, y) FN_##y
2396#define FM(x) FN_##x
2397 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2398 0, 0,
2399 0, 0,
2400 0, 0,
2401 0, 0,
2402 0, 0,
2403 0, 0,
2404 0, 0,
2405 0, 0,
2406 0, 0,
2407 0, 0,
2408 0, 0,
2409 0, 0,
2410 0, 0,
2411 0, 0,
2412 0, 0,
2413 0, 0,
2414 0, 0,
2415 0, 0,
2416 0, 0,
2417 0, 0,
2418 0, 0,
2419 0, 0,
2420 0, 0,
2421 GP_0_8_FN, GPSR0_8,
2422 GP_0_7_FN, GPSR0_7,
2423 GP_0_6_FN, GPSR0_6,
2424 GP_0_5_FN, GPSR0_5,
2425 GP_0_4_FN, GPSR0_4,
2426 GP_0_3_FN, GPSR0_3,
2427 GP_0_2_FN, GPSR0_2,
2428 GP_0_1_FN, GPSR0_1,
2429 GP_0_0_FN, GPSR0_0, ))
2430 },
2431 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2432 GP_1_31_FN, GPSR1_31,
2433 GP_1_30_FN, GPSR1_30,
2434 GP_1_29_FN, GPSR1_29,
2435 GP_1_28_FN, GPSR1_28,
2436 GP_1_27_FN, GPSR1_27,
2437 GP_1_26_FN, GPSR1_26,
2438 GP_1_25_FN, GPSR1_25,
2439 GP_1_24_FN, GPSR1_24,
2440 GP_1_23_FN, GPSR1_23,
2441 GP_1_22_FN, GPSR1_22,
2442 GP_1_21_FN, GPSR1_21,
2443 GP_1_20_FN, GPSR1_20,
2444 GP_1_19_FN, GPSR1_19,
2445 GP_1_18_FN, GPSR1_18,
2446 GP_1_17_FN, GPSR1_17,
2447 GP_1_16_FN, GPSR1_16,
2448 GP_1_15_FN, GPSR1_15,
2449 GP_1_14_FN, GPSR1_14,
2450 GP_1_13_FN, GPSR1_13,
2451 GP_1_12_FN, GPSR1_12,
2452 GP_1_11_FN, GPSR1_11,
2453 GP_1_10_FN, GPSR1_10,
2454 GP_1_9_FN, GPSR1_9,
2455 GP_1_8_FN, GPSR1_8,
2456 GP_1_7_FN, GPSR1_7,
2457 GP_1_6_FN, GPSR1_6,
2458 GP_1_5_FN, GPSR1_5,
2459 GP_1_4_FN, GPSR1_4,
2460 GP_1_3_FN, GPSR1_3,
2461 GP_1_2_FN, GPSR1_2,
2462 GP_1_1_FN, GPSR1_1,
2463 GP_1_0_FN, GPSR1_0, ))
2464 },
2465 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2466 GP_2_31_FN, GPSR2_31,
2467 GP_2_30_FN, GPSR2_30,
2468 GP_2_29_FN, GPSR2_29,
2469 GP_2_28_FN, GPSR2_28,
2470 GP_2_27_FN, GPSR2_27,
2471 GP_2_26_FN, GPSR2_26,
2472 GP_2_25_FN, GPSR2_25,
2473 GP_2_24_FN, GPSR2_24,
2474 GP_2_23_FN, GPSR2_23,
2475 GP_2_22_FN, GPSR2_22,
2476 GP_2_21_FN, GPSR2_21,
2477 GP_2_20_FN, GPSR2_20,
2478 GP_2_19_FN, GPSR2_19,
2479 GP_2_18_FN, GPSR2_18,
2480 GP_2_17_FN, GPSR2_17,
2481 GP_2_16_FN, GPSR2_16,
2482 GP_2_15_FN, GPSR2_15,
2483 GP_2_14_FN, GPSR2_14,
2484 GP_2_13_FN, GPSR2_13,
2485 GP_2_12_FN, GPSR2_12,
2486 GP_2_11_FN, GPSR2_11,
2487 GP_2_10_FN, GPSR2_10,
2488 GP_2_9_FN, GPSR2_9,
2489 GP_2_8_FN, GPSR2_8,
2490 GP_2_7_FN, GPSR2_7,
2491 GP_2_6_FN, GPSR2_6,
2492 GP_2_5_FN, GPSR2_5,
2493 GP_2_4_FN, GPSR2_4,
2494 GP_2_3_FN, GPSR2_3,
2495 GP_2_2_FN, GPSR2_2,
2496 GP_2_1_FN, GPSR2_1,
2497 GP_2_0_FN, GPSR2_0, ))
2498 },
2499 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2500 0, 0,
2501 0, 0,
2502 0, 0,
2503 0, 0,
2504 0, 0,
2505 0, 0,
2506 0, 0,
2507 0, 0,
2508 0, 0,
2509 0, 0,
2510 0, 0,
2511 0, 0,
2512 0, 0,
2513 0, 0,
2514 0, 0,
2515 0, 0,
2516 0, 0,
2517 0, 0,
2518 0, 0,
2519 0, 0,
2520 0, 0,
2521 0, 0,
2522 GP_3_9_FN, GPSR3_9,
2523 GP_3_8_FN, GPSR3_8,
2524 GP_3_7_FN, GPSR3_7,
2525 GP_3_6_FN, GPSR3_6,
2526 GP_3_5_FN, GPSR3_5,
2527 GP_3_4_FN, GPSR3_4,
2528 GP_3_3_FN, GPSR3_3,
2529 GP_3_2_FN, GPSR3_2,
2530 GP_3_1_FN, GPSR3_1,
2531 GP_3_0_FN, GPSR3_0, ))
2532 },
2533 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2534 GP_4_31_FN, GPSR4_31,
2535 GP_4_30_FN, GPSR4_30,
2536 GP_4_29_FN, GPSR4_29,
2537 GP_4_28_FN, GPSR4_28,
2538 GP_4_27_FN, GPSR4_27,
2539 GP_4_26_FN, GPSR4_26,
2540 GP_4_25_FN, GPSR4_25,
2541 GP_4_24_FN, GPSR4_24,
2542 GP_4_23_FN, GPSR4_23,
2543 GP_4_22_FN, GPSR4_22,
2544 GP_4_21_FN, GPSR4_21,
2545 GP_4_20_FN, GPSR4_20,
2546 GP_4_19_FN, GPSR4_19,
2547 GP_4_18_FN, GPSR4_18,
2548 GP_4_17_FN, GPSR4_17,
2549 GP_4_16_FN, GPSR4_16,
2550 GP_4_15_FN, GPSR4_15,
2551 GP_4_14_FN, GPSR4_14,
2552 GP_4_13_FN, GPSR4_13,
2553 GP_4_12_FN, GPSR4_12,
2554 GP_4_11_FN, GPSR4_11,
2555 GP_4_10_FN, GPSR4_10,
2556 GP_4_9_FN, GPSR4_9,
2557 GP_4_8_FN, GPSR4_8,
2558 GP_4_7_FN, GPSR4_7,
2559 GP_4_6_FN, GPSR4_6,
2560 GP_4_5_FN, GPSR4_5,
2561 GP_4_4_FN, GPSR4_4,
2562 GP_4_3_FN, GPSR4_3,
2563 GP_4_2_FN, GPSR4_2,
2564 GP_4_1_FN, GPSR4_1,
2565 GP_4_0_FN, GPSR4_0, ))
2566 },
2567 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2568 0, 0,
2569 0, 0,
2570 0, 0,
2571 0, 0,
2572 0, 0,
2573 0, 0,
2574 0, 0,
2575 0, 0,
2576 0, 0,
2577 0, 0,
2578 0, 0,
2579 GP_5_20_FN, GPSR5_20,
2580 GP_5_19_FN, GPSR5_19,
2581 GP_5_18_FN, GPSR5_18,
2582 GP_5_17_FN, GPSR5_17,
2583 GP_5_16_FN, GPSR5_16,
2584 GP_5_15_FN, GPSR5_15,
2585 GP_5_14_FN, GPSR5_14,
2586 GP_5_13_FN, GPSR5_13,
2587 GP_5_12_FN, GPSR5_12,
2588 GP_5_11_FN, GPSR5_11,
2589 GP_5_10_FN, GPSR5_10,
2590 GP_5_9_FN, GPSR5_9,
2591 GP_5_8_FN, GPSR5_8,
2592 GP_5_7_FN, GPSR5_7,
2593 GP_5_6_FN, GPSR5_6,
2594 GP_5_5_FN, GPSR5_5,
2595 GP_5_4_FN, GPSR5_4,
2596 GP_5_3_FN, GPSR5_3,
2597 GP_5_2_FN, GPSR5_2,
2598 GP_5_1_FN, GPSR5_1,
2599 GP_5_0_FN, GPSR5_0, ))
2600 },
2601 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
2602 0, 0,
2603 0, 0,
2604 0, 0,
2605 0, 0,
2606 0, 0,
2607 0, 0,
2608 0, 0,
2609 0, 0,
2610 0, 0,
2611 0, 0,
2612 0, 0,
2613 0, 0,
2614 0, 0,
2615 0, 0,
2616 0, 0,
2617 0, 0,
2618 0, 0,
2619 0, 0,
2620 GP_6_13_FN, GPSR6_13,
2621 GP_6_12_FN, GPSR6_12,
2622 GP_6_11_FN, GPSR6_11,
2623 GP_6_10_FN, GPSR6_10,
2624 GP_6_9_FN, GPSR6_9,
2625 GP_6_8_FN, GPSR6_8,
2626 GP_6_7_FN, GPSR6_7,
2627 GP_6_6_FN, GPSR6_6,
2628 GP_6_5_FN, GPSR6_5,
2629 GP_6_4_FN, GPSR6_4,
2630 GP_6_3_FN, GPSR6_3,
2631 GP_6_2_FN, GPSR6_2,
2632 GP_6_1_FN, GPSR6_1,
2633 GP_6_0_FN, GPSR6_0, ))
2634 },
2635#undef F_
2636#undef FM
2637
2638#define F_(x, y) x,
2639#define FM(x) FN_##x,
2640 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2641 IP0_31_28
2642 IP0_27_24
2643 IP0_23_20
2644 IP0_19_16
2645 IP0_15_12
2646 IP0_11_8
2647 IP0_7_4
2648 IP0_3_0 ))
2649 },
2650 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2651 IP1_31_28
2652 IP1_27_24
2653 IP1_23_20
2654 IP1_19_16
2655 IP1_15_12
2656 IP1_11_8
2657 IP1_7_4
2658 IP1_3_0 ))
2659 },
2660 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2661 IP2_31_28
2662 IP2_27_24
2663 IP2_23_20
2664 IP2_19_16
2665 IP2_15_12
2666 IP2_11_8
2667 IP2_7_4
2668 IP2_3_0 ))
2669 },
2670 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2671 IP3_31_28
2672 IP3_27_24
2673 IP3_23_20
2674 IP3_19_16
2675 IP3_15_12
2676 IP3_11_8
2677 IP3_7_4
2678 IP3_3_0 ))
2679 },
2680 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2681 IP4_31_28
2682 IP4_27_24
2683 IP4_23_20
2684 IP4_19_16
2685 IP4_15_12
2686 IP4_11_8
2687 IP4_7_4
2688 IP4_3_0 ))
2689 },
2690 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2691 IP5_31_28
2692 IP5_27_24
2693 IP5_23_20
2694 IP5_19_16
2695 IP5_15_12
2696 IP5_11_8
2697 IP5_7_4
2698 IP5_3_0 ))
2699 },
2700 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2701 IP6_31_28
2702 IP6_27_24
2703 IP6_23_20
2704 IP6_19_16
2705 IP6_15_12
2706 IP6_11_8
2707 IP6_7_4
2708 IP6_3_0 ))
2709 },
2710 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2711 IP7_31_28
2712 IP7_27_24
2713 IP7_23_20
2714 IP7_19_16
2715 IP7_15_12
2716 IP7_11_8
2717 IP7_7_4
2718 IP7_3_0 ))
2719 },
2720 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2721 IP8_31_28
2722 IP8_27_24
2723 IP8_23_20
2724 IP8_19_16
2725 IP8_15_12
2726 IP8_11_8
2727 IP8_7_4
2728 IP8_3_0 ))
2729 },
2730 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2731 IP9_31_28
2732 IP9_27_24
2733 IP9_23_20
2734 IP9_19_16
2735 IP9_15_12
2736 IP9_11_8
2737 IP9_7_4
2738 IP9_3_0 ))
2739 },
2740 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
2741 IP10_31_28
2742 IP10_27_24
2743 IP10_23_20
2744 IP10_19_16
2745 IP10_15_12
2746 IP10_11_8
2747 IP10_7_4
2748 IP10_3_0 ))
2749 },
2750 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
2751 IP11_31_28
2752 IP11_27_24
2753 IP11_23_20
2754 IP11_19_16
2755 IP11_15_12
2756 IP11_11_8
2757 IP11_7_4
2758 IP11_3_0 ))
2759 },
2760 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
2761 IP12_31_28
2762 IP12_27_24
2763 IP12_23_20
2764 IP12_19_16
2765 IP12_15_12
2766 IP12_11_8
2767 IP12_7_4
2768 IP12_3_0 ))
2769 },
2770 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
2771 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2772 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2773 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2774 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2775 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2776 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2777 IP13_7_4
2778 IP13_3_0 ))
2779 },
2780#undef F_
2781#undef FM
2782
2783#define F_(x, y) x,
2784#define FM(x) FN_##x,
2785 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2786 GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
2787 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1),
2788 GROUP(
2789
2790 0, 0,
2791 MOD_SEL0_30
2792 MOD_SEL0_29
2793 MOD_SEL0_28
2794 MOD_SEL0_27
2795 MOD_SEL0_26
2796 MOD_SEL0_25
2797 MOD_SEL0_24_23
2798 MOD_SEL0_22_21
2799 MOD_SEL0_20_19
2800 MOD_SEL0_18_17
2801
2802 0, 0,
2803 MOD_SEL0_15
2804 MOD_SEL0_14
2805 MOD_SEL0_13
2806 MOD_SEL0_12
2807 MOD_SEL0_11
2808 MOD_SEL0_10
2809
2810 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2811 MOD_SEL0_5
2812 MOD_SEL0_4
2813 MOD_SEL0_3
2814 MOD_SEL0_2
2815 MOD_SEL0_1
2816 MOD_SEL0_0 ))
2817 },
2818 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2819 GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4),
2820 GROUP(
2821 MOD_SEL1_31
2822 MOD_SEL1_30
2823 MOD_SEL1_29
2824 MOD_SEL1_28
2825 MOD_SEL1_27
2826 MOD_SEL1_26
2827
2828 0, 0, 0, 0,
2829
2830 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2831
2832 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2833
2834 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2835
2836 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2837
2838 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2839
2840 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
2841 },
2842 { },
2843};
2844
2845static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
2846{
2847 int bit = -EINVAL;
2848
2849 *pocctrl = 0xe6060380;
2850
2851 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
2852 bit = 29 - (pin - RCAR_GP_PIN(3, 0));
2853
2854 return bit;
2855}
2856
2857static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2858 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2859 [ 0] = RCAR_GP_PIN(1, 9),
2860 [ 1] = RCAR_GP_PIN(1, 8),
2861 [ 2] = RCAR_GP_PIN(1, 7),
2862 [ 3] = RCAR_GP_PIN(1, 6),
2863 [ 4] = RCAR_GP_PIN(1, 5),
2864 [ 5] = RCAR_GP_PIN(1, 4),
2865 [ 6] = RCAR_GP_PIN(1, 3),
2866 [ 7] = RCAR_GP_PIN(1, 2),
2867 [ 8] = RCAR_GP_PIN(1, 1),
2868 [ 9] = RCAR_GP_PIN(1, 0),
2869 [10] = PIN_MLB_REF,
2870 [11] = RCAR_GP_PIN(0, 8),
2871 [12] = RCAR_GP_PIN(0, 7),
2872 [13] = RCAR_GP_PIN(0, 6),
2873 [14] = RCAR_GP_PIN(0, 5),
2874 [15] = RCAR_GP_PIN(0, 4),
2875 [16] = RCAR_GP_PIN(0, 3),
2876 [17] = RCAR_GP_PIN(0, 2),
2877 [18] = RCAR_GP_PIN(0, 1),
2878 [19] = RCAR_GP_PIN(0, 0),
2879 [20] = PIN_PRESETOUT_N,
2880 [21] = PIN_DU_DOTCLKIN0,
2881 [22] = PIN_FSCLKST_N,
2882 [23] = SH_PFC_PIN_NONE,
2883 [24] = SH_PFC_PIN_NONE,
2884 [25] = SH_PFC_PIN_NONE,
2885 [26] = SH_PFC_PIN_NONE,
2886 [27] = SH_PFC_PIN_NONE,
2887 [28] = PIN_TDI,
2888 [29] = PIN_TMS,
2889 [30] = PIN_TCK,
2890 [31] = PIN_TRST_N,
2891 } },
2892 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2893 [ 0] = RCAR_GP_PIN(2, 9),
2894 [ 1] = RCAR_GP_PIN(2, 8),
2895 [ 2] = RCAR_GP_PIN(2, 7),
2896 [ 3] = RCAR_GP_PIN(2, 6),
2897 [ 4] = RCAR_GP_PIN(2, 5),
2898 [ 5] = RCAR_GP_PIN(2, 4),
2899 [ 6] = RCAR_GP_PIN(2, 3),
2900 [ 7] = RCAR_GP_PIN(2, 2),
2901 [ 8] = RCAR_GP_PIN(2, 1),
2902 [ 9] = RCAR_GP_PIN(2, 0),
2903 [10] = RCAR_GP_PIN(1, 31),
2904 [11] = RCAR_GP_PIN(1, 30),
2905 [12] = RCAR_GP_PIN(1, 29),
2906 [13] = RCAR_GP_PIN(1, 28),
2907 [14] = RCAR_GP_PIN(1, 27),
2908 [15] = RCAR_GP_PIN(1, 26),
2909 [16] = RCAR_GP_PIN(1, 25),
2910 [17] = RCAR_GP_PIN(1, 24),
2911 [18] = RCAR_GP_PIN(1, 23),
2912 [19] = RCAR_GP_PIN(1, 22),
2913 [20] = RCAR_GP_PIN(1, 21),
2914 [21] = RCAR_GP_PIN(1, 20),
2915 [22] = RCAR_GP_PIN(1, 19),
2916 [23] = RCAR_GP_PIN(1, 18),
2917 [24] = RCAR_GP_PIN(1, 17),
2918 [25] = RCAR_GP_PIN(1, 16),
2919 [26] = RCAR_GP_PIN(1, 15),
2920 [27] = RCAR_GP_PIN(1, 14),
2921 [28] = RCAR_GP_PIN(1, 13),
2922 [29] = RCAR_GP_PIN(1, 12),
2923 [30] = RCAR_GP_PIN(1, 11),
2924 [31] = RCAR_GP_PIN(1, 10),
2925 } },
2926 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2927 [ 0] = RCAR_GP_PIN(3, 8),
2928 [ 1] = RCAR_GP_PIN(3, 7),
2929 [ 2] = RCAR_GP_PIN(3, 6),
2930 [ 3] = RCAR_GP_PIN(3, 5),
2931 [ 4] = RCAR_GP_PIN(3, 4),
2932 [ 5] = RCAR_GP_PIN(3, 3),
2933 [ 6] = RCAR_GP_PIN(3, 2),
2934 [ 7] = RCAR_GP_PIN(3, 1),
2935 [ 8] = RCAR_GP_PIN(3, 0),
2936 [ 9] = RCAR_GP_PIN(4, 0),
2937 [10] = RCAR_GP_PIN(2, 31),
2938 [11] = RCAR_GP_PIN(2, 30),
2939 [12] = RCAR_GP_PIN(2, 29),
2940 [13] = RCAR_GP_PIN(2, 28),
2941 [14] = RCAR_GP_PIN(2, 27),
2942 [15] = RCAR_GP_PIN(2, 26),
2943 [16] = RCAR_GP_PIN(2, 25),
2944 [17] = RCAR_GP_PIN(2, 24),
2945 [18] = RCAR_GP_PIN(2, 23),
2946 [19] = RCAR_GP_PIN(2, 22),
2947 [20] = RCAR_GP_PIN(2, 21),
2948 [21] = RCAR_GP_PIN(2, 20),
2949 [22] = RCAR_GP_PIN(2, 19),
2950 [23] = RCAR_GP_PIN(2, 18),
2951 [24] = RCAR_GP_PIN(2, 17),
2952 [25] = RCAR_GP_PIN(2, 16),
2953 [26] = RCAR_GP_PIN(2, 15),
2954 [27] = RCAR_GP_PIN(2, 14),
2955 [28] = RCAR_GP_PIN(2, 13),
2956 [29] = RCAR_GP_PIN(2, 12),
2957 [30] = RCAR_GP_PIN(2, 11),
2958 [31] = RCAR_GP_PIN(2, 10),
2959 } },
2960 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2961 [ 0] = RCAR_GP_PIN(4, 31),
2962 [ 1] = RCAR_GP_PIN(5, 2),
2963 [ 2] = RCAR_GP_PIN(5, 1),
2964 [ 3] = RCAR_GP_PIN(5, 0),
2965 [ 4] = RCAR_GP_PIN(4, 27),
2966 [ 5] = RCAR_GP_PIN(4, 26),
2967 [ 6] = RCAR_GP_PIN(4, 25),
2968 [ 7] = RCAR_GP_PIN(4, 24),
2969 [ 8] = RCAR_GP_PIN(4, 23),
2970 [ 9] = RCAR_GP_PIN(4, 22),
2971 [10] = RCAR_GP_PIN(4, 21),
2972 [11] = RCAR_GP_PIN(4, 20),
2973 [12] = RCAR_GP_PIN(4, 19),
2974 [13] = RCAR_GP_PIN(4, 18),
2975 [14] = RCAR_GP_PIN(4, 17),
2976 [15] = RCAR_GP_PIN(4, 16),
2977 [16] = RCAR_GP_PIN(4, 15),
2978 [17] = RCAR_GP_PIN(4, 14),
2979 [18] = RCAR_GP_PIN(4, 13),
2980 [19] = RCAR_GP_PIN(4, 12),
2981 [20] = RCAR_GP_PIN(4, 11),
2982 [21] = RCAR_GP_PIN(4, 10),
2983 [22] = RCAR_GP_PIN(4, 9),
2984 [23] = RCAR_GP_PIN(4, 8),
2985 [24] = RCAR_GP_PIN(4, 7),
2986 [25] = RCAR_GP_PIN(4, 6),
2987 [26] = RCAR_GP_PIN(4, 5),
2988 [27] = RCAR_GP_PIN(4, 4),
2989 [28] = RCAR_GP_PIN(4, 3),
2990 [29] = RCAR_GP_PIN(4, 2),
2991 [30] = RCAR_GP_PIN(4, 1),
2992 [31] = RCAR_GP_PIN(3, 9),
2993 } },
2994 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
2995 [ 0] = RCAR_GP_PIN(6, 10),
2996 [ 1] = RCAR_GP_PIN(6, 9),
2997 [ 2] = RCAR_GP_PIN(6, 8),
2998 [ 3] = RCAR_GP_PIN(6, 7),
2999 [ 4] = RCAR_GP_PIN(6, 6),
3000 [ 5] = RCAR_GP_PIN(6, 5),
3001 [ 6] = RCAR_GP_PIN(6, 4),
3002 [ 7] = RCAR_GP_PIN(6, 3),
3003 [ 8] = RCAR_GP_PIN(6, 2),
3004 [ 9] = RCAR_GP_PIN(6, 1),
3005 [10] = RCAR_GP_PIN(6, 0),
3006 [11] = RCAR_GP_PIN(5, 20),
3007 [12] = RCAR_GP_PIN(5, 19),
3008 [13] = RCAR_GP_PIN(5, 18),
3009 [14] = RCAR_GP_PIN(5, 17),
3010 [15] = RCAR_GP_PIN(5, 16),
3011 [16] = RCAR_GP_PIN(5, 15),
3012 [17] = RCAR_GP_PIN(5, 14),
3013 [18] = RCAR_GP_PIN(5, 13),
3014 [19] = RCAR_GP_PIN(5, 12),
3015 [20] = RCAR_GP_PIN(5, 11),
3016 [21] = RCAR_GP_PIN(5, 10),
3017 [22] = RCAR_GP_PIN(5, 9),
3018 [23] = RCAR_GP_PIN(5, 8),
3019 [24] = RCAR_GP_PIN(5, 7),
3020 [25] = RCAR_GP_PIN(5, 6),
3021 [26] = RCAR_GP_PIN(5, 5),
3022 [27] = RCAR_GP_PIN(5, 4),
3023 [28] = RCAR_GP_PIN(5, 3),
3024 [29] = RCAR_GP_PIN(4, 30),
3025 [30] = RCAR_GP_PIN(4, 29),
3026 [31] = RCAR_GP_PIN(4, 28),
3027 } },
3028 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD4", 0xe6060454) {
3029 [ 0] = SH_PFC_PIN_NONE,
3030 [ 1] = SH_PFC_PIN_NONE,
3031 [ 2] = SH_PFC_PIN_NONE,
3032 [ 3] = SH_PFC_PIN_NONE,
3033 [ 4] = SH_PFC_PIN_NONE,
3034 [ 5] = SH_PFC_PIN_NONE,
3035 [ 6] = SH_PFC_PIN_NONE,
3036 [ 7] = SH_PFC_PIN_NONE,
3037 [ 8] = SH_PFC_PIN_NONE,
3038 [ 9] = SH_PFC_PIN_NONE,
3039 [10] = SH_PFC_PIN_NONE,
3040 [11] = SH_PFC_PIN_NONE,
3041 [12] = SH_PFC_PIN_NONE,
3042 [13] = SH_PFC_PIN_NONE,
3043 [14] = SH_PFC_PIN_NONE,
3044 [15] = SH_PFC_PIN_NONE,
3045 [16] = SH_PFC_PIN_NONE,
3046 [17] = SH_PFC_PIN_NONE,
3047 [18] = SH_PFC_PIN_NONE,
3048 [19] = SH_PFC_PIN_NONE,
3049 [20] = SH_PFC_PIN_NONE,
3050 [21] = SH_PFC_PIN_NONE,
3051 [22] = SH_PFC_PIN_NONE,
3052 [23] = SH_PFC_PIN_NONE,
3053 [24] = SH_PFC_PIN_NONE,
3054 [25] = SH_PFC_PIN_NONE,
3055 [26] = SH_PFC_PIN_NONE,
3056 [27] = SH_PFC_PIN_NONE,
3057 [28] = SH_PFC_PIN_NONE,
3058 [29] = RCAR_GP_PIN(6, 13),
3059 [30] = RCAR_GP_PIN(6, 12),
3060 [31] = RCAR_GP_PIN(6, 11),
3061 } },
3062 { }
3063};
3064
3065enum ioctrl_regs {
3066 TDSELCTRL,
3067};
3068
3069static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
3070 [TDSELCTRL] = { 0xe60603c0, },
3071 { },
3072};
3073
3074static const struct pinmux_bias_reg *
3075r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
3076 unsigned int *puen_bit, unsigned int *pud_bit)
3077{
3078 const struct pinmux_bias_reg *reg;
3079 unsigned int bit;
3080
3081 reg = rcar_pin_to_bias_reg(pfc, pin, &bit);
3082 if (!reg)
3083 return reg;
3084
3085 *puen_bit = bit;
3086
3087
3088 switch (pin) {
3089 case RCAR_GP_PIN(3, 0):
3090 *pud_bit = 7;
3091 break;
3092
3093 case RCAR_GP_PIN(3, 1):
3094 *pud_bit = 8;
3095 break;
3096
3097 default:
3098 *pud_bit = bit;
3099 break;
3100 }
3101
3102 return reg;
3103}
3104
3105static unsigned int r8a77995_pinmux_get_bias(struct sh_pfc *pfc,
3106 unsigned int pin)
3107{
3108 const struct pinmux_bias_reg *reg;
3109 unsigned int puen_bit, pud_bit;
3110
3111 reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
3112 if (!reg)
3113 return PIN_CONFIG_BIAS_DISABLE;
3114
3115 if (!(sh_pfc_read(pfc, reg->puen) & BIT(puen_bit)))
3116 return PIN_CONFIG_BIAS_DISABLE;
3117 else if (sh_pfc_read(pfc, reg->pud) & BIT(pud_bit))
3118 return PIN_CONFIG_BIAS_PULL_UP;
3119 else
3120 return PIN_CONFIG_BIAS_PULL_DOWN;
3121}
3122
3123static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3124 unsigned int bias)
3125{
3126 const struct pinmux_bias_reg *reg;
3127 unsigned int puen_bit, pud_bit;
3128 u32 enable, updown;
3129
3130 reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
3131 if (!reg)
3132 return;
3133
3134 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(puen_bit);
3135 if (bias != PIN_CONFIG_BIAS_DISABLE) {
3136 enable |= BIT(puen_bit);
3137
3138 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(pud_bit);
3139 if (bias == PIN_CONFIG_BIAS_PULL_UP)
3140 updown |= BIT(pud_bit);
3141
3142 sh_pfc_write(pfc, reg->pud, updown);
3143 }
3144 sh_pfc_write(pfc, reg->puen, enable);
3145}
3146
3147static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
3148 .pin_to_pocctrl = r8a77995_pin_to_pocctrl,
3149 .get_bias = r8a77995_pinmux_get_bias,
3150 .set_bias = r8a77995_pinmux_set_bias,
3151};
3152
3153const struct sh_pfc_soc_info r8a77995_pinmux_info = {
3154 .name = "r8a77995_pfc",
3155 .ops = &r8a77995_pinmux_ops,
3156 .unlock_reg = 0xe6060000,
3157
3158 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3159
3160 .pins = pinmux_pins,
3161 .nr_pins = ARRAY_SIZE(pinmux_pins),
3162 .groups = pinmux_groups,
3163 .nr_groups = ARRAY_SIZE(pinmux_groups),
3164 .functions = pinmux_functions,
3165 .nr_functions = ARRAY_SIZE(pinmux_functions),
3166
3167 .cfg_regs = pinmux_config_regs,
3168 .bias_regs = pinmux_bias_regs,
3169 .ioctrl_regs = pinmux_ioctrl_regs,
3170
3171 .pinmux_data = pinmux_data,
3172 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3173};
3174
