LXR linux/drivers/rtc/rtc-stmp3xxx.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Freescale STMP37XX/STMP378X Real Time Clock driver
   4 *
   5 * Copyright (c) 2007 Sigmatel, Inc.
   6 * Peter Hartley, <peter.hartley@sigmatel.com>
   7 *
   8 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
   9 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
  10 * Copyright 2011 Wolfram Sang, Pengutronix e.K.
  11 */
  12#include <linux/kernel.h>
  13#include <linux/module.h>
  14#include <linux/io.h>
  15#include <linux/init.h>
  16#include <linux/platform_device.h>
  17#include <linux/interrupt.h>
  18#include <linux/delay.h>
  19#include <linux/rtc.h>
  20#include <linux/slab.h>
  21#include <linux/of_device.h>
  22#include <linux/of.h>
  23#include <linux/stmp_device.h>
  24#include <linux/stmp3xxx_rtc_wdt.h>
  25
  26#define STMP3XXX_RTC_CTRL                       0x0
  27#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN          0x00000001
  28#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN        0x00000002
  29#define STMP3XXX_RTC_CTRL_ALARM_IRQ             0x00000004
  30#define STMP3XXX_RTC_CTRL_WATCHDOGEN            0x00000010
  31
  32#define STMP3XXX_RTC_STAT                       0x10
  33#define STMP3XXX_RTC_STAT_STALE_SHIFT           16
  34#define STMP3XXX_RTC_STAT_RTC_PRESENT           0x80000000
  35#define STMP3XXX_RTC_STAT_XTAL32000_PRESENT     0x10000000
  36#define STMP3XXX_RTC_STAT_XTAL32768_PRESENT     0x08000000
  37
  38#define STMP3XXX_RTC_SECONDS                    0x30
  39
  40#define STMP3XXX_RTC_ALARM                      0x40
  41
  42#define STMP3XXX_RTC_WATCHDOG                   0x50
  43
  44#define STMP3XXX_RTC_PERSISTENT0                0x60
  45#define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE            (1 << 0)
  46#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN          (1 << 1)
  47#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN               (1 << 2)
  48#define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP        (1 << 4)
  49#define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP        (1 << 5)
  50#define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ            (1 << 6)
  51#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE             (1 << 7)
  52
  53#define STMP3XXX_RTC_PERSISTENT1                0x70
  54/* missing bitmask in headers */
  55#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER  0x80000000
  56
  57struct stmp3xxx_rtc_data {
  58        struct rtc_device *rtc;
  59        void __iomem *io;
  60        int irq_alarm;
  61};
  62
  63#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
  64/**
  65 * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
  66 * @dev: the parent device of the watchdog (= the RTC)
  67 * @timeout: the desired value for the timeout register of the watchdog.
  68 *           0 disables the watchdog
  69 *
  70 * The watchdog needs one register and two bits which are in the RTC domain.
  71 * To handle the resource conflict, the RTC driver will create another
  72 * platform_device for the watchdog driver as a child of the RTC device.
  73 * The watchdog driver is passed the below accessor function via platform_data
  74 * to configure the watchdog. Locking is not needed because accessing SET/CLR
  75 * registers is atomic.
  76 */
  77
  78static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
  79{
  80        struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
  81
  82        if (timeout) {
  83                writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
  84                writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
  85                       rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
  86                writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
  87                       rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
  88        } else {
  89                writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
  90                       rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
  91                writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
  92                       rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
  93        }
  94}
  95
  96static struct stmp3xxx_wdt_pdata wdt_pdata = {
  97        .wdt_set_timeout = stmp3xxx_wdt_set_timeout,
  98};
  99
 100static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
 101{
 102        int rc = -1;
 103        struct platform_device *wdt_pdev =
 104                platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
 105
 106        if (wdt_pdev) {
 107                wdt_pdev->dev.parent = &rtc_pdev->dev;
 108                wdt_pdev->dev.platform_data = &wdt_pdata;
 109                rc = platform_device_add(wdt_pdev);
 110        }
 111
 112        if (rc)
 113                dev_err(&rtc_pdev->dev,
 114                        "failed to register stmp3xxx_rtc_wdt\n");
 115}
 116#else
 117static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
 118{
 119}
 120#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
 121
 122static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
 123{
 124        int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
 125        /*
 126         * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
 127         * states:
 128         * | The order in which registers are updated is
 129         * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
 130         * | (This list is in bitfield order, from LSB to MSB, as they would
 131         * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
 132         * | register. For example, the Seconds register corresponds to
 133         * | STALE_REGS or NEW_REGS containing 0x80.)
 134         */
 135        do {
 136                if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
 137                                (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
 138                        return 0;
 139                udelay(1);
 140        } while (--timeout > 0);
 141        return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
 142                (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
 143}
 144
 145/* Time read/write */
 146static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
 147{
 148        int ret;
 149        struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 150
 151        ret = stmp3xxx_wait_time(rtc_data);
 152        if (ret)
 153                return ret;
 154
 155        rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
 156        return 0;
 157}
 158
 159static int stmp3xxx_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
 160{
 161        struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 162
 163        writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS);
 164        return stmp3xxx_wait_time(rtc_data);
 165}
 166
 167/* interrupt(s) handler */
 168static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
 169{
 170        struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
 171        u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
 172
 173        if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
 174                writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
 175                        rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
 176                rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
 177                return IRQ_HANDLED;
 178        }
 179
 180        return IRQ_NONE;
 181}
 182
 183static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
 184{
 185        struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 186
 187        if (enabled) {
 188                writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
 189                                STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
 190                        rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
 191                                STMP_OFFSET_REG_SET);
 192                writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
 193                        rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
 194        } else {
 195                writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
 196                                STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
 197                        rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
 198                                STMP_OFFSET_REG_CLR);
 199                writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
 200                        rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
 201        }
 202        return 0;
 203}
 204
 205static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
 206{
 207        struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 208
 209        rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
 210        return 0;
 211}
 212
 213static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
 214{
 215        struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 216
 217        writel(rtc_tm_to_time64(&alm->time), rtc_data->io + STMP3XXX_RTC_ALARM);
 218
 219        stmp3xxx_alarm_irq_enable(dev, alm->enabled);
 220
 221        return 0;
 222}
 223
 224static const struct rtc_class_ops stmp3xxx_rtc_ops = {
 225        .alarm_irq_enable =
 226                          stmp3xxx_alarm_irq_enable,
 227        .read_time      = stmp3xxx_rtc_gettime,
 228        .set_time       = stmp3xxx_rtc_settime,
 229        .read_alarm     = stmp3xxx_rtc_read_alarm,
 230        .set_alarm      = stmp3xxx_rtc_set_alarm,
 231};
 232
 233static int stmp3xxx_rtc_remove(struct platform_device *pdev)
 234{
 235        struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
 236
 237        if (!rtc_data)
 238                return 0;
 239
 240        writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
 241                rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
 242
 243        return 0;
 244}
 245
 246static int stmp3xxx_rtc_probe(struct platform_device *pdev)
 247{
 248        struct stmp3xxx_rtc_data *rtc_data;
 249        struct resource *r;
 250        u32 rtc_stat;
 251        u32 pers0_set, pers0_clr;
 252        u32 crystalfreq = 0;
 253        int err;
 254
 255        rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
 256        if (!rtc_data)
 257                return -ENOMEM;
 258
 259        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 260        if (!r) {
 261                dev_err(&pdev->dev, "failed to get resource\n");
 262                return -ENXIO;
 263        }
 264
 265        rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 266        if (!rtc_data->io) {
 267                dev_err(&pdev->dev, "ioremap failed\n");
 268                return -EIO;
 269        }
 270
 271        rtc_data->irq_alarm = platform_get_irq(pdev, 0);
 272
 273        rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
 274        if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
 275                dev_err(&pdev->dev, "no device onboard\n");
 276                return -ENODEV;
 277        }
 278
 279        platform_set_drvdata(pdev, rtc_data);
 280
 281        /*
 282         * Resetting the rtc stops the watchdog timer that is potentially
 283         * running. So (assuming it is running on purpose) don't reset if the
 284         * watchdog is enabled.
 285         */
 286        if (readl(rtc_data->io + STMP3XXX_RTC_CTRL) &
 287            STMP3XXX_RTC_CTRL_WATCHDOGEN) {
 288                dev_info(&pdev->dev,
 289                         "Watchdog is running, skip resetting rtc\n");
 290        } else {
 291                err = stmp_reset_block(rtc_data->io);
 292                if (err) {
 293                        dev_err(&pdev->dev, "stmp_reset_block failed: %d\n",
 294                                err);
 295                        return err;
 296                }
 297        }
 298
 299        /*
 300         * Obviously the rtc needs a clock input to be able to run.
 301         * This clock can be provided by an external 32k crystal. If that one is
 302         * missing XTAL must not be disabled in suspend which consumes a
 303         * lot of power. Normally the presence and exact frequency (supported
 304         * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
 305         * proves these fuses are not blown correctly on all machines, so the
 306         * frequency can be overridden in the device tree.
 307         */
 308        if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
 309                crystalfreq = 32000;
 310        else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
 311                crystalfreq = 32768;
 312
 313        of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
 314                             &crystalfreq);
 315
 316        switch (crystalfreq) {
 317        case 32000:
 318                /* keep 32kHz crystal running in low-power mode */
 319                pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ |
 320                        STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
 321                        STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
 322                pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
 323                break;
 324        case 32768:
 325                /* keep 32.768kHz crystal running in low-power mode */
 326                pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
 327                        STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
 328                pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
 329                        STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
 330                break;
 331        default:
 332                dev_warn(&pdev->dev,
 333                         "invalid crystal-freq specified in device-tree. Assuming no crystal\n");
 334                fallthrough;
 335        case 0:
 336                /* keep XTAL on in low-power mode */
 337                pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
 338                pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
 339                        STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
 340        }
 341
 342        writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
 343                        STMP_OFFSET_REG_SET);
 344
 345        writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
 346                        STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
 347                        STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
 348                rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
 349
 350        writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
 351                        STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
 352                rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
 353
 354        rtc_data->rtc = devm_rtc_allocate_device(&pdev->dev);
 355        if (IS_ERR(rtc_data->rtc))
 356                return PTR_ERR(rtc_data->rtc);
 357
 358        err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
 359                        stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
 360        if (err) {
 361                dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
 362                        rtc_data->irq_alarm);
 363                return err;
 364        }
 365
 366        rtc_data->rtc->ops = &stmp3xxx_rtc_ops;
 367        rtc_data->rtc->range_max = U32_MAX;
 368
 369        err = devm_rtc_register_device(rtc_data->rtc);
 370        if (err)
 371                return err;
 372
 373        stmp3xxx_wdt_register(pdev);
 374        return 0;
 375}
 376
 377#ifdef CONFIG_PM_SLEEP
 378static int stmp3xxx_rtc_suspend(struct device *dev)
 379{
 380        return 0;
 381}
 382
 383static int stmp3xxx_rtc_resume(struct device *dev)
 384{
 385        struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 386
 387        stmp_reset_block(rtc_data->io);
 388        writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
 389                        STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
 390                        STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
 391                rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
 392        return 0;
 393}
 394#endif
 395
 396static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
 397                        stmp3xxx_rtc_resume);
 398
 399static const struct of_device_id rtc_dt_ids[] = {
 400        { .compatible = "fsl,stmp3xxx-rtc", },
 401        { /* sentinel */ }
 402};
 403MODULE_DEVICE_TABLE(of, rtc_dt_ids);
 404
 405static struct platform_driver stmp3xxx_rtcdrv = {
 406        .probe          = stmp3xxx_rtc_probe,
 407        .remove         = stmp3xxx_rtc_remove,
 408        .driver         = {
 409                .name   = "stmp3xxx-rtc",
 410                .pm     = &stmp3xxx_rtc_pm_ops,
 411                .of_match_table = rtc_dt_ids,
 412        },
 413};
 414
 415module_platform_driver(stmp3xxx_rtcdrv);
 416
 417MODULE_DESCRIPTION("STMP3xxx RTC Driver");
 418MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
 419                "Wolfram Sang <kernel@pengutronix.de>");
 420MODULE_LICENSE("GPL");
 421