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35#ifndef __CSIO_HW_H__
36#define __CSIO_HW_H__
37
38#include <linux/kernel.h>
39#include <linux/pci.h>
40#include <linux/device.h>
41#include <linux/workqueue.h>
42#include <linux/compiler.h>
43#include <linux/cdev.h>
44#include <linux/list.h>
45#include <linux/mempool.h>
46#include <linux/io.h>
47#include <linux/spinlock_types.h>
48#include <scsi/scsi_device.h>
49#include <scsi/scsi_transport_fc.h>
50
51#include "t4_hw.h"
52#include "csio_hw_chip.h"
53#include "csio_wr.h"
54#include "csio_mb.h"
55#include "csio_scsi.h"
56#include "csio_defs.h"
57#include "t4_regs.h"
58#include "t4_msg.h"
59
60
61
62
63#define FW_HOSTERROR 255
64
65#define CSIO_HW_NAME "Chelsio FCoE Adapter"
66#define CSIO_MAX_PFN 8
67#define CSIO_MAX_PPORTS 4
68
69#define CSIO_MAX_LUN 0xFFFF
70#define CSIO_MAX_QUEUE 2048
71#define CSIO_MAX_CMD_PER_LUN 32
72#define CSIO_MAX_DDP_BUF_SIZE (1024 * 1024)
73#define CSIO_MAX_SECTOR_SIZE 128
74#define CSIO_MIN_T6_FW 0x01102D00
75
76
77#define CSIO_EXTRA_MSI_IQS 2
78
79#define CSIO_EXTRA_VECS 2
80#define CSIO_MAX_SCSI_CPU 128
81#define CSIO_MAX_SCSI_QSETS (CSIO_MAX_SCSI_CPU * CSIO_MAX_PPORTS)
82#define CSIO_MAX_MSIX_VECS (CSIO_MAX_SCSI_QSETS + CSIO_EXTRA_VECS)
83
84
85enum {
86 CSIO_INTR_WRSIZE = 128,
87 CSIO_INTR_IQSIZE = ((CSIO_MAX_MSIX_VECS + 1) * CSIO_INTR_WRSIZE),
88 CSIO_FWEVT_WRSIZE = 128,
89 CSIO_FWEVT_IQLEN = 128,
90 CSIO_FWEVT_FLBUFS = 64,
91 CSIO_FWEVT_IQSIZE = (CSIO_FWEVT_WRSIZE * CSIO_FWEVT_IQLEN),
92 CSIO_HW_NIQ = 1,
93 CSIO_HW_NFLQ = 1,
94 CSIO_HW_NEQ = 1,
95 CSIO_HW_NINTXQ = 1,
96};
97
98struct csio_msix_entries {
99 void *dev_id;
100 char desc[24];
101};
102
103struct csio_scsi_qset {
104 int iq_idx;
105 int eq_idx;
106 uint32_t intr_idx;
107};
108
109struct csio_scsi_cpu_info {
110 int16_t max_cpus;
111};
112
113extern int csio_dbg_level;
114extern unsigned int csio_port_mask;
115extern int csio_msi;
116
117#define CSIO_VENDOR_ID 0x1425
118#define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
119#define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
120
121#define CSIO_GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | \
122 EDC0_F | EDC1_F | LE_F | TP_F | MA_F | \
123 PM_TX_F | PM_RX_F | ULP_RX_F | \
124 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
125
126
127
128
129
130enum {
131
132 CSIO_SGE_DBFIFO_INT_THRESH = 10,
133
134 CSIO_SGE_RX_DMA_OFFSET = 2,
135
136 CSIO_SGE_FLBUF_SIZE1 = 65536,
137 CSIO_SGE_FLBUF_SIZE2 = 1536,
138 CSIO_SGE_FLBUF_SIZE3 = 9024,
139 CSIO_SGE_FLBUF_SIZE4 = 9216,
140 CSIO_SGE_FLBUF_SIZE5 = 2048,
141 CSIO_SGE_FLBUF_SIZE6 = 128,
142 CSIO_SGE_FLBUF_SIZE7 = 8192,
143 CSIO_SGE_FLBUF_SIZE8 = 16384,
144
145 CSIO_SGE_TIMER_VAL_0 = 5,
146 CSIO_SGE_TIMER_VAL_1 = 10,
147 CSIO_SGE_TIMER_VAL_2 = 20,
148 CSIO_SGE_TIMER_VAL_3 = 50,
149 CSIO_SGE_TIMER_VAL_4 = 100,
150 CSIO_SGE_TIMER_VAL_5 = 200,
151
152 CSIO_SGE_INT_CNT_VAL_0 = 1,
153 CSIO_SGE_INT_CNT_VAL_1 = 4,
154 CSIO_SGE_INT_CNT_VAL_2 = 8,
155 CSIO_SGE_INT_CNT_VAL_3 = 16,
156};
157
158
159enum csio_evt {
160 CSIO_EVT_FW = 0,
161 CSIO_EVT_MBX,
162 CSIO_EVT_SCN,
163 CSIO_EVT_DEV_LOSS,
164 CSIO_EVT_MAX,
165};
166
167#define CSIO_EVT_MSG_SIZE 512
168#define CSIO_EVTQ_SIZE 512
169
170
171struct csio_evt_msg {
172 struct list_head list;
173 enum csio_evt type;
174 uint8_t data[CSIO_EVT_MSG_SIZE];
175};
176
177enum {
178 SERNUM_LEN = 16,
179 EC_LEN = 16,
180 ID_LEN = 16,
181};
182
183enum {
184 SF_SIZE = SF_SEC_SIZE * 16,
185};
186
187
188enum {
189 SF_ATTEMPTS = 10,
190
191
192 SF_PROG_PAGE = 2,
193 SF_WR_DISABLE = 4,
194 SF_RD_STATUS = 5,
195 SF_WR_ENABLE = 6,
196 SF_RD_DATA_FAST = 0xb,
197 SF_RD_ID = 0x9f,
198 SF_ERASE_SECTOR = 0xd8,
199};
200
201
202enum {
203 CSIO_MGMT_EQ_WRSIZE = 512,
204 CSIO_MGMT_IQ_WRSIZE = 128,
205 CSIO_MGMT_EQLEN = 64,
206 CSIO_MGMT_IQLEN = 64,
207};
208
209#define CSIO_MGMT_EQSIZE (CSIO_MGMT_EQLEN * CSIO_MGMT_EQ_WRSIZE)
210#define CSIO_MGMT_IQSIZE (CSIO_MGMT_IQLEN * CSIO_MGMT_IQ_WRSIZE)
211
212
213struct csio_mgmtm_stats {
214 uint32_t n_abort_req;
215 uint32_t n_abort_rsp;
216 uint32_t n_close_req;
217 uint32_t n_close_rsp;
218 uint32_t n_err;
219 uint32_t n_drop;
220 uint32_t n_active;
221 uint32_t n_cbfn;
222};
223
224
225struct csio_mgmtm {
226 struct csio_hw *hw;
227 int eq_idx;
228 int iq_idx;
229 int msi_vec;
230 struct list_head active_q;
231 struct list_head abort_q;
232 struct list_head cbfn_q;
233 struct list_head mgmt_req_freelist;
234
235 struct timer_list mgmt_timer;
236 struct csio_mgmtm_stats stats;
237};
238
239struct csio_adap_desc {
240 char model_no[16];
241 char description[32];
242};
243
244struct pci_params {
245 uint16_t vendor_id;
246 uint16_t device_id;
247 int vpd_cap_addr;
248 uint16_t speed;
249 uint8_t width;
250};
251
252
253struct csio_hw_params {
254 uint32_t sf_size;
255
256
257 uint32_t sf_nsec;
258 struct pci_params pci;
259 uint32_t log_level;
260
261
262};
263
264struct csio_vpd {
265 uint32_t cclk;
266 uint8_t ec[EC_LEN + 1];
267 uint8_t sn[SERNUM_LEN + 1];
268 uint8_t id[ID_LEN + 1];
269};
270
271
272
273typedef u16 fw_port_cap16_t;
274typedef u32 fw_port_cap32_t;
275
276enum fw_caps {
277 FW_CAPS_UNKNOWN = 0,
278 FW_CAPS16 = 1,
279 FW_CAPS32 = 2,
280};
281
282enum cc_pause {
283 PAUSE_RX = 1 << 0,
284 PAUSE_TX = 1 << 1,
285 PAUSE_AUTONEG = 1 << 2
286};
287
288enum cc_fec {
289 FEC_AUTO = 1 << 0,
290 FEC_RS = 1 << 1,
291 FEC_BASER_RS = 1 << 2
292};
293
294struct link_config {
295 fw_port_cap32_t pcaps;
296 fw_port_cap32_t def_acaps;
297 fw_port_cap32_t acaps;
298 fw_port_cap32_t lpacaps;
299
300 fw_port_cap32_t speed_caps;
301 unsigned int speed;
302
303 enum cc_pause requested_fc;
304 enum cc_pause fc;
305
306 enum cc_fec requested_fec;
307 enum cc_fec fec;
308
309 unsigned char autoneg;
310
311 unsigned char link_ok;
312 unsigned char link_down_rc;
313};
314
315#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
316
317#define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
318 FW_PORT_CAP32_ANEG)
319
320
321#define AUTONEG_DISABLE 0x00
322#define AUTONEG_ENABLE 0x01
323
324struct csio_pport {
325 uint16_t pcap;
326 uint16_t acap;
327 uint8_t portid;
328 uint8_t link_status;
329 uint16_t link_speed;
330 uint8_t mac[6];
331 uint8_t mod_type;
332 uint8_t rsvd1;
333 uint8_t rsvd2;
334 uint8_t rsvd3;
335 struct link_config link_cfg;
336};
337
338
339struct csio_fcoe_res_info {
340 uint16_t e_d_tov;
341 uint16_t r_a_tov_seq;
342 uint16_t r_a_tov_els;
343 uint16_t r_r_tov;
344 uint32_t max_xchgs;
345 uint32_t max_ssns;
346 uint32_t used_xchgs;
347 uint32_t used_ssns;
348 uint32_t max_fcfs;
349 uint32_t max_vnps;
350 uint32_t used_fcfs;
351 uint32_t used_vnps;
352};
353
354
355enum csio_hw_ev {
356 CSIO_HWE_CFG = (uint32_t)1,
357 CSIO_HWE_INIT,
358 CSIO_HWE_INIT_DONE,
359 CSIO_HWE_FATAL,
360 CSIO_HWE_PCIERR_DETECTED,
361 CSIO_HWE_PCIERR_SLOT_RESET,
362 CSIO_HWE_PCIERR_RESUME,
363 CSIO_HWE_QUIESCED,
364 CSIO_HWE_HBA_RESET,
365 CSIO_HWE_HBA_RESET_DONE,
366 CSIO_HWE_FW_DLOAD,
367 CSIO_HWE_PCI_REMOVE,
368 CSIO_HWE_SUSPEND,
369 CSIO_HWE_RESUME,
370 CSIO_HWE_MAX,
371};
372
373
374struct csio_hw_stats {
375 uint32_t n_evt_activeq;
376 uint32_t n_evt_freeq;
377 uint32_t n_evt_drop;
378 uint32_t n_evt_unexp;
379 uint32_t n_pcich_offline;
380 uint32_t n_lnlkup_miss;
381 uint32_t n_cpl_fw6_msg;
382 uint32_t n_cpl_fw6_pld;
383 uint32_t n_cpl_unexp;
384 uint32_t n_mbint_unexp;
385
386 uint32_t n_plint_unexp;
387
388 uint32_t n_plint_cnt;
389 uint32_t n_int_stray;
390 uint32_t n_err;
391 uint32_t n_err_fatal;
392 uint32_t n_err_nomem;
393 uint32_t n_err_io;
394 enum csio_hw_ev n_evt_sm[CSIO_HWE_MAX];
395 uint64_t n_reset_start;
396 uint32_t rsvd1;
397};
398
399
400#define CSIO_HWF_MASTER 0x00000001
401
402
403
404#define CSIO_HWF_HW_INTR_ENABLED 0x00000002
405
406
407#define CSIO_HWF_FWEVT_PENDING 0x00000004
408#define CSIO_HWF_Q_MEM_ALLOCED 0x00000008
409
410
411#define CSIO_HWF_Q_FW_ALLOCED 0x00000010
412
413
414#define CSIO_HWF_VPD_VALID 0x00000020
415#define CSIO_HWF_DEVID_CACHED 0X00000040
416
417#define CSIO_HWF_FWEVT_STOP 0x00000080
418
419
420#define CSIO_HWF_USING_SOFT_PARAMS 0x00000100
421
422
423#define CSIO_HWF_HOST_INTR_ENABLED 0x00000200
424
425
426#define CSIO_HWF_ROOT_NO_RELAXED_ORDERING 0x00000400
427
428
429
430#define csio_is_hw_intr_enabled(__hw) \
431 ((__hw)->flags & CSIO_HWF_HW_INTR_ENABLED)
432#define csio_is_host_intr_enabled(__hw) \
433 ((__hw)->flags & CSIO_HWF_HOST_INTR_ENABLED)
434#define csio_is_hw_master(__hw) ((__hw)->flags & CSIO_HWF_MASTER)
435#define csio_is_valid_vpd(__hw) ((__hw)->flags & CSIO_HWF_VPD_VALID)
436#define csio_is_dev_id_cached(__hw) ((__hw)->flags & CSIO_HWF_DEVID_CACHED)
437#define csio_valid_vpd_copied(__hw) ((__hw)->flags |= CSIO_HWF_VPD_VALID)
438#define csio_dev_id_cached(__hw) ((__hw)->flags |= CSIO_HWF_DEVID_CACHED)
439
440
441enum csio_intr_mode {
442 CSIO_IM_NONE = 0,
443 CSIO_IM_INTX = 1,
444 CSIO_IM_MSI = 2,
445 CSIO_IM_MSIX = 3,
446};
447
448
449struct csio_hw {
450 struct csio_sm sm;
451
452
453 spinlock_t lock;
454
455 struct csio_scsim scsim;
456 struct csio_wrm wrm;
457 struct pci_dev *pdev;
458
459 void __iomem *regstart;
460
461
462
463 uint32_t num_sqsets;
464
465 uint32_t num_scsi_msix_cpus;
466
467
468
469
470
471 struct csio_scsi_qset sqset[CSIO_MAX_PPORTS][CSIO_MAX_SCSI_CPU];
472 struct csio_scsi_cpu_info scsi_cpu_info[CSIO_MAX_PPORTS];
473
474 uint32_t evtflag;
475 uint32_t flags;
476
477 struct csio_mgmtm mgmtm;
478 struct csio_mbm mbm;
479
480
481 uint32_t num_lns;
482 struct csio_lnode *rln;
483 struct list_head sln_head;
484
485
486 int intr_iq_idx;
487
488
489 int fwevt_iq_idx;
490 struct work_struct evtq_work;
491
492
493 struct list_head evt_free_q;
494
495
496 struct list_head evt_active_q;
497
498
499 char name[32];
500 char hw_ver[16];
501 char model_desc[32];
502 char drv_version[32];
503 char fwrev_str[32];
504 uint32_t optrom_ver;
505 uint32_t fwrev;
506 uint32_t tp_vers;
507 char chip_ver;
508 uint16_t chip_id;
509 enum csio_dev_state fw_state;
510 struct csio_vpd vpd;
511
512 uint8_t pfn;
513
514
515 uint32_t port_vec;
516 uint8_t num_pports;
517
518
519 uint8_t rst_retries;
520 uint8_t cur_evt;
521 uint8_t prev_evt;
522 uint32_t dev_num;
523 struct csio_pport pport[CSIO_MAX_PPORTS];
524 struct csio_hw_params params;
525
526 struct dma_pool *scsi_dma_pool;
527 mempool_t *mb_mempool;
528 mempool_t *rnode_mempool;
529
530
531 enum csio_intr_mode intr_mode;
532 uint32_t fwevt_intr_idx;
533
534
535 uint32_t nondata_intr_idx;
536
537
538
539 uint8_t cfg_neq;
540
541
542 uint8_t cfg_niq;
543
544
545
546 struct csio_fcoe_res_info fres_info;
547 struct csio_hw_chip_ops *chip_ops;
548
549
550
551
552 struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS];
553
554 struct dentry *debugfs_root;
555 struct csio_hw_stats stats;
556};
557
558
559#define csio_reg(_b, _r) ((_b) + (_r))
560
561#define csio_rd_reg8(_h, _r) readb(csio_reg((_h)->regstart, (_r)))
562#define csio_rd_reg16(_h, _r) readw(csio_reg((_h)->regstart, (_r)))
563#define csio_rd_reg32(_h, _r) readl(csio_reg((_h)->regstart, (_r)))
564#define csio_rd_reg64(_h, _r) readq(csio_reg((_h)->regstart, (_r)))
565
566#define csio_wr_reg8(_h, _v, _r) writeb((_v), \
567 csio_reg((_h)->regstart, (_r)))
568#define csio_wr_reg16(_h, _v, _r) writew((_v), \
569 csio_reg((_h)->regstart, (_r)))
570#define csio_wr_reg32(_h, _v, _r) writel((_v), \
571 csio_reg((_h)->regstart, (_r)))
572#define csio_wr_reg64(_h, _v, _r) writeq((_v), \
573 csio_reg((_h)->regstart, (_r)))
574
575void csio_set_reg_field(struct csio_hw *, uint32_t, uint32_t, uint32_t);
576
577
578static inline uint32_t
579csio_core_ticks_to_us(struct csio_hw *hw, uint32_t ticks)
580{
581
582 return (ticks * 1000 + hw->vpd.cclk/2) / hw->vpd.cclk;
583}
584
585static inline uint32_t
586csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us)
587{
588 return (us * hw->vpd.cclk) / 1000;
589}
590
591
592#define csio_hw_to_wrm(hw) ((struct csio_wrm *)(&(hw)->wrm))
593#define csio_hw_to_mbm(hw) ((struct csio_mbm *)(&(hw)->mbm))
594#define csio_hw_to_scsim(hw) ((struct csio_scsim *)(&(hw)->scsim))
595#define csio_hw_to_mgmtm(hw) ((struct csio_mgmtm *)(&(hw)->mgmtm))
596
597#define CSIO_PCI_BUS(hw) ((hw)->pdev->bus->number)
598#define CSIO_PCI_DEV(hw) (PCI_SLOT((hw)->pdev->devfn))
599#define CSIO_PCI_FUNC(hw) (PCI_FUNC((hw)->pdev->devfn))
600
601#define csio_set_fwevt_intr_idx(_h, _i) ((_h)->fwevt_intr_idx = (_i))
602#define csio_get_fwevt_intr_idx(_h) ((_h)->fwevt_intr_idx)
603#define csio_set_nondata_intr_idx(_h, _i) ((_h)->nondata_intr_idx = (_i))
604#define csio_get_nondata_intr_idx(_h) ((_h)->nondata_intr_idx)
605
606
607#define CSIO_DEVID(__dev) ((__dev)->dev_num)
608#define CSIO_DEVID_LO(__dev) (CSIO_DEVID((__dev)) & 0xFFFF)
609#define CSIO_DEVID_HI(__dev) ((CSIO_DEVID((__dev)) >> 16) & 0xFFFF)
610
611#define csio_info(__hw, __fmt, ...) \
612 dev_info(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
613
614#define csio_fatal(__hw, __fmt, ...) \
615 dev_crit(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
616
617#define csio_err(__hw, __fmt, ...) \
618 dev_err(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
619
620#define csio_warn(__hw, __fmt, ...) \
621 dev_warn(&(__hw)->pdev->dev, __fmt, ##__VA_ARGS__)
622
623#ifdef __CSIO_DEBUG__
624#define csio_dbg(__hw, __fmt, ...) \
625 csio_info((__hw), __fmt, ##__VA_ARGS__);
626#else
627#define csio_dbg(__hw, __fmt, ...)
628#endif
629
630int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int,
631 int, int, uint32_t *);
632void csio_hw_tp_wr_bits_indirect(struct csio_hw *, unsigned int,
633 unsigned int, unsigned int);
634int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *);
635void csio_hw_intr_disable(struct csio_hw *);
636int csio_hw_slow_intr_handler(struct csio_hw *);
637int csio_handle_intr_status(struct csio_hw *, unsigned int,
638 const struct intr_info *);
639
640fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps);
641fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16);
642fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32);
643fw_port_cap32_t lstatus_to_fwcap(u32 lstatus);
644
645int csio_hw_start(struct csio_hw *);
646int csio_hw_stop(struct csio_hw *);
647int csio_hw_reset(struct csio_hw *);
648int csio_is_hw_ready(struct csio_hw *);
649int csio_is_hw_removing(struct csio_hw *);
650
651int csio_fwevtq_handler(struct csio_hw *);
652void csio_evtq_worker(struct work_struct *);
653int csio_enqueue_evt(struct csio_hw *, enum csio_evt, void *, uint16_t);
654void csio_evtq_flush(struct csio_hw *hw);
655
656int csio_request_irqs(struct csio_hw *);
657void csio_intr_enable(struct csio_hw *);
658void csio_intr_disable(struct csio_hw *, bool);
659void csio_hw_fatal_err(struct csio_hw *);
660
661struct csio_lnode *csio_lnode_alloc(struct csio_hw *);
662int csio_config_queues(struct csio_hw *);
663
664int csio_hw_init(struct csio_hw *);
665void csio_hw_exit(struct csio_hw *);
666#endif
667