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7#ifndef _ESP_SCSI_H
8#define _ESP_SCSI_H
9
10
11#define ESP_TCLOW 0x00UL
12#define ESP_TCMED 0x01UL
13#define ESP_FDATA 0x02UL
14#define ESP_CMD 0x03UL
15#define ESP_STATUS 0x04UL
16#define ESP_BUSID ESP_STATUS
17#define ESP_INTRPT 0x05UL
18#define ESP_TIMEO ESP_INTRPT
19#define ESP_SSTEP 0x06UL
20#define ESP_STP ESP_SSTEP
21#define ESP_FFLAGS 0x07UL
22#define ESP_SOFF ESP_FFLAGS
23#define ESP_CFG1 0x08UL
24#define ESP_CFACT 0x09UL
25#define ESP_STATUS2 ESP_CFACT
26#define ESP_CTEST 0x0aUL
27#define ESP_CFG2 0x0bUL
28#define ESP_CFG3 0x0cUL
29#define ESP_CFG4 0x0dUL
30#define ESP_TCHI 0x0eUL
31#define ESP_UID ESP_TCHI
32#define FAS_RLO ESP_TCHI
33#define ESP_FGRND 0x0fUL
34#define FAS_RHI ESP_FGRND
35
36#define SBUS_ESP_REG_SIZE 0x40UL
37
38
39
40
41#define ESP_CONFIG1_ID 0x07
42#define ESP_CONFIG1_CHTEST 0x08
43#define ESP_CONFIG1_PENABLE 0x10
44#define ESP_CONFIG1_PARTEST 0x20
45#define ESP_CONFIG1_SRRDISAB 0x40
46#define ESP_CONFIG1_SLCABLE 0x80
47
48
49#define ESP_CONFIG2_DMAPARITY 0x01
50#define ESP_CONFIG2_REGPARITY 0x02
51#define ESP_CONFIG2_BADPARITY 0x04
52#define ESP_CONFIG2_SCSI2ENAB 0x08
53#define ESP_CONFIG2_HI 0x10
54#define ESP_CONFIG2_HMEFENAB 0x10
55#define ESP_CONFIG2_BCM 0x20
56#define ESP_CONFIG2_DISPINT 0x20
57#define ESP_CONFIG2_FENAB 0x40
58#define ESP_CONFIG2_SPL 0x40
59#define ESP_CONFIG2_MKDONE 0x40
60#define ESP_CONFIG2_HME32 0x80
61#define ESP_CONFIG2_MAGIC 0xe0
62
63
64#define ESP_CONFIG3_FCLOCK 0x01
65#define ESP_CONFIG3_TEM 0x01
66#define ESP_CONFIG3_FAST 0x02
67#define ESP_CONFIG3_ADMA 0x02
68#define ESP_CONFIG3_TENB 0x04
69#define ESP_CONFIG3_SRB 0x04
70#define ESP_CONFIG3_TMS 0x08
71#define ESP_CONFIG3_FCLK 0x08
72#define ESP_CONFIG3_IDMSG 0x10
73#define ESP_CONFIG3_FSCSI 0x10
74#define ESP_CONFIG3_GTM 0x20
75#define ESP_CONFIG3_IDBIT3 0x20
76#define ESP_CONFIG3_TBMS 0x40
77#define ESP_CONFIG3_EWIDE 0x40
78#define ESP_CONFIG3_IMS 0x80
79#define ESP_CONFIG3_OBPUSH 0x80
80
81
82#define ESP_CONFIG4_BBTE 0x01
83#define ESP_CONGIG4_TEST 0x02
84#define ESP_CONFIG4_RADE 0x04
85#define ESP_CONFIG4_RAE 0x08
86#define ESP_CONFIG4_PWD 0x20
87#define ESP_CONFIG4_GE0 0x40
88#define ESP_CONFIG4_GE1 0x80
89
90#define ESP_CONFIG_GE_12NS (0)
91#define ESP_CONFIG_GE_25NS (ESP_CONFIG_GE1)
92#define ESP_CONFIG_GE_35NS (ESP_CONFIG_GE0)
93#define ESP_CONFIG_GE_0NS (ESP_CONFIG_GE0 | ESP_CONFIG_GE1)
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100
101#define ESP_CMD_NULL 0x00
102#define ESP_CMD_FLUSH 0x01
103#define ESP_CMD_RC 0x02
104#define ESP_CMD_RS 0x03
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108
109#define ESP_CMD_TI 0x10
110#define ESP_CMD_ICCSEQ 0x11
111#define ESP_CMD_MOK 0x12
112#define ESP_CMD_TPAD 0x18
113#define ESP_CMD_SATN 0x1a
114#define ESP_CMD_RATN 0x1b
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117
118
119#define ESP_CMD_SMSG 0x20
120#define ESP_CMD_SSTAT 0x21
121#define ESP_CMD_SDATA 0x22
122#define ESP_CMD_DSEQ 0x23
123#define ESP_CMD_TSEQ 0x24
124#define ESP_CMD_TCCSEQ 0x25
125#define ESP_CMD_DCNCT 0x27
126#define ESP_CMD_RMSG 0x28
127#define ESP_CMD_RCMD 0x29
128#define ESP_CMD_RDATA 0x2a
129#define ESP_CMD_RCSEQ 0x2b
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134
135#define ESP_CMD_RSEL 0x40
136#define ESP_CMD_SEL 0x41
137#define ESP_CMD_SELA 0x42
138#define ESP_CMD_SELAS 0x43
139#define ESP_CMD_ESEL 0x44
140#define ESP_CMD_DSEL 0x45
141#define ESP_CMD_SA3 0x46
142#define ESP_CMD_RSEL3 0x47
143
144
145#define ESP_CMD_DMA 0x80
146
147
148#define ESP_STAT_PIO 0x01
149#define ESP_STAT_PCD 0x02
150#define ESP_STAT_PMSG 0x04
151#define ESP_STAT_PMASK 0x07
152#define ESP_STAT_TDONE 0x08
153#define ESP_STAT_TCNT 0x10
154#define ESP_STAT_PERR 0x20
155#define ESP_STAT_SPAM 0x40
156
157
158
159#define ESP_STAT_INTR 0x80
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165
166#define ESP_DOP (0)
167#define ESP_DIP (ESP_STAT_PIO)
168#define ESP_CMDP (ESP_STAT_PCD)
169#define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO)
170#define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD)
171#define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO)
172
173
174#define ESP_STAT2_SCHBIT 0x01
175#define ESP_STAT2_FFLAGS 0x02
176#define ESP_STAT2_XCNT 0x04
177#define ESP_STAT2_CREGA 0x08
178#define ESP_STAT2_WIDE 0x10
179#define ESP_STAT2_F1BYTE 0x20
180#define ESP_STAT2_FMSB 0x40
181#define ESP_STAT2_FEMPTY 0x80
182
183
184#define ESP_INTR_S 0x01
185#define ESP_INTR_SATN 0x02
186#define ESP_INTR_RSEL 0x04
187#define ESP_INTR_FDONE 0x08
188#define ESP_INTR_BSERV 0x10
189#define ESP_INTR_DC 0x20
190#define ESP_INTR_IC 0x40
191#define ESP_INTR_SR 0x80
192
193
194#define ESP_STEP_VBITS 0x07
195#define ESP_STEP_ASEL 0x00
196#define ESP_STEP_SID 0x01
197#define ESP_STEP_NCMD 0x02
198#define ESP_STEP_PPC 0x03
199
200
201#define ESP_STEP_FINI4 0x04
202
203
204#define ESP_STEP_FINI5 0x05
205#define ESP_STEP_FINI6 0x06
206#define ESP_STEP_FINI7 0x07
207
208
209#define ESP_TEST_TARG 0x01
210#define ESP_TEST_INI 0x02
211#define ESP_TEST_TS 0x04
212
213
214#define ESP_UID_FAM 0xf8
215
216#define ESP_FAMILY(uid) (((uid) & ESP_UID_FAM) >> 3)
217
218
219#define ESP_UID_F100A 0x00
220#define ESP_UID_F236 0x02
221#define ESP_UID_HME 0x0a
222#define ESP_UID_FSC 0x14
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225
226#define ESP_FF_FBYTES 0x1f
227#define ESP_FF_ONOTZERO 0x20
228#define ESP_FF_SSTEP 0xe0
229
230
231#define ESP_CCF_F0 0x00
232#define ESP_CCF_NEVER 0x01
233#define ESP_CCF_F2 0x02
234#define ESP_CCF_F3 0x03
235#define ESP_CCF_F4 0x04
236#define ESP_CCF_F5 0x05
237#define ESP_CCF_F6 0x06
238#define ESP_CCF_F7 0x07
239
240
241#define ESP_BUSID_RESELID 0x10
242#define ESP_BUSID_CTR32BIT 0x40
243
244#define ESP_BUS_TIMEOUT 250
245#define ESP_TIMEO_CONST 8192
246#define ESP_NEG_DEFP(mhz, cfact) \
247 ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
248#define ESP_HZ_TO_CYCLE(hertz) ((1000000000) / ((hertz) / 1000))
249#define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
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255#define SYNC_DEFP_SLOW 0x32
256#define SYNC_DEFP_FAST 0x19
257
258struct esp_cmd_priv {
259 int num_sg;
260 int cur_residue;
261 struct scatterlist *prv_sg;
262 struct scatterlist *cur_sg;
263 int tot_residue;
264};
265#define ESP_CMD_PRIV(CMD) ((struct esp_cmd_priv *)(&(CMD)->SCp))
266
267
268enum esp_rev {
269 ESP100,
270 ESP100A,
271 ESP236,
272 FAS236,
273 PCSCSI,
274 FSC,
275 FAS100A,
276 FAST,
277 FASHME,
278};
279
280struct esp_cmd_entry {
281 struct list_head list;
282
283 struct scsi_cmnd *cmd;
284
285 unsigned int saved_cur_residue;
286 struct scatterlist *saved_prv_sg;
287 struct scatterlist *saved_cur_sg;
288 unsigned int saved_tot_residue;
289
290 u8 flags;
291#define ESP_CMD_FLAG_WRITE 0x01
292#define ESP_CMD_FLAG_AUTOSENSE 0x04
293#define ESP_CMD_FLAG_RESIDUAL 0x08
294
295 u8 tag[2];
296 u8 orig_tag[2];
297
298 u8 status;
299 u8 message;
300
301 unsigned char *sense_ptr;
302 unsigned char *saved_sense_ptr;
303 dma_addr_t sense_dma;
304
305 struct completion *eh_done;
306};
307
308#define ESP_DEFAULT_TAGS 16
309
310#define ESP_MAX_TARGET 16
311#define ESP_MAX_LUN 8
312#define ESP_MAX_TAG 256
313
314struct esp_lun_data {
315 struct esp_cmd_entry *non_tagged_cmd;
316 int num_tagged;
317 int hold;
318 struct esp_cmd_entry *tagged_cmds[ESP_MAX_TAG];
319};
320
321struct esp_target_data {
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326 u8 esp_period;
327 u8 esp_offset;
328 u8 esp_config3;
329
330 u8 flags;
331#define ESP_TGT_WIDE 0x01
332#define ESP_TGT_DISCONNECT 0x02
333#define ESP_TGT_NEGO_WIDE 0x04
334#define ESP_TGT_NEGO_SYNC 0x08
335#define ESP_TGT_CHECK_NEGO 0x40
336#define ESP_TGT_BROKEN 0x80
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341 u8 nego_goal_period;
342 u8 nego_goal_offset;
343 u8 nego_goal_width;
344 u8 nego_goal_tags;
345
346 struct scsi_target *starget;
347};
348
349struct esp_event_ent {
350 u8 type;
351#define ESP_EVENT_TYPE_EVENT 0x01
352#define ESP_EVENT_TYPE_CMD 0x02
353 u8 val;
354
355 u8 sreg;
356 u8 seqreg;
357 u8 sreg2;
358 u8 ireg;
359 u8 select_state;
360 u8 event;
361 u8 __pad;
362};
363
364struct esp;
365struct esp_driver_ops {
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370 void (*esp_write8)(struct esp *esp, u8 val, unsigned long reg);
371 u8 (*esp_read8)(struct esp *esp, unsigned long reg);
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378 int (*irq_pending)(struct esp *esp);
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383 u32 (*dma_length_limit)(struct esp *esp, u32 dma_addr,
384 u32 dma_len);
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390 void (*reset_dma)(struct esp *esp);
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395 void (*dma_drain)(struct esp *esp);
396
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398 void (*dma_invalidate)(struct esp *esp);
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410 void (*send_dma_cmd)(struct esp *esp, u32 dma_addr, u32 esp_count,
411 u32 dma_count, int write, u8 cmd);
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415
416 int (*dma_error)(struct esp *esp);
417};
418
419#define ESP_MAX_MSG_SZ 8
420#define ESP_EVENT_LOG_SZ 32
421
422#define ESP_QUICKIRQ_LIMIT 100
423#define ESP_RESELECT_TAG_LIMIT 2500
424
425struct esp {
426 void __iomem *regs;
427 void __iomem *dma_regs;
428
429 const struct esp_driver_ops *ops;
430
431 struct Scsi_Host *host;
432 struct device *dev;
433
434 struct esp_cmd_entry *active_cmd;
435
436 struct list_head queued_cmds;
437 struct list_head active_cmds;
438
439 u8 *command_block;
440 dma_addr_t command_block_dma;
441
442 unsigned int data_dma_len;
443
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446
447 u8 sreg;
448 u8 seqreg;
449 u8 sreg2;
450 u8 ireg;
451
452 u32 prev_hme_dmacsr;
453 u8 prev_soff;
454 u8 prev_stp;
455 u8 prev_cfg3;
456 u8 num_tags;
457
458 struct list_head esp_cmd_pool;
459
460 struct esp_target_data target[ESP_MAX_TARGET];
461
462 int fifo_cnt;
463 u8 fifo[16];
464
465 struct esp_event_ent esp_event_log[ESP_EVENT_LOG_SZ];
466 int esp_event_cur;
467
468 u8 msg_out[ESP_MAX_MSG_SZ];
469 int msg_out_len;
470
471 u8 msg_in[ESP_MAX_MSG_SZ];
472 int msg_in_len;
473
474 u8 bursts;
475 u8 config1;
476 u8 config2;
477 u8 config4;
478
479 u8 scsi_id;
480 u32 scsi_id_mask;
481
482 enum esp_rev rev;
483
484 u32 flags;
485#define ESP_FLAG_DIFFERENTIAL 0x00000001
486#define ESP_FLAG_RESETTING 0x00000002
487#define ESP_FLAG_WIDE_CAPABLE 0x00000008
488#define ESP_FLAG_QUICKIRQ_CHECK 0x00000010
489#define ESP_FLAG_DISABLE_SYNC 0x00000020
490#define ESP_FLAG_USE_FIFO 0x00000040
491#define ESP_FLAG_NO_DMA_MAP 0x00000080
492
493 u8 select_state;
494#define ESP_SELECT_NONE 0x00
495#define ESP_SELECT_BASIC 0x01
496#define ESP_SELECT_MSGOUT 0x02
497
498
499 u8 event;
500#define ESP_EVENT_NONE 0x00
501#define ESP_EVENT_CMD_START 0x01
502#define ESP_EVENT_CMD_DONE 0x02
503#define ESP_EVENT_DATA_IN 0x03
504#define ESP_EVENT_DATA_OUT 0x04
505#define ESP_EVENT_DATA_DONE 0x05
506#define ESP_EVENT_MSGIN 0x06
507#define ESP_EVENT_MSGIN_MORE 0x07
508#define ESP_EVENT_MSGIN_DONE 0x08
509#define ESP_EVENT_MSGOUT 0x09
510#define ESP_EVENT_MSGOUT_DONE 0x0a
511#define ESP_EVENT_STATUS 0x0b
512#define ESP_EVENT_FREE_BUS 0x0c
513#define ESP_EVENT_CHECK_PHASE 0x0d
514#define ESP_EVENT_RESET 0x10
515
516
517 u32 cfact;
518 u32 cfreq;
519 u32 ccycle;
520 u32 ctick;
521 u32 neg_defp;
522 u32 sync_defp;
523
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525 u32 max_period;
526 u32 min_period;
527 u32 radelay;
528
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530 u8 *cmd_bytes_ptr;
531 int cmd_bytes_left;
532
533 struct completion *eh_reset;
534
535 void *dma;
536 int dmarev;
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539 u8 __iomem *fifo_reg;
540 int send_cmd_error;
541 u32 send_cmd_residual;
542};
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574extern struct scsi_host_template scsi_esp_template;
575extern int scsi_esp_register(struct esp *);
576
577extern void scsi_esp_unregister(struct esp *);
578extern irqreturn_t scsi_esp_intr(int, void *);
579extern void scsi_esp_cmd(struct esp *, u8);
580
581extern void esp_send_pio_cmd(struct esp *esp, u32 dma_addr, u32 esp_count,
582 u32 dma_count, int write, u8 cmd);
583
584#endif
585