1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Support for Medifield PNW Camera Imaging ISP subsystem. 4 * 5 * Copyright (c) 2012 Intel Corporation. All Rights Reserved. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License version 9 * 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * 17 */ 18 19#ifndef ATOMISP_REGS_H 20#define ATOMISP_REGS_H 21 22/* common register definitions */ 23#define PCICMDSTS 0x01 24#define INTR 0x0f 25#define MSI_CAPID 0x24 26#define MSI_ADDRESS 0x25 27#define MSI_DATA 0x26 28#define INTR_CTL 0x27 29 30#define PCI_MSI_CAPID 0x90 31#define PCI_MSI_ADDR 0x94 32#define PCI_MSI_DATA 0x98 33#define PCI_INTERRUPT_CTRL 0x9C 34#define PCI_I_CONTROL 0xfc 35 36/* MRFLD specific register definitions */ 37#define MRFLD_CSI_AFE 0x39 38#define MRFLD_CSI_CONTROL 0x3a 39#define MRFLD_CSI_RCOMP 0x3d 40 41#define MRFLD_PCI_PMCS 0x84 42#define MRFLD_PCI_CSI_ACCESS_CTRL_VIOL 0xd4 43#define MRFLD_PCI_CSI_AFE_HS_CONTROL 0xdc 44#define MRFLD_PCI_CSI_AFE_RCOMP_CONTROL 0xe0 45#define MRFLD_PCI_CSI_CONTROL 0xe8 46#define MRFLD_PCI_CSI_AFE_TRIM_CONTROL 0xe4 47#define MRFLD_PCI_CSI_DEADLINE_CONTROL 0xec 48#define MRFLD_PCI_CSI_RCOMP_CONTROL 0xf4 49 50/* Select Arasan (legacy)/Intel input system */ 51#define MRFLD_PCI_CSI_CONTROL_PARPATHEN BIT(24) 52/* Enable CSI interface (ANN B0/K0) */ 53#define MRFLD_PCI_CSI_CONTROL_CSI_READY BIT(25) 54 55/* 56 * Enables the combining of adjacent 32-byte read requests to the same 57 * cache line. When cleared, each 32-byte read request is sent as a 58 * separate request on the IB interface. 59 */ 60#define MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING 0x1 61 62/* 63 * Register: MRFLD_PCI_CSI_RCOMP_CONTROL 64 * If cleared, the high speed clock going to the digital logic is gated when 65 * RCOMP update is happening. The clock is gated for a minimum of 100 nsec. 66 * If this bit is set, then the high speed clock is not gated during the 67 * update cycle. 68 */ 69#define MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE 0x800000 70 71/* 72 * Enables the combining of adjacent 32-byte write requests to the same 73 * cache line. When cleared, each 32-byte write request is sent as a 74 * separate request on the IB interface. 75 */ 76#define MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING 0x2 77 78#define MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK 0xc 79 80#define MRFLD_PCI_CSI1_HSRXCLKTRIM 0x2 81#define MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT 16 82#define MRFLD_PCI_CSI2_HSRXCLKTRIM 0x3 83#define MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT 24 84#define MRFLD_PCI_CSI3_HSRXCLKTRIM 0x2 85#define MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT 28 86#define MRFLD_PCI_CSI_HSRXCLKTRIM_MASK 0xf 87 88/* 89 * This register is IUINT MMIO register, it is used to select the CSI 90 * receiver backend. 91 * 1: SH CSI backend 92 * 0: Arasan CSI backend 93 */ 94#define MRFLD_CSI_RECEIVER_SELECTION_REG 0x8081c 95 96#define MRFLD_INTR_CLEAR_REG 0x50c 97#define MRFLD_INTR_STATUS_REG 0x508 98#define MRFLD_INTR_ENABLE_REG 0x510 99 100#define MRFLD_MAX_ZOOM_FACTOR 1024 101 102/* MRFLD ISP POWER related */ 103#define MRFLD_ISPSSPM0 0x39 104#define MRFLD_ISPSSPM0_ISPSSC_OFFSET 0 105#define MRFLD_ISPSSPM0_ISPSSS_OFFSET 24 106#define MRFLD_ISPSSPM0_ISPSSC_MASK 0x3 107#define MRFLD_ISPSSPM0_IUNIT_POWER_ON 0 108#define MRFLD_ISPSSPM0_IUNIT_POWER_OFF 0x3 109#define MRFLD_ISPSSDVFS 0x13F 110#define MRFLD_BIT0 0x0001 111#define MRFLD_BIT1 0x0002 112 113/* MRFLD CSI lane configuration related */ 114#define MRFLD_PORT_CONFIG_NUM 8 115#define MRFLD_PORT_NUM 3 116#define MRFLD_PORT1_ENABLE_SHIFT 0 117#define MRFLD_PORT2_ENABLE_SHIFT 1 118#define MRFLD_PORT3_ENABLE_SHIFT 2 119#define MRFLD_PORT1_LANES_SHIFT 3 120#define MRFLD_PORT2_LANES_SHIFT 7 121#define MRFLD_PORT3_LANES_SHIFT 8 122#define MRFLD_PORT_CONFIG_MASK 0x000f03ff 123#define MRFLD_PORT_CONFIGCODE_SHIFT 16 124#define MRFLD_ALL_CSI_PORTS_OFF_MASK 0x7 125 126#define CHV_PORT3_LANES_SHIFT 9 127#define CHV_PORT_CONFIG_MASK 0x1f07ff 128 129#define ISPSSPM1 0x3a 130#define ISP_FREQ_STAT_MASK (0x1f << ISP_FREQ_STAT_OFFSET) 131#define ISP_REQ_FREQ_MASK 0x1f 132#define ISP_FREQ_VALID_MASK (0x1 << ISP_FREQ_VALID_OFFSET) 133#define ISP_FREQ_STAT_OFFSET 0x18 134#define ISP_REQ_GUAR_FREQ_OFFSET 0x8 135#define ISP_REQ_FREQ_OFFSET 0x0 136#define ISP_FREQ_VALID_OFFSET 0x7 137#define ISP_FREQ_RULE_ANY 0x0 138 139#define ISP_FREQ_457MHZ 0x1C9 140#define ISP_FREQ_400MHZ 0x190 141#define ISP_FREQ_356MHZ 0x164 142#define ISP_FREQ_320MHZ 0x140 143#define ISP_FREQ_266MHZ 0x10a 144#define ISP_FREQ_200MHZ 0xc8 145#define ISP_FREQ_100MHZ 0x64 146 147#define HPLL_FREQ_800MHZ 0x320 148#define HPLL_FREQ_1600MHZ 0x640 149#define HPLL_FREQ_2000MHZ 0x7D0 150 151#define CCK_FUSE_REG_0 0x08 152#define CCK_FUSE_HPLL_FREQ_MASK 0x03 153 154/* ISP2401 CSI2+ receiver delay settings */ 155#define CSI2_PORT_A_BASE 0xC0000 156#define CSI2_PORT_B_BASE 0xC2000 157#define CSI2_PORT_C_BASE 0xC4000 158 159#define CSI2_LANE_CL_BASE 0x418 160#define CSI2_LANE_D0_BASE 0x420 161#define CSI2_LANE_D1_BASE 0x428 162#define CSI2_LANE_D2_BASE 0x430 163#define CSI2_LANE_D3_BASE 0x438 164 165#define CSI2_REG_RX_CSI_DLY_CNT_TERMEN 0 166#define CSI2_REG_RX_CSI_DLY_CNT_SETTLE 0x4 167 168#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC0418 169#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC041C 170#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC0420 171#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC0424 172#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC0428 173#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC042C 174#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE2 0xC0430 175#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE2 0xC0434 176#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE3 0xC0438 177#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE3 0xC043C 178 179#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC2418 180#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC241C 181#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC2420 182#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC2424 183#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC2428 184#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC242C 185 186#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC4418 187#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC441C 188#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC4420 189#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC4424 190#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC4428 191#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC442C 192 193#define DMA_BURST_SIZE_REG 0xCD408 194 195#define ISP_DFS_TRY_TIMES 2 196 197#endif /* ATOMISP_REGS_H */ 198