1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16#ifndef _input_system_ctrl_defs_h 17#define _input_system_ctrl_defs_h 18 19#define _INPUT_SYSTEM_CTRL_REG_ALIGN 4 /* assuming 32 bit control bus width */ 20 21/* --------------------------------------------------*/ 22 23/* --------------------------------------------------*/ 24/* REGISTER INFO */ 25/* --------------------------------------------------*/ 26 27// Number of registers 28#define ISYS_CTRL_NOF_REGS 23 29 30// Register id's of MMIO slave accessible registers 31#define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID 0 32#define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID 1 33#define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID 2 34#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID 3 35#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID 4 36#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID 5 37#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID 6 38#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID 7 39#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID 8 40#define ISYS_CTRL_ACQ_START_ADDR_REG_ID 9 41#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID 10 42#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID 11 43#define ISYS_CTRL_INIT_REG_ID 12 44#define ISYS_CTRL_LAST_COMMAND_REG_ID 13 45#define ISYS_CTRL_NEXT_COMMAND_REG_ID 14 46#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID 15 47#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID 16 48#define ISYS_CTRL_FSM_STATE_INFO_REG_ID 17 49#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID 18 50#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID 19 51#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20 52#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21 53#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22 54 55/* register reset value */ 56#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0 57#define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL 0 58#define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL 0 59#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128 60#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128 61#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128 62#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3 63#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3 64#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3 65#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0 66#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128 67#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3 68#define ISYS_CTRL_INIT_REG_RSTVAL 0 69#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) 70#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) 71#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) 72#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) 73#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0 74#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0 75#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0 76#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0 77#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0 78#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0 79 80/* register width value */ 81#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9 82#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9 83#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9 84#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9 85#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9 86#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9 87#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9 88#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9 89#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9 90#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9 91#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9 92#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9 93#define ISYS_CTRL_INIT_REG_WIDTH 3 94#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */ 95#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32 96#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32 97#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH 32 98#define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH 32 99#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH 32 100#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH 32 101#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH 32 102#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH 32 103#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH 1 104 105/* bit definitions */ 106 107/* --------------------------------------------------*/ 108/* TOKEN INFO */ 109/* --------------------------------------------------*/ 110 111/* 112InpSysCaptFramesAcq 1/0 [3:0] - 'b0000 113[7:4] - CaptPortId, 114 CaptA-'b0000 115 CaptB-'b0001 116 CaptC-'b0010 117[31:16] - NOF_frames 118InpSysCaptFrameExt 2/0 [3:0] - 'b0001' 119[7:4] - CaptPortId, 120 'b0000 - CaptA 121 'b0001 - CaptB 122 'b0010 - CaptC 123 124 2/1 [31:0] - external capture address 125InpSysAcqFrame 2/0 [3:0] - 'b0010, 126[31:4] - NOF_ext_mem_words 127 2/1 [31:0] - external memory read start address 128InpSysOverruleON 1/0 [3:0] - 'b0011, 129[7:4] - overrule port id (opid) 130 'b0000 - CaptA 131 'b0001 - CaptB 132 'b0010 - CaptC 133 'b0011 - Acq 134 'b0100 - DMA 135 136InpSysOverruleOFF 1/0 [3:0] - 'b0100, 137[7:4] - overrule port id (opid) 138 'b0000 - CaptA 139 'b0001 - CaptB 140 'b0010 - CaptC 141 'b0011 - Acq 142 'b0100 - DMA 143 144InpSysOverruleCmd 2/0 [3:0] - 'b0101, 145[7:4] - overrule port id (opid) 146 'b0000 - CaptA 147 'b0001 - CaptB 148 'b0010 - CaptC 149 'b0011 - Acq 150 'b0100 - DMA 151 152 2/1 [31:0] - command token value for port opid 153 154acknowledge tokens: 155 156InpSysAckCFA 1/0 [3:0] - 'b0000 157 [7:4] - CaptPortId, 158 CaptA-'b0000 159 CaptB- 'b0001 160 CaptC-'b0010 161 [31:16] - NOF_frames 162InpSysAckCFE 1/0 [3:0] - 'b0001' 163[7:4] - CaptPortId, 164 'b0000 - CaptA 165 'b0001 - CaptB 166 'b0010 - CaptC 167 168InpSysAckAF 1/0 [3:0] - 'b0010 169InpSysAckOverruleON 1/0 [3:0] - 'b0011, 170[7:4] - overrule port id (opid) 171 'b0000 - CaptA 172 'b0001 - CaptB 173 'b0010 - CaptC 174 'b0011 - Acq 175 'b0100 - DMA 176 177InpSysAckOverruleOFF 1/0 [3:0] - 'b0100, 178[7:4] - overrule port id (opid) 179 'b0000 - CaptA 180 'b0001 - CaptB 181 'b0010 - CaptC 182 'b0011 - Acq 183 'b0100 - DMA 184 185InpSysAckOverrule 2/0 [3:0] - 'b0101, 186[7:4] - overrule port id (opid) 187 'b0000 - CaptA 188 'b0001 - CaptB 189 'b0010 - CaptC 190 'b0011 - Acq 191 'b0100 - DMA 192 193 2/1 [31:0] - acknowledge token value from port opid 194 195*/ 196 197/* Command and acknowledge tokens IDs */ 198#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */ 199#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */ 200#define ISYS_CTRL_ACQ_FRAME_TOKEN_ID 2 /* 0010b */ 201#define ISYS_CTRL_OVERRULE_ON_TOKEN_ID 3 /* 0011b */ 202#define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID 4 /* 0100b */ 203#define ISYS_CTRL_OVERRULE_TOKEN_ID 5 /* 0101b */ 204 205#define ISYS_CTRL_ACK_CFA_TOKEN_ID 0 206#define ISYS_CTRL_ACK_CFE_TOKEN_ID 1 207#define ISYS_CTRL_ACK_AF_TOKEN_ID 2 208#define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID 3 209#define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID 4 210#define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID 5 211#define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID 6 212 213#define ISYS_CTRL_TOKEN_ID_MSB 3 214#define ISYS_CTRL_TOKEN_ID_LSB 0 215#define ISYS_CTRL_PORT_ID_TOKEN_MSB 7 216#define ISYS_CTRL_PORT_ID_TOKEN_LSB 4 217#define ISYS_CTRL_NOF_CAPT_TOKEN_MSB 31 218#define ISYS_CTRL_NOF_CAPT_TOKEN_LSB 16 219#define ISYS_CTRL_NOF_EXT_TOKEN_MSB 31 220#define ISYS_CTRL_NOF_EXT_TOKEN_LSB 8 221 222#define ISYS_CTRL_TOKEN_ID_IDX 0 223#define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1) 224#define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS) 225#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB + 1) 226#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB 227#define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1) 228#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB 229#define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1) 230 231#define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */ 232#define ISYS_CTRL_PORT_ID_CAPT_B 1 /* device ID for capture unit B */ 233#define ISYS_CTRL_PORT_ID_CAPT_C 2 /* device ID for capture unit C */ 234#define ISYS_CTRL_PORT_ID_ACQUISITION 3 /* device ID for acquistion unit */ 235#define ISYS_CTRL_PORT_ID_DMA_CAPT_A 4 /* device ID for dma unit */ 236#define ISYS_CTRL_PORT_ID_DMA_CAPT_B 5 /* device ID for dma unit */ 237#define ISYS_CTRL_PORT_ID_DMA_CAPT_C 6 /* device ID for dma unit */ 238#define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */ 239 240#define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */ 241#define ISYS_CTRL_NO_DMA_ACK 0 242#define ISYS_CTRL_NO_CAPT_ACK 16 243 244#endif /* _input_system_ctrl_defs_h */ 245