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16#ifndef __INPUT_SYSTEM_LOCAL_H_INCLUDED__
17#define __INPUT_SYSTEM_LOCAL_H_INCLUDED__
18
19#include <type_support.h>
20
21#include "input_system_global.h"
22
23#include "input_system_defs.h"
24
25
26
27
28
29#include "css_receiver_2400_defs.h"
30
31#include "isp_capture_defs.h"
32
33#include "isp_acquisition_defs.h"
34#include "input_system_ctrl_defs.h"
35
36typedef enum {
37 INPUT_SYSTEM_PORT_A = 0,
38 INPUT_SYSTEM_PORT_B,
39 INPUT_SYSTEM_PORT_C,
40 N_INPUT_SYSTEM_PORTS
41} input_system_csi_port_t;
42
43typedef struct ctrl_unit_cfg_s ctrl_unit_cfg_t;
44typedef struct input_system_network_cfg_s input_system_network_cfg_t;
45typedef struct target_cfg2400_s target_cfg2400_t;
46typedef struct channel_cfg_s channel_cfg_t;
47typedef struct backend_channel_cfg_s backend_channel_cfg_t;
48typedef struct input_system_cfg2400_s input_system_cfg2400_t;
49typedef struct mipi_port_state_s mipi_port_state_t;
50typedef struct rx_channel_state_s rx_channel_state_t;
51typedef struct input_switch_cfg_channel_s input_switch_cfg_channel_t;
52typedef struct input_switch_cfg_s input_switch_cfg_t;
53
54struct ctrl_unit_cfg_s {
55 isp2400_ib_buffer_t buffer_mipi[N_CAPTURE_UNIT_ID];
56 isp2400_ib_buffer_t buffer_acquire[N_ACQUISITION_UNIT_ID];
57};
58
59struct input_system_network_cfg_s {
60 input_system_connection_t multicast_cfg[N_CAPTURE_UNIT_ID];
61 input_system_multiplex_t mux_cfg;
62 ctrl_unit_cfg_t ctrl_unit_cfg[N_CTRL_UNIT_ID];
63};
64
65typedef struct {
66
67 u32 dummy_parameter;
68} target_isp_cfg_t;
69
70typedef struct {
71
72 u32 dummy_parameter;
73} target_sp_cfg_t;
74
75typedef struct {
76
77 u32 dummy_parameter;
78} target_strm2mem_cfg_t;
79
80struct input_switch_cfg_channel_s {
81 u32 hsync_data_reg[2];
82 u32 vsync_data_reg;
83};
84
85struct target_cfg2400_s {
86 input_switch_cfg_channel_t input_switch_channel_cfg;
87 target_isp_cfg_t target_isp_cfg;
88 target_sp_cfg_t target_sp_cfg;
89 target_strm2mem_cfg_t target_strm2mem_cfg;
90};
91
92struct backend_channel_cfg_s {
93 u32 fmt_control_word_1;
94 u32 fmt_control_word_2;
95 u32 no_side_band;
96};
97
98typedef union {
99 csi_cfg_t csi_cfg;
100 tpg_cfg_t tpg_cfg;
101 prbs_cfg_t prbs_cfg;
102 gpfifo_cfg_t gpfifo_cfg;
103} source_cfg_t;
104
105struct input_switch_cfg_s {
106 u32 hsync_data_reg[N_RX_CHANNEL_ID * 2];
107 u32 vsync_data_reg;
108};
109
110
111struct channel_cfg_s {
112 u32 ch_id;
113 backend_channel_cfg_t backend_ch;
114 input_system_source_t source_type;
115 source_cfg_t source_cfg;
116 target_cfg2400_t target_cfg;
117};
118
119
120struct input_system_cfg2400_s {
121 input_system_source_t source_type;
122 input_system_config_flags_t source_type_flags;
123
124 input_system_config_flags_t ch_flags[N_CHANNELS];
125
126 csi_cfg_t csi_value[N_CSI_PORTS];
127 input_system_config_flags_t csi_flags[N_CSI_PORTS];
128
129
130
131 isp2400_ib_buffer_t csi_buffer[N_CSI_PORTS];
132 input_system_config_flags_t csi_buffer_flags[N_CSI_PORTS];
133 isp2400_ib_buffer_t acquisition_buffer_unique;
134 input_system_config_flags_t acquisition_buffer_unique_flags;
135 u32 unallocated_ib_mem_words;
136
137
138 input_system_connection_t multicast[N_CSI_PORTS];
139 input_system_multiplex_t multiplexer;
140 input_system_config_flags_t multiplexer_flags;
141
142 tpg_cfg_t tpg_value;
143 input_system_config_flags_t tpg_flags;
144 prbs_cfg_t prbs_value;
145 input_system_config_flags_t prbs_flags;
146 gpfifo_cfg_t gpfifo_value;
147 input_system_config_flags_t gpfifo_flags;
148
149 input_switch_cfg_t input_switch_cfg;
150
151 target_isp_cfg_t target_isp[N_CHANNELS];
152 input_system_config_flags_t target_isp_flags[N_CHANNELS];
153 target_sp_cfg_t target_sp[N_CHANNELS];
154 input_system_config_flags_t target_sp_flags[N_CHANNELS];
155 target_strm2mem_cfg_t target_strm2mem[N_CHANNELS];
156 input_system_config_flags_t target_strm2mem_flags[N_CHANNELS];
157
158 input_system_config_flags_t session_flags;
159
160};
161
162
163
164
165#define _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX
166#define _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX
167#define _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX
168#define _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX
169#define _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX
170
171#define _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX
172#define _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX
173#define _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX
174
175
176
177#define _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX
178#define _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX
179#define _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX
180#define _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX
181#define _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX
182#define _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX
183#define _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX
184#define _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX
185#define _HRT_CSS_RECEIVER_RAW18_REG_IDX _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX
186#define _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX
187#define _HRT_CSS_RECEIVER_RAW16_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX
188
189
190#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX
191#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX
192#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX
193#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX
194#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX
195#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX
196#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX
197#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX
198
199
200#define _HRT_CSS_BE_OFFSET 448
201#define _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX + _HRT_CSS_BE_OFFSET)
202#define _HRT_CSS_RECEIVER_BE_SRST_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX + _HRT_CSS_BE_OFFSET)
203#define _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX + _HRT_CSS_BE_OFFSET)
204#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX + _HRT_CSS_BE_OFFSET)
205#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX + _HRT_CSS_BE_OFFSET)
206#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX + _HRT_CSS_BE_OFFSET)
207#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX + _HRT_CSS_BE_OFFSET)
208#define _HRT_CSS_RECEIVER_BE_SEL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX + _HRT_CSS_BE_OFFSET)
209#define _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET)
210#define _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET)
211#define _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX + _HRT_CSS_BE_OFFSET)
212#define _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX + _HRT_CSS_BE_OFFSET)
213#define _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX + _HRT_CSS_BE_OFFSET)
214
215#define _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT
216#define _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT
217#define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT
218#define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT
219#define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT
220#define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT
221#define _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT
222#define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT
223#define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT
224#define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT
225#define _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT
226#define _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT
227#define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT
228#define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT
229#define _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT
230#define _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT
231#define _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT
232
233#define _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX
234#define _HRT_CSS_RECEIVER_DATA_TIMEOUT_IDX _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX
235#define _HRT_CSS_RECEIVER_DATA_TIMEOUT_BITS _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS
236
237typedef struct capture_unit_state_s capture_unit_state_t;
238typedef struct acquisition_unit_state_s acquisition_unit_state_t;
239typedef struct ctrl_unit_state_s ctrl_unit_state_t;
240
241
242
243
244
245
246
247
248
249
250
251
252typedef enum {
253 MONO_4L_1L_0L = 0,
254 MONO_3L_1L_0L,
255 MONO_2L_1L_0L,
256 MONO_1L_1L_0L,
257 STEREO_2L_1L_2L,
258 STEREO_3L_1L_1L,
259 STEREO_2L_1L_1L,
260 STEREO_1L_1L_1L,
261 N_RX_MODE
262} rx_mode_t;
263
264typedef enum {
265 MIPI_PREDICTOR_NONE = 0,
266 MIPI_PREDICTOR_TYPE1,
267 MIPI_PREDICTOR_TYPE2,
268 N_MIPI_PREDICTOR_TYPES
269} mipi_predictor_t;
270
271typedef enum {
272 MIPI_COMPRESSOR_NONE = 0,
273 MIPI_COMPRESSOR_10_6_10,
274 MIPI_COMPRESSOR_10_7_10,
275 MIPI_COMPRESSOR_10_8_10,
276 MIPI_COMPRESSOR_12_6_12,
277 MIPI_COMPRESSOR_12_7_12,
278 MIPI_COMPRESSOR_12_8_12,
279 N_MIPI_COMPRESSOR_METHODS
280} mipi_compressor_t;
281
282typedef enum {
283 MIPI_FORMAT_RGB888 = 0,
284 MIPI_FORMAT_RGB555,
285 MIPI_FORMAT_RGB444,
286 MIPI_FORMAT_RGB565,
287 MIPI_FORMAT_RGB666,
288 MIPI_FORMAT_RAW8,
289 MIPI_FORMAT_RAW10,
290 MIPI_FORMAT_RAW6,
291 MIPI_FORMAT_RAW7,
292 MIPI_FORMAT_RAW12,
293 MIPI_FORMAT_RAW14,
294 MIPI_FORMAT_YUV420_8,
295 MIPI_FORMAT_YUV420_10,
296 MIPI_FORMAT_YUV422_8,
297 MIPI_FORMAT_YUV422_10,
298 MIPI_FORMAT_CUSTOM0,
299 MIPI_FORMAT_YUV420_8_LEGACY,
300 MIPI_FORMAT_EMBEDDED,
301 MIPI_FORMAT_CUSTOM1,
302 MIPI_FORMAT_CUSTOM2,
303 MIPI_FORMAT_CUSTOM3,
304 MIPI_FORMAT_CUSTOM4,
305 MIPI_FORMAT_CUSTOM5,
306 MIPI_FORMAT_CUSTOM6,
307 MIPI_FORMAT_CUSTOM7,
308 MIPI_FORMAT_YUV420_8_SHIFT,
309 MIPI_FORMAT_YUV420_10_SHIFT,
310 MIPI_FORMAT_RAW16,
311 MIPI_FORMAT_RAW18,
312 N_MIPI_FORMAT,
313} mipi_format_t;
314
315#define MIPI_FORMAT_JPEG MIPI_FORMAT_CUSTOM0
316#define MIPI_FORMAT_BINARY_8 MIPI_FORMAT_CUSTOM0
317#define N_MIPI_FORMAT_CUSTOM 8
318
319
320#define N_MIPI_COMPRESSOR_CONTEXT (N_RX_CHANNEL_ID * N_MIPI_FORMAT_CUSTOM)
321
322typedef enum {
323 RX_IRQ_INFO_BUFFER_OVERRUN = 1UL << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT,
324 RX_IRQ_INFO_INIT_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT,
325 RX_IRQ_INFO_ENTER_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT,
326 RX_IRQ_INFO_EXIT_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT,
327 RX_IRQ_INFO_ECC_CORRECTED = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT,
328 RX_IRQ_INFO_ERR_SOT = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT,
329 RX_IRQ_INFO_ERR_SOT_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT,
330 RX_IRQ_INFO_ERR_CONTROL = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT,
331 RX_IRQ_INFO_ERR_ECC_DOUBLE = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT,
332
333 RX_IRQ_INFO_ERR_CRC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT,
334 RX_IRQ_INFO_ERR_UNKNOWN_ID = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT,
335 RX_IRQ_INFO_ERR_FRAME_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT,
336 RX_IRQ_INFO_ERR_FRAME_DATA = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT,
337 RX_IRQ_INFO_ERR_DATA_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT,
338 RX_IRQ_INFO_ERR_UNKNOWN_ESC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT,
339 RX_IRQ_INFO_ERR_LINE_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT,
340} rx_irq_info_t;
341
342typedef struct rx_cfg_s rx_cfg_t;
343
344
345
346
347struct rx_cfg_s {
348 rx_mode_t mode;
349 enum mipi_port_id port;
350 unsigned int timeout;
351 unsigned int initcount;
352 unsigned int synccount;
353 unsigned int rxcount;
354 mipi_predictor_t comp;
355 bool is_two_ppc;
356};
357
358
359static const hrt_address __maybe_unused MIPI_PORT_OFFSET[N_MIPI_PORT_ID] = {
360 0x00000000UL,
361 0x00000100UL,
362 0x00000200UL
363};
364
365static const hrt_address __maybe_unused SUB_SYSTEM_OFFSET[N_SUB_SYSTEM_ID] = {
366 0x00001000UL,
367 0x00002000UL,
368 0x00003000UL,
369 0x00004000UL,
370 0x00005000UL,
371 0x00009000UL,
372 0x0000A000UL,
373 0x0000B000UL,
374 0x0000C000UL
375};
376
377struct capture_unit_state_s {
378 int Packet_Length;
379 int Received_Length;
380 int Received_Short_Packets;
381 int Received_Long_Packets;
382 int Last_Command;
383 int Next_Command;
384 int Last_Acknowledge;
385 int Next_Acknowledge;
386 int FSM_State_Info;
387 int StartMode;
388 int Start_Addr;
389 int Mem_Region_Size;
390 int Num_Mem_Regions;
391
392
393
394};
395
396struct acquisition_unit_state_s {
397
398 int Received_Short_Packets;
399 int Received_Long_Packets;
400 int Last_Command;
401 int Next_Command;
402 int Last_Acknowledge;
403 int Next_Acknowledge;
404 int FSM_State_Info;
405 int Int_Cntr_Info;
406 int Start_Addr;
407 int Mem_Region_Size;
408 int Num_Mem_Regions;
409};
410
411struct ctrl_unit_state_s {
412 int last_cmd;
413 int next_cmd;
414 int last_ack;
415 int next_ack;
416 int top_fsm_state;
417 int captA_fsm_state;
418 int captB_fsm_state;
419 int captC_fsm_state;
420 int acq_fsm_state;
421 int captA_start_addr;
422 int captB_start_addr;
423 int captC_start_addr;
424 int captA_mem_region_size;
425 int captB_mem_region_size;
426 int captC_mem_region_size;
427 int captA_num_mem_regions;
428 int captB_num_mem_regions;
429 int captC_num_mem_regions;
430 int acq_start_addr;
431 int acq_mem_region_size;
432 int acq_num_mem_regions;
433
434 int capt_reserve_one_mem_region;
435};
436
437struct input_system_state_s {
438 int str_multicastA_sel;
439 int str_multicastB_sel;
440 int str_multicastC_sel;
441 int str_mux_sel;
442 int str_mon_status;
443 int str_mon_irq_cond;
444 int str_mon_irq_en;
445 int isys_srst;
446 int isys_slv_reg_srst;
447 int str_deint_portA_cnt;
448 int str_deint_portB_cnt;
449 struct capture_unit_state_s capture_unit[N_CAPTURE_UNIT_ID];
450 struct acquisition_unit_state_s acquisition_unit[N_ACQUISITION_UNIT_ID];
451 struct ctrl_unit_state_s ctrl_unit_state[N_CTRL_UNIT_ID];
452};
453
454struct mipi_port_state_s {
455 int device_ready;
456 int irq_status;
457 int irq_enable;
458 u32 timeout_count;
459 u16 init_count;
460 u16 raw16_18;
461 u32 sync_count;
462 u32 rx_count;
463 u8 lane_sync_count[MIPI_4LANE_CFG];
464 u8 lane_rx_count[MIPI_4LANE_CFG];
465};
466
467struct rx_channel_state_s {
468 u32 comp_scheme0;
469 u32 comp_scheme1;
470 mipi_predictor_t pred[N_MIPI_FORMAT_CUSTOM];
471 mipi_compressor_t comp[N_MIPI_FORMAT_CUSTOM];
472};
473
474struct receiver_state_s {
475 u8 fs_to_ls_delay;
476 u8 ls_to_data_delay;
477 u8 data_to_le_delay;
478 u8 le_to_fe_delay;
479 u8 fe_to_fs_delay;
480 u8 le_to_fs_delay;
481 bool is_two_ppc;
482 int backend_rst;
483 u16 raw18;
484 bool force_raw8;
485 u16 raw16;
486 struct mipi_port_state_s mipi_port_state[N_MIPI_PORT_ID];
487 struct rx_channel_state_s rx_channel_state[N_RX_CHANNEL_ID];
488 int be_gsp_acc_ovl;
489 int be_srst;
490 int be_is_two_ppc;
491 int be_comp_format0;
492 int be_comp_format1;
493 int be_comp_format2;
494 int be_comp_format3;
495 int be_sel;
496 int be_raw16_config;
497 int be_raw18_config;
498 int be_force_raw8;
499 int be_irq_status;
500 int be_irq_clear;
501};
502
503#endif
504